1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <spi.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 15 16 #ifdef CONFIG_MX27 17 /* i.MX27 has a completely wrong register layout and register definitions in the 18 * datasheet, the correct one is in the Freescale's Linux driver */ 19 20 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ 21 "See linux mxc_spi driver from Freescale for details." 22 #endif 23 24 static unsigned long spi_bases[] = { 25 MXC_SPI_BASE_ADDRESSES 26 }; 27 28 #define OUT MXC_GPIO_DIRECTION_OUT 29 30 #define reg_read readl 31 #define reg_write(a, v) writel(v, a) 32 33 struct mxc_spi_slave { 34 struct spi_slave slave; 35 unsigned long base; 36 u32 ctrl_reg; 37 #if defined(MXC_ECSPI) 38 u32 cfg_reg; 39 #endif 40 int gpio; 41 int ss_pol; 42 }; 43 44 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 45 { 46 return container_of(slave, struct mxc_spi_slave, slave); 47 } 48 49 void spi_cs_activate(struct spi_slave *slave) 50 { 51 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 52 if (mxcs->gpio > 0) 53 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 54 } 55 56 void spi_cs_deactivate(struct spi_slave *slave) 57 { 58 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 59 if (mxcs->gpio > 0) 60 gpio_set_value(mxcs->gpio, 61 !(mxcs->ss_pol)); 62 } 63 64 u32 get_cspi_div(u32 div) 65 { 66 int i; 67 68 for (i = 0; i < 8; i++) { 69 if (div <= (4 << i)) 70 return i; 71 } 72 return i; 73 } 74 75 #ifdef MXC_CSPI 76 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 77 unsigned int max_hz, unsigned int mode) 78 { 79 unsigned int ctrl_reg; 80 u32 clk_src; 81 u32 div; 82 83 clk_src = mxc_get_clock(MXC_CSPI_CLK); 84 85 div = DIV_ROUND_UP(clk_src, max_hz); 86 div = get_cspi_div(div); 87 88 debug("clk %d Hz, div %d, real clk %d Hz\n", 89 max_hz, div, clk_src / (4 << div)); 90 91 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 92 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 93 MXC_CSPICTRL_DATARATE(div) | 94 MXC_CSPICTRL_EN | 95 #ifdef CONFIG_MX35 96 MXC_CSPICTRL_SSCTL | 97 #endif 98 MXC_CSPICTRL_MODE; 99 100 if (mode & SPI_CPHA) 101 ctrl_reg |= MXC_CSPICTRL_PHA; 102 if (mode & SPI_CPOL) 103 ctrl_reg |= MXC_CSPICTRL_POL; 104 if (mode & SPI_CS_HIGH) 105 ctrl_reg |= MXC_CSPICTRL_SSPOL; 106 mxcs->ctrl_reg = ctrl_reg; 107 108 return 0; 109 } 110 #endif 111 112 #ifdef MXC_ECSPI 113 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 114 unsigned int max_hz, unsigned int mode) 115 { 116 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 117 s32 reg_ctrl, reg_config; 118 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; 119 u32 pre_div = 0, post_div = 0; 120 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 121 122 if (max_hz == 0) { 123 printf("Error: desired clock is 0\n"); 124 return -1; 125 } 126 127 /* 128 * Reset SPI and set all CSs to master mode, if toggling 129 * between slave and master mode we might see a glitch 130 * on the clock line 131 */ 132 reg_ctrl = MXC_CSPICTRL_MODE_MASK; 133 reg_write(®s->ctrl, reg_ctrl); 134 reg_ctrl |= MXC_CSPICTRL_EN; 135 reg_write(®s->ctrl, reg_ctrl); 136 137 if (clk_src > max_hz) { 138 pre_div = (clk_src - 1) / max_hz; 139 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ 140 post_div = fls(pre_div); 141 if (post_div > 4) { 142 post_div -= 4; 143 if (post_div >= 16) { 144 printf("Error: no divider for the freq: %d\n", 145 max_hz); 146 return -1; 147 } 148 pre_div >>= post_div; 149 } else { 150 post_div = 0; 151 } 152 } 153 154 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 155 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 156 MXC_CSPICTRL_SELCHAN(cs); 157 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 158 MXC_CSPICTRL_PREDIV(pre_div); 159 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 160 MXC_CSPICTRL_POSTDIV(post_div); 161 162 /* We need to disable SPI before changing registers */ 163 reg_ctrl &= ~MXC_CSPICTRL_EN; 164 165 if (mode & SPI_CS_HIGH) 166 ss_pol = 1; 167 168 if (mode & SPI_CPOL) { 169 sclkpol = 1; 170 sclkctl = 1; 171 } 172 173 if (mode & SPI_CPHA) 174 sclkpha = 1; 175 176 reg_config = reg_read(®s->cfg); 177 178 /* 179 * Configuration register setup 180 * The MX51 supports different setup for each SS 181 */ 182 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 183 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 184 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 185 (sclkpol << (cs + MXC_CSPICON_POL)); 186 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | 187 (sclkctl << (cs + MXC_CSPICON_CTL)); 188 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 189 (sclkpha << (cs + MXC_CSPICON_PHA)); 190 191 debug("reg_ctrl = 0x%x\n", reg_ctrl); 192 reg_write(®s->ctrl, reg_ctrl); 193 debug("reg_config = 0x%x\n", reg_config); 194 reg_write(®s->cfg, reg_config); 195 196 /* save config register and control register */ 197 mxcs->ctrl_reg = reg_ctrl; 198 mxcs->cfg_reg = reg_config; 199 200 /* clear interrupt reg */ 201 reg_write(®s->intr, 0); 202 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 203 204 return 0; 205 } 206 #endif 207 208 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 209 const u8 *dout, u8 *din, unsigned long flags) 210 { 211 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 212 int nbytes = DIV_ROUND_UP(bitlen, 8); 213 u32 data, cnt, i; 214 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 215 216 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 217 __func__, bitlen, (u32)dout, (u32)din); 218 219 mxcs->ctrl_reg = (mxcs->ctrl_reg & 220 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 221 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 222 223 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 224 #ifdef MXC_ECSPI 225 reg_write(®s->cfg, mxcs->cfg_reg); 226 #endif 227 228 /* Clear interrupt register */ 229 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 230 231 /* 232 * The SPI controller works only with words, 233 * check if less than a word is sent. 234 * Access to the FIFO is only 32 bit 235 */ 236 if (bitlen % 32) { 237 data = 0; 238 cnt = (bitlen % 32) / 8; 239 if (dout) { 240 for (i = 0; i < cnt; i++) { 241 data = (data << 8) | (*dout++ & 0xFF); 242 } 243 } 244 debug("Sending SPI 0x%x\n", data); 245 246 reg_write(®s->txdata, data); 247 nbytes -= cnt; 248 } 249 250 data = 0; 251 252 while (nbytes > 0) { 253 data = 0; 254 if (dout) { 255 /* Buffer is not 32-bit aligned */ 256 if ((unsigned long)dout & 0x03) { 257 data = 0; 258 for (i = 0; i < 4; i++) 259 data = (data << 8) | (*dout++ & 0xFF); 260 } else { 261 data = *(u32 *)dout; 262 data = cpu_to_be32(data); 263 dout += 4; 264 } 265 } 266 debug("Sending SPI 0x%x\n", data); 267 reg_write(®s->txdata, data); 268 nbytes -= 4; 269 } 270 271 /* FIFO is written, now starts the transfer setting the XCH bit */ 272 reg_write(®s->ctrl, mxcs->ctrl_reg | 273 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 274 275 /* Wait until the TC (Transfer completed) bit is set */ 276 while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) 277 ; 278 279 /* Transfer completed, clear any pending request */ 280 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 281 282 nbytes = DIV_ROUND_UP(bitlen, 8); 283 284 cnt = nbytes % 32; 285 286 if (bitlen % 32) { 287 data = reg_read(®s->rxdata); 288 cnt = (bitlen % 32) / 8; 289 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 290 debug("SPI Rx unaligned: 0x%x\n", data); 291 if (din) { 292 memcpy(din, &data, cnt); 293 din += cnt; 294 } 295 nbytes -= cnt; 296 } 297 298 while (nbytes > 0) { 299 u32 tmp; 300 tmp = reg_read(®s->rxdata); 301 data = cpu_to_be32(tmp); 302 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 303 cnt = min(nbytes, sizeof(data)); 304 if (din) { 305 memcpy(din, &data, cnt); 306 din += cnt; 307 } 308 nbytes -= cnt; 309 } 310 311 return 0; 312 313 } 314 315 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 316 void *din, unsigned long flags) 317 { 318 int n_bytes = DIV_ROUND_UP(bitlen, 8); 319 int n_bits; 320 int ret; 321 u32 blk_size; 322 u8 *p_outbuf = (u8 *)dout; 323 u8 *p_inbuf = (u8 *)din; 324 325 if (!slave) 326 return -1; 327 328 if (flags & SPI_XFER_BEGIN) 329 spi_cs_activate(slave); 330 331 while (n_bytes > 0) { 332 if (n_bytes < MAX_SPI_BYTES) 333 blk_size = n_bytes; 334 else 335 blk_size = MAX_SPI_BYTES; 336 337 n_bits = blk_size * 8; 338 339 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 340 341 if (ret) 342 return ret; 343 if (dout) 344 p_outbuf += blk_size; 345 if (din) 346 p_inbuf += blk_size; 347 n_bytes -= blk_size; 348 } 349 350 if (flags & SPI_XFER_END) { 351 spi_cs_deactivate(slave); 352 } 353 354 return 0; 355 } 356 357 void spi_init(void) 358 { 359 } 360 361 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 362 { 363 int ret; 364 365 /* 366 * Some SPI devices require active chip-select over multiple 367 * transactions, we achieve this using a GPIO. Still, the SPI 368 * controller has to be configured to use one of its own chipselects. 369 * To use this feature you have to call spi_setup_slave() with 370 * cs = internal_cs | (gpio << 8), and you have to use some unused 371 * on this SPI controller cs between 0 and 3. 372 */ 373 if (cs > 3) { 374 mxcs->gpio = cs >> 8; 375 cs &= 3; 376 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); 377 if (ret) { 378 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 379 return -EINVAL; 380 } 381 } else { 382 mxcs->gpio = -1; 383 } 384 385 return cs; 386 } 387 388 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 389 unsigned int max_hz, unsigned int mode) 390 { 391 struct mxc_spi_slave *mxcs; 392 int ret; 393 394 if (bus >= ARRAY_SIZE(spi_bases)) 395 return NULL; 396 397 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); 398 if (!mxcs) { 399 puts("mxc_spi: SPI Slave not allocated !\n"); 400 return NULL; 401 } 402 403 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 404 405 ret = decode_cs(mxcs, cs); 406 if (ret < 0) { 407 free(mxcs); 408 return NULL; 409 } 410 411 cs = ret; 412 413 mxcs->base = spi_bases[bus]; 414 415 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 416 if (ret) { 417 printf("mxc_spi: cannot setup SPI controller\n"); 418 free(mxcs); 419 return NULL; 420 } 421 return &mxcs->slave; 422 } 423 424 void spi_free_slave(struct spi_slave *slave) 425 { 426 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 427 428 free(mxcs); 429 } 430 431 int spi_claim_bus(struct spi_slave *slave) 432 { 433 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 434 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 435 436 reg_write(®s->rxdata, 1); 437 udelay(1); 438 reg_write(®s->ctrl, mxcs->ctrl_reg); 439 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 440 reg_write(®s->intr, 0); 441 442 return 0; 443 } 444 445 void spi_release_bus(struct spi_slave *slave) 446 { 447 /* TODO: Shut the controller down */ 448 } 449