1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <spi.h> 10 #include <asm/errno.h> 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/clock.h> 15 16 #ifdef CONFIG_MX27 17 /* i.MX27 has a completely wrong register layout and register definitions in the 18 * datasheet, the correct one is in the Freescale's Linux driver */ 19 20 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ 21 "See linux mxc_spi driver from Freescale for details." 22 #endif 23 24 static unsigned long spi_bases[] = { 25 MXC_SPI_BASE_ADDRESSES 26 }; 27 28 #define OUT MXC_GPIO_DIRECTION_OUT 29 30 #define reg_read readl 31 #define reg_write(a, v) writel(v, a) 32 33 #if !defined(CONFIG_SYS_SPI_MXC_WAIT) 34 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ 35 #endif 36 37 struct mxc_spi_slave { 38 struct spi_slave slave; 39 unsigned long base; 40 u32 ctrl_reg; 41 #if defined(MXC_ECSPI) 42 u32 cfg_reg; 43 #endif 44 int gpio; 45 int ss_pol; 46 }; 47 48 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 49 { 50 return container_of(slave, struct mxc_spi_slave, slave); 51 } 52 53 void spi_cs_activate(struct spi_slave *slave) 54 { 55 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 56 if (mxcs->gpio > 0) 57 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 58 } 59 60 void spi_cs_deactivate(struct spi_slave *slave) 61 { 62 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 63 if (mxcs->gpio > 0) 64 gpio_set_value(mxcs->gpio, 65 !(mxcs->ss_pol)); 66 } 67 68 u32 get_cspi_div(u32 div) 69 { 70 int i; 71 72 for (i = 0; i < 8; i++) { 73 if (div <= (4 << i)) 74 return i; 75 } 76 return i; 77 } 78 79 #ifdef MXC_CSPI 80 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 81 unsigned int max_hz, unsigned int mode) 82 { 83 unsigned int ctrl_reg; 84 u32 clk_src; 85 u32 div; 86 87 clk_src = mxc_get_clock(MXC_CSPI_CLK); 88 89 div = DIV_ROUND_UP(clk_src, max_hz); 90 div = get_cspi_div(div); 91 92 debug("clk %d Hz, div %d, real clk %d Hz\n", 93 max_hz, div, clk_src / (4 << div)); 94 95 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 96 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 97 MXC_CSPICTRL_DATARATE(div) | 98 MXC_CSPICTRL_EN | 99 #ifdef CONFIG_MX35 100 MXC_CSPICTRL_SSCTL | 101 #endif 102 MXC_CSPICTRL_MODE; 103 104 if (mode & SPI_CPHA) 105 ctrl_reg |= MXC_CSPICTRL_PHA; 106 if (mode & SPI_CPOL) 107 ctrl_reg |= MXC_CSPICTRL_POL; 108 if (mode & SPI_CS_HIGH) 109 ctrl_reg |= MXC_CSPICTRL_SSPOL; 110 mxcs->ctrl_reg = ctrl_reg; 111 112 return 0; 113 } 114 #endif 115 116 #ifdef MXC_ECSPI 117 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 118 unsigned int max_hz, unsigned int mode) 119 { 120 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 121 s32 reg_ctrl, reg_config; 122 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; 123 u32 pre_div = 0, post_div = 0; 124 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 125 126 if (max_hz == 0) { 127 printf("Error: desired clock is 0\n"); 128 return -1; 129 } 130 131 /* 132 * Reset SPI and set all CSs to master mode, if toggling 133 * between slave and master mode we might see a glitch 134 * on the clock line 135 */ 136 reg_ctrl = MXC_CSPICTRL_MODE_MASK; 137 reg_write(®s->ctrl, reg_ctrl); 138 reg_ctrl |= MXC_CSPICTRL_EN; 139 reg_write(®s->ctrl, reg_ctrl); 140 141 if (clk_src > max_hz) { 142 pre_div = (clk_src - 1) / max_hz; 143 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ 144 post_div = fls(pre_div); 145 if (post_div > 4) { 146 post_div -= 4; 147 if (post_div >= 16) { 148 printf("Error: no divider for the freq: %d\n", 149 max_hz); 150 return -1; 151 } 152 pre_div >>= post_div; 153 } else { 154 post_div = 0; 155 } 156 } 157 158 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 159 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 160 MXC_CSPICTRL_SELCHAN(cs); 161 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 162 MXC_CSPICTRL_PREDIV(pre_div); 163 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 164 MXC_CSPICTRL_POSTDIV(post_div); 165 166 /* We need to disable SPI before changing registers */ 167 reg_ctrl &= ~MXC_CSPICTRL_EN; 168 169 if (mode & SPI_CS_HIGH) 170 ss_pol = 1; 171 172 if (mode & SPI_CPOL) { 173 sclkpol = 1; 174 sclkctl = 1; 175 } 176 177 if (mode & SPI_CPHA) 178 sclkpha = 1; 179 180 reg_config = reg_read(®s->cfg); 181 182 /* 183 * Configuration register setup 184 * The MX51 supports different setup for each SS 185 */ 186 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 187 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 188 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 189 (sclkpol << (cs + MXC_CSPICON_POL)); 190 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | 191 (sclkctl << (cs + MXC_CSPICON_CTL)); 192 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 193 (sclkpha << (cs + MXC_CSPICON_PHA)); 194 195 debug("reg_ctrl = 0x%x\n", reg_ctrl); 196 reg_write(®s->ctrl, reg_ctrl); 197 debug("reg_config = 0x%x\n", reg_config); 198 reg_write(®s->cfg, reg_config); 199 200 /* save config register and control register */ 201 mxcs->ctrl_reg = reg_ctrl; 202 mxcs->cfg_reg = reg_config; 203 204 /* clear interrupt reg */ 205 reg_write(®s->intr, 0); 206 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 207 208 return 0; 209 } 210 #endif 211 212 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 213 const u8 *dout, u8 *din, unsigned long flags) 214 { 215 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 216 int nbytes = DIV_ROUND_UP(bitlen, 8); 217 u32 data, cnt, i; 218 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 219 u32 ts; 220 int status; 221 222 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 223 __func__, bitlen, (u32)dout, (u32)din); 224 225 mxcs->ctrl_reg = (mxcs->ctrl_reg & 226 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 227 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 228 229 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 230 #ifdef MXC_ECSPI 231 reg_write(®s->cfg, mxcs->cfg_reg); 232 #endif 233 234 /* Clear interrupt register */ 235 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 236 237 /* 238 * The SPI controller works only with words, 239 * check if less than a word is sent. 240 * Access to the FIFO is only 32 bit 241 */ 242 if (bitlen % 32) { 243 data = 0; 244 cnt = (bitlen % 32) / 8; 245 if (dout) { 246 for (i = 0; i < cnt; i++) { 247 data = (data << 8) | (*dout++ & 0xFF); 248 } 249 } 250 debug("Sending SPI 0x%x\n", data); 251 252 reg_write(®s->txdata, data); 253 nbytes -= cnt; 254 } 255 256 data = 0; 257 258 while (nbytes > 0) { 259 data = 0; 260 if (dout) { 261 /* Buffer is not 32-bit aligned */ 262 if ((unsigned long)dout & 0x03) { 263 data = 0; 264 for (i = 0; i < 4; i++) 265 data = (data << 8) | (*dout++ & 0xFF); 266 } else { 267 data = *(u32 *)dout; 268 data = cpu_to_be32(data); 269 dout += 4; 270 } 271 } 272 debug("Sending SPI 0x%x\n", data); 273 reg_write(®s->txdata, data); 274 nbytes -= 4; 275 } 276 277 /* FIFO is written, now starts the transfer setting the XCH bit */ 278 reg_write(®s->ctrl, mxcs->ctrl_reg | 279 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 280 281 ts = get_timer(0); 282 status = reg_read(®s->stat); 283 /* Wait until the TC (Transfer completed) bit is set */ 284 while ((status & MXC_CSPICTRL_TC) == 0) { 285 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { 286 printf("spi_xchg_single: Timeout!\n"); 287 return -1; 288 } 289 status = reg_read(®s->stat); 290 } 291 292 /* Transfer completed, clear any pending request */ 293 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 294 295 nbytes = DIV_ROUND_UP(bitlen, 8); 296 297 cnt = nbytes % 32; 298 299 if (bitlen % 32) { 300 data = reg_read(®s->rxdata); 301 cnt = (bitlen % 32) / 8; 302 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 303 debug("SPI Rx unaligned: 0x%x\n", data); 304 if (din) { 305 memcpy(din, &data, cnt); 306 din += cnt; 307 } 308 nbytes -= cnt; 309 } 310 311 while (nbytes > 0) { 312 u32 tmp; 313 tmp = reg_read(®s->rxdata); 314 data = cpu_to_be32(tmp); 315 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 316 cnt = min(nbytes, sizeof(data)); 317 if (din) { 318 memcpy(din, &data, cnt); 319 din += cnt; 320 } 321 nbytes -= cnt; 322 } 323 324 return 0; 325 326 } 327 328 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 329 void *din, unsigned long flags) 330 { 331 int n_bytes = DIV_ROUND_UP(bitlen, 8); 332 int n_bits; 333 int ret; 334 u32 blk_size; 335 u8 *p_outbuf = (u8 *)dout; 336 u8 *p_inbuf = (u8 *)din; 337 338 if (!slave) 339 return -1; 340 341 if (flags & SPI_XFER_BEGIN) 342 spi_cs_activate(slave); 343 344 while (n_bytes > 0) { 345 if (n_bytes < MAX_SPI_BYTES) 346 blk_size = n_bytes; 347 else 348 blk_size = MAX_SPI_BYTES; 349 350 n_bits = blk_size * 8; 351 352 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 353 354 if (ret) 355 return ret; 356 if (dout) 357 p_outbuf += blk_size; 358 if (din) 359 p_inbuf += blk_size; 360 n_bytes -= blk_size; 361 } 362 363 if (flags & SPI_XFER_END) { 364 spi_cs_deactivate(slave); 365 } 366 367 return 0; 368 } 369 370 void spi_init(void) 371 { 372 } 373 374 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 375 { 376 int ret; 377 378 /* 379 * Some SPI devices require active chip-select over multiple 380 * transactions, we achieve this using a GPIO. Still, the SPI 381 * controller has to be configured to use one of its own chipselects. 382 * To use this feature you have to call spi_setup_slave() with 383 * cs = internal_cs | (gpio << 8), and you have to use some unused 384 * on this SPI controller cs between 0 and 3. 385 */ 386 if (cs > 3) { 387 mxcs->gpio = cs >> 8; 388 cs &= 3; 389 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); 390 if (ret) { 391 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 392 return -EINVAL; 393 } 394 } else { 395 mxcs->gpio = -1; 396 } 397 398 return cs; 399 } 400 401 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 402 unsigned int max_hz, unsigned int mode) 403 { 404 struct mxc_spi_slave *mxcs; 405 int ret; 406 407 if (bus >= ARRAY_SIZE(spi_bases)) 408 return NULL; 409 410 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); 411 if (!mxcs) { 412 puts("mxc_spi: SPI Slave not allocated !\n"); 413 return NULL; 414 } 415 416 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 417 418 ret = decode_cs(mxcs, cs); 419 if (ret < 0) { 420 free(mxcs); 421 return NULL; 422 } 423 424 cs = ret; 425 426 mxcs->base = spi_bases[bus]; 427 428 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 429 if (ret) { 430 printf("mxc_spi: cannot setup SPI controller\n"); 431 free(mxcs); 432 return NULL; 433 } 434 return &mxcs->slave; 435 } 436 437 void spi_free_slave(struct spi_slave *slave) 438 { 439 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 440 441 free(mxcs); 442 } 443 444 int spi_claim_bus(struct spi_slave *slave) 445 { 446 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 447 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 448 449 reg_write(®s->rxdata, 1); 450 udelay(1); 451 reg_write(®s->ctrl, mxcs->ctrl_reg); 452 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 453 reg_write(®s->intr, 0); 454 455 return 0; 456 } 457 458 void spi_release_bus(struct spi_slave *slave) 459 { 460 /* TODO: Shut the controller down */ 461 } 462