1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #include <common.h> 22 #include <malloc.h> 23 #include <spi.h> 24 #include <asm/errno.h> 25 #include <asm/io.h> 26 #include <asm/gpio.h> 27 #include <asm/arch/imx-regs.h> 28 #include <asm/arch/clock.h> 29 30 #ifdef CONFIG_MX27 31 /* i.MX27 has a completely wrong register layout and register definitions in the 32 * datasheet, the correct one is in the Freescale's Linux driver */ 33 34 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ 35 "See linux mxc_spi driver from Freescale for details." 36 37 #elif defined(CONFIG_MX31) 38 39 #define MXC_CSPICTRL_EN (1 << 0) 40 #define MXC_CSPICTRL_MODE (1 << 1) 41 #define MXC_CSPICTRL_XCH (1 << 2) 42 #define MXC_CSPICTRL_SMC (1 << 3) 43 #define MXC_CSPICTRL_POL (1 << 4) 44 #define MXC_CSPICTRL_PHA (1 << 5) 45 #define MXC_CSPICTRL_SSCTL (1 << 6) 46 #define MXC_CSPICTRL_SSPOL (1 << 7) 47 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 48 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 49 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 50 #define MXC_CSPICTRL_TC (1 << 8) 51 #define MXC_CSPICTRL_RXOVF (1 << 6) 52 #define MXC_CSPICTRL_MAXBITS 0x1f 53 54 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 55 #define MAX_SPI_BYTES 4 56 57 static unsigned long spi_bases[] = { 58 0x43fa4000, 59 0x50010000, 60 0x53f84000, 61 }; 62 63 #elif defined(CONFIG_MX51) 64 65 #define MXC_CSPICTRL_EN (1 << 0) 66 #define MXC_CSPICTRL_MODE (1 << 1) 67 #define MXC_CSPICTRL_XCH (1 << 2) 68 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 69 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 70 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 71 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 72 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 73 #define MXC_CSPICTRL_MAXBITS 0xfff 74 #define MXC_CSPICTRL_TC (1 << 7) 75 #define MXC_CSPICTRL_RXOVF (1 << 6) 76 77 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 78 #define MAX_SPI_BYTES 32 79 80 /* Bit position inside CTRL register to be associated with SS */ 81 #define MXC_CSPICTRL_CHAN 18 82 83 /* Bit position inside CON register to be associated with SS */ 84 #define MXC_CSPICON_POL 4 85 #define MXC_CSPICON_PHA 0 86 #define MXC_CSPICON_SSPOL 12 87 88 static unsigned long spi_bases[] = { 89 CSPI1_BASE_ADDR, 90 CSPI2_BASE_ADDR, 91 CSPI3_BASE_ADDR, 92 }; 93 94 #elif defined(CONFIG_MX35) 95 96 #define MXC_CSPICTRL_EN (1 << 0) 97 #define MXC_CSPICTRL_MODE (1 << 1) 98 #define MXC_CSPICTRL_XCH (1 << 2) 99 #define MXC_CSPICTRL_SMC (1 << 3) 100 #define MXC_CSPICTRL_POL (1 << 4) 101 #define MXC_CSPICTRL_PHA (1 << 5) 102 #define MXC_CSPICTRL_SSCTL (1 << 6) 103 #define MXC_CSPICTRL_SSPOL (1 << 7) 104 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 105 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 106 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 107 #define MXC_CSPICTRL_TC (1 << 7) 108 #define MXC_CSPICTRL_RXOVF (1 << 6) 109 #define MXC_CSPICTRL_MAXBITS 0xfff 110 111 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 112 #define MAX_SPI_BYTES 4 113 114 static unsigned long spi_bases[] = { 115 0x43fa4000, 116 0x50010000, 117 }; 118 119 #else 120 #error "Unsupported architecture" 121 #endif 122 123 #define OUT MXC_GPIO_DIRECTION_OUT 124 125 #define reg_read readl 126 #define reg_write(a, v) writel(v, a) 127 128 struct mxc_spi_slave { 129 struct spi_slave slave; 130 unsigned long base; 131 u32 ctrl_reg; 132 #if defined(CONFIG_MX51) 133 u32 cfg_reg; 134 #endif 135 int gpio; 136 int ss_pol; 137 }; 138 139 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) 140 { 141 return container_of(slave, struct mxc_spi_slave, slave); 142 } 143 144 void spi_cs_activate(struct spi_slave *slave) 145 { 146 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 147 if (mxcs->gpio > 0) 148 gpio_set_value(mxcs->gpio, mxcs->ss_pol); 149 } 150 151 void spi_cs_deactivate(struct spi_slave *slave) 152 { 153 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 154 if (mxcs->gpio > 0) 155 gpio_set_value(mxcs->gpio, 156 !(mxcs->ss_pol)); 157 } 158 159 u32 get_cspi_div(u32 div) 160 { 161 int i; 162 163 for (i = 0; i < 8; i++) { 164 if (div <= (4 << i)) 165 return i; 166 } 167 return i; 168 } 169 170 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) 171 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 172 unsigned int max_hz, unsigned int mode) 173 { 174 unsigned int ctrl_reg; 175 u32 clk_src; 176 u32 div; 177 178 clk_src = mxc_get_clock(MXC_CSPI_CLK); 179 180 div = clk_src / max_hz; 181 div = get_cspi_div(div); 182 183 debug("clk %d Hz, div %d, real clk %d Hz\n", 184 max_hz, div, clk_src / (4 << div)); 185 186 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 187 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | 188 MXC_CSPICTRL_DATARATE(div) | 189 MXC_CSPICTRL_EN | 190 #ifdef CONFIG_MX35 191 MXC_CSPICTRL_SSCTL | 192 #endif 193 MXC_CSPICTRL_MODE; 194 195 if (mode & SPI_CPHA) 196 ctrl_reg |= MXC_CSPICTRL_PHA; 197 if (mode & SPI_CPOL) 198 ctrl_reg |= MXC_CSPICTRL_POL; 199 if (mode & SPI_CS_HIGH) 200 ctrl_reg |= MXC_CSPICTRL_SSPOL; 201 mxcs->ctrl_reg = ctrl_reg; 202 203 return 0; 204 } 205 #endif 206 207 #if defined(CONFIG_MX51) 208 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, 209 unsigned int max_hz, unsigned int mode) 210 { 211 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); 212 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; 213 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; 214 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 215 216 if (max_hz == 0) { 217 printf("Error: desired clock is 0\n"); 218 return -1; 219 } 220 221 reg_ctrl = reg_read(®s->ctrl); 222 223 /* Reset spi */ 224 reg_write(®s->ctrl, 0); 225 reg_write(®s->ctrl, (reg_ctrl | 0x1)); 226 227 /* 228 * The following computation is taken directly from Freescale's code. 229 */ 230 if (clk_src > max_hz) { 231 pre_div = clk_src / max_hz; 232 if (pre_div > 16) { 233 post_div = pre_div / 16; 234 pre_div = 15; 235 } 236 if (post_div != 0) { 237 for (i = 0; i < 16; i++) { 238 if ((1 << i) >= post_div) 239 break; 240 } 241 if (i == 16) { 242 printf("Error: no divider for the freq: %d\n", 243 max_hz); 244 return -1; 245 } 246 post_div = i; 247 } 248 } 249 250 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); 251 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | 252 MXC_CSPICTRL_SELCHAN(cs); 253 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | 254 MXC_CSPICTRL_PREDIV(pre_div); 255 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | 256 MXC_CSPICTRL_POSTDIV(post_div); 257 258 /* always set to master mode */ 259 reg_ctrl |= 1 << (cs + 4); 260 261 /* We need to disable SPI before changing registers */ 262 reg_ctrl &= ~MXC_CSPICTRL_EN; 263 264 if (mode & SPI_CS_HIGH) 265 ss_pol = 1; 266 267 if (mode & SPI_CPOL) 268 sclkpol = 1; 269 270 if (mode & SPI_CPHA) 271 sclkpha = 1; 272 273 reg_config = reg_read(®s->cfg); 274 275 /* 276 * Configuration register setup 277 * The MX51 supports different setup for each SS 278 */ 279 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | 280 (ss_pol << (cs + MXC_CSPICON_SSPOL)); 281 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | 282 (sclkpol << (cs + MXC_CSPICON_POL)); 283 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | 284 (sclkpha << (cs + MXC_CSPICON_PHA)); 285 286 debug("reg_ctrl = 0x%x\n", reg_ctrl); 287 reg_write(®s->ctrl, reg_ctrl); 288 debug("reg_config = 0x%x\n", reg_config); 289 reg_write(®s->cfg, reg_config); 290 291 /* save config register and control register */ 292 mxcs->ctrl_reg = reg_ctrl; 293 mxcs->cfg_reg = reg_config; 294 295 /* clear interrupt reg */ 296 reg_write(®s->intr, 0); 297 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 298 299 return 0; 300 } 301 #endif 302 303 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, 304 const u8 *dout, u8 *din, unsigned long flags) 305 { 306 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 307 int nbytes = (bitlen + 7) / 8; 308 u32 data, cnt, i; 309 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 310 311 debug("%s: bitlen %d dout 0x%x din 0x%x\n", 312 __func__, bitlen, (u32)dout, (u32)din); 313 314 mxcs->ctrl_reg = (mxcs->ctrl_reg & 315 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | 316 MXC_CSPICTRL_BITCOUNT(bitlen - 1); 317 318 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); 319 #ifdef CONFIG_MX51 320 reg_write(®s->cfg, mxcs->cfg_reg); 321 #endif 322 323 /* Clear interrupt register */ 324 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 325 326 /* 327 * The SPI controller works only with words, 328 * check if less than a word is sent. 329 * Access to the FIFO is only 32 bit 330 */ 331 if (bitlen % 32) { 332 data = 0; 333 cnt = (bitlen % 32) / 8; 334 if (dout) { 335 for (i = 0; i < cnt; i++) { 336 data = (data << 8) | (*dout++ & 0xFF); 337 } 338 } 339 debug("Sending SPI 0x%x\n", data); 340 341 reg_write(®s->txdata, data); 342 nbytes -= cnt; 343 } 344 345 data = 0; 346 347 while (nbytes > 0) { 348 data = 0; 349 if (dout) { 350 /* Buffer is not 32-bit aligned */ 351 if ((unsigned long)dout & 0x03) { 352 data = 0; 353 for (i = 0; i < 4; i++) 354 data = (data << 8) | (*dout++ & 0xFF); 355 } else { 356 data = *(u32 *)dout; 357 data = cpu_to_be32(data); 358 } 359 dout += 4; 360 } 361 debug("Sending SPI 0x%x\n", data); 362 reg_write(®s->txdata, data); 363 nbytes -= 4; 364 } 365 366 /* FIFO is written, now starts the transfer setting the XCH bit */ 367 reg_write(®s->ctrl, mxcs->ctrl_reg | 368 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); 369 370 /* Wait until the TC (Transfer completed) bit is set */ 371 while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) 372 ; 373 374 /* Transfer completed, clear any pending request */ 375 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); 376 377 nbytes = (bitlen + 7) / 8; 378 379 cnt = nbytes % 32; 380 381 if (bitlen % 32) { 382 data = reg_read(®s->rxdata); 383 cnt = (bitlen % 32) / 8; 384 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); 385 debug("SPI Rx unaligned: 0x%x\n", data); 386 if (din) { 387 memcpy(din, &data, cnt); 388 din += cnt; 389 } 390 nbytes -= cnt; 391 } 392 393 while (nbytes > 0) { 394 u32 tmp; 395 tmp = reg_read(®s->rxdata); 396 data = cpu_to_be32(tmp); 397 debug("SPI Rx: 0x%x 0x%x\n", tmp, data); 398 cnt = min(nbytes, sizeof(data)); 399 if (din) { 400 memcpy(din, &data, cnt); 401 din += cnt; 402 } 403 nbytes -= cnt; 404 } 405 406 return 0; 407 408 } 409 410 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 411 void *din, unsigned long flags) 412 { 413 int n_bytes = (bitlen + 7) / 8; 414 int n_bits; 415 int ret; 416 u32 blk_size; 417 u8 *p_outbuf = (u8 *)dout; 418 u8 *p_inbuf = (u8 *)din; 419 420 if (!slave) 421 return -1; 422 423 if (flags & SPI_XFER_BEGIN) 424 spi_cs_activate(slave); 425 426 while (n_bytes > 0) { 427 if (n_bytes < MAX_SPI_BYTES) 428 blk_size = n_bytes; 429 else 430 blk_size = MAX_SPI_BYTES; 431 432 n_bits = blk_size * 8; 433 434 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); 435 436 if (ret) 437 return ret; 438 if (dout) 439 p_outbuf += blk_size; 440 if (din) 441 p_inbuf += blk_size; 442 n_bytes -= blk_size; 443 } 444 445 if (flags & SPI_XFER_END) { 446 spi_cs_deactivate(slave); 447 } 448 449 return 0; 450 } 451 452 void spi_init(void) 453 { 454 } 455 456 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) 457 { 458 int ret; 459 460 /* 461 * Some SPI devices require active chip-select over multiple 462 * transactions, we achieve this using a GPIO. Still, the SPI 463 * controller has to be configured to use one of its own chipselects. 464 * To use this feature you have to call spi_setup_slave() with 465 * cs = internal_cs | (gpio << 8), and you have to use some unused 466 * on this SPI controller cs between 0 and 3. 467 */ 468 if (cs > 3) { 469 mxcs->gpio = cs >> 8; 470 cs &= 3; 471 ret = gpio_direction_output(mxcs->gpio, 0); 472 if (ret) { 473 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); 474 return -EINVAL; 475 } 476 } else { 477 mxcs->gpio = -1; 478 } 479 480 return cs; 481 } 482 483 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 484 unsigned int max_hz, unsigned int mode) 485 { 486 struct mxc_spi_slave *mxcs; 487 int ret; 488 489 if (bus >= ARRAY_SIZE(spi_bases)) 490 return NULL; 491 492 mxcs = malloc(sizeof(struct mxc_spi_slave)); 493 if (!mxcs) { 494 puts("mxc_spi: SPI Slave not allocated !\n"); 495 return NULL; 496 } 497 498 ret = decode_cs(mxcs, cs); 499 if (ret < 0) { 500 free(mxcs); 501 return NULL; 502 } 503 504 cs = ret; 505 506 mxcs->slave.bus = bus; 507 mxcs->slave.cs = cs; 508 mxcs->base = spi_bases[bus]; 509 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; 510 511 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); 512 if (ret) { 513 printf("mxc_spi: cannot setup SPI controller\n"); 514 free(mxcs); 515 return NULL; 516 } 517 return &mxcs->slave; 518 } 519 520 void spi_free_slave(struct spi_slave *slave) 521 { 522 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 523 524 free(mxcs); 525 } 526 527 int spi_claim_bus(struct spi_slave *slave) 528 { 529 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); 530 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; 531 532 reg_write(®s->rxdata, 1); 533 udelay(1); 534 reg_write(®s->ctrl, mxcs->ctrl_reg); 535 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); 536 reg_write(®s->intr, 0); 537 538 return 0; 539 } 540 541 void spi_release_bus(struct spi_slave *slave) 542 { 543 /* TODO: Shut the controller down */ 544 } 545