1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Stefan Roese <sr@denx.de> 4 * 5 * Derived from the Linux driver version drivers/spi/spi-mt7621.c 6 * Copyright (C) 2011 Sergiy <piratfm@gmail.com> 7 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 8 * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name> 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <wait_bit.h> 15 #include <linux/io.h> 16 17 #define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */ 18 /* Enough for SPI NAND page read / write with page size 2048 bytes */ 19 #define SPI_MSG_SIZE_OVERALL (2048 + 16) 20 21 #define MT7621_SPI_TRANS 0x00 22 #define MT7621_SPI_TRANS_START BIT(8) 23 #define MT7621_SPI_TRANS_BUSY BIT(16) 24 25 #define MT7621_SPI_OPCODE 0x04 26 #define MT7621_SPI_DATA0 0x08 27 #define MT7621_SPI_DATA4 0x18 28 #define MT7621_SPI_MASTER 0x28 29 #define MT7621_SPI_MOREBUF 0x2c 30 #define MT7621_SPI_POLAR 0x38 31 32 #define MT7621_LSB_FIRST BIT(3) 33 #define MT7621_CPOL BIT(4) 34 #define MT7621_CPHA BIT(5) 35 36 #define MASTER_MORE_BUFMODE BIT(2) 37 #define MASTER_RS_CLK_SEL GENMASK(27, 16) 38 #define MASTER_RS_CLK_SEL_SHIFT 16 39 #define MASTER_RS_SLAVE_SEL GENMASK(31, 29) 40 41 struct mt7621_spi { 42 void __iomem *base; 43 unsigned int sys_freq; 44 u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1]; 45 int tx_len; 46 }; 47 48 static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) 49 { 50 setbits_le32(rs->base + MT7621_SPI_MASTER, 51 MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); 52 } 53 54 static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) 55 { 56 u32 val = 0; 57 58 debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); 59 if (enable) 60 val = BIT(cs); 61 iowrite32(val, rs->base + MT7621_SPI_POLAR); 62 } 63 64 static int mt7621_spi_set_mode(struct udevice *bus, uint mode) 65 { 66 struct mt7621_spi *rs = dev_get_priv(bus); 67 u32 reg; 68 69 debug("%s: mode=0x%08x\n", __func__, mode); 70 reg = ioread32(rs->base + MT7621_SPI_MASTER); 71 72 reg &= ~MT7621_LSB_FIRST; 73 if (mode & SPI_LSB_FIRST) 74 reg |= MT7621_LSB_FIRST; 75 76 reg &= ~(MT7621_CPHA | MT7621_CPOL); 77 switch (mode & (SPI_CPOL | SPI_CPHA)) { 78 case SPI_MODE_0: 79 break; 80 case SPI_MODE_1: 81 reg |= MT7621_CPHA; 82 break; 83 case SPI_MODE_2: 84 reg |= MT7621_CPOL; 85 break; 86 case SPI_MODE_3: 87 reg |= MT7621_CPOL | MT7621_CPHA; 88 break; 89 } 90 iowrite32(reg, rs->base + MT7621_SPI_MASTER); 91 92 return 0; 93 } 94 95 static int mt7621_spi_set_speed(struct udevice *bus, uint speed) 96 { 97 struct mt7621_spi *rs = dev_get_priv(bus); 98 u32 rate; 99 u32 reg; 100 101 debug("%s: speed=%d\n", __func__, speed); 102 rate = DIV_ROUND_UP(rs->sys_freq, speed); 103 debug("rate:%u\n", rate); 104 105 if (rate > 4097) 106 return -EINVAL; 107 108 if (rate < 2) 109 rate = 2; 110 111 reg = ioread32(rs->base + MT7621_SPI_MASTER); 112 reg &= ~MASTER_RS_CLK_SEL; 113 reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; 114 iowrite32(reg, rs->base + MT7621_SPI_MASTER); 115 116 return 0; 117 } 118 119 static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) 120 { 121 int ret; 122 123 ret = wait_for_bit_le32(rs->base + MT7621_SPI_TRANS, 124 MT7621_SPI_TRANS_BUSY, 0, 10, 0); 125 if (ret) 126 pr_err("Timeout in %s!\n", __func__); 127 128 return ret; 129 } 130 131 static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, 132 const void *dout, void *din, unsigned long flags) 133 { 134 struct udevice *bus = dev->parent; 135 struct mt7621_spi *rs = dev_get_priv(bus); 136 const u8 *tx_buf = dout; 137 u8 *ptr = (u8 *)dout; 138 u8 *rx_buf = din; 139 int total_size = bitlen >> 3; 140 int chunk_size; 141 int rx_len = 0; 142 u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 }; 143 u32 val; 144 int i; 145 146 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, 147 total_size, flags); 148 149 /* 150 * This driver only supports half-duplex, so complain and bail out 151 * upon full-duplex messages 152 */ 153 if (dout && din) { 154 printf("Only half-duplex SPI transfer supported\n"); 155 return -EIO; 156 } 157 158 if (dout) { 159 debug("TX-DATA: "); 160 for (i = 0; i < total_size; i++) 161 debug("%02x ", *ptr++); 162 debug("\n"); 163 } 164 165 mt7621_spi_wait_till_ready(rs); 166 167 /* 168 * Set CS active upon start of SPI message. This message can 169 * be split upon multiple calls to this xfer function 170 */ 171 if (flags & SPI_XFER_BEGIN) 172 mt7621_spi_set_cs(rs, spi_chip_select(dev), 1); 173 174 while (total_size > 0) { 175 /* Don't exceed the max xfer size */ 176 chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX); 177 178 /* 179 * We might have some TX data buffered from the last xfer 180 * message. Make sure, that this does not exceed the max 181 * xfer size 182 */ 183 if (rs->tx_len > 4) 184 chunk_size -= rs->tx_len; 185 if (din) 186 rx_len = chunk_size; 187 188 if (tx_buf) { 189 /* Check if this message does not exceed the buffer */ 190 if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) { 191 printf("TX message size too big (%d)\n", 192 chunk_size + rs->tx_len); 193 return -EMSGSIZE; 194 } 195 196 /* 197 * Write all TX data into internal buffer to collect 198 * all TX messages into one buffer (might be split into 199 * multiple calls to this function) 200 */ 201 for (i = 0; i < chunk_size; i++, rs->tx_len++) { 202 rs->data[rs->tx_len / 4] |= 203 tx_buf[i] << (8 * (rs->tx_len & 3)); 204 } 205 } 206 207 if (flags & SPI_XFER_END) { 208 /* Write TX data into controller */ 209 if (rs->tx_len) { 210 rs->data[0] = swab32(rs->data[0]); 211 if (rs->tx_len < 4) 212 rs->data[0] >>= (4 - rs->tx_len) * 8; 213 214 for (i = 0; i < rs->tx_len; i += 4) { 215 iowrite32(rs->data[i / 4], rs->base + 216 MT7621_SPI_OPCODE + i); 217 } 218 } 219 220 /* Write length into controller */ 221 val = (min_t(int, rs->tx_len, 4) * 8) << 24; 222 if (rs->tx_len > 4) 223 val |= (rs->tx_len - 4) * 8; 224 val |= (rx_len * 8) << 12; 225 iowrite32(val, rs->base + MT7621_SPI_MOREBUF); 226 227 /* Start the xfer */ 228 setbits_le32(rs->base + MT7621_SPI_TRANS, 229 MT7621_SPI_TRANS_START); 230 231 /* Wait until xfer is finished on bus */ 232 mt7621_spi_wait_till_ready(rs); 233 234 /* Reset TX length and TX buffer for next xfer */ 235 rs->tx_len = 0; 236 memset(rs->data, 0, sizeof(rs->data)); 237 } 238 239 for (i = 0; i < rx_len; i += 4) 240 data[i / 4] = ioread32(rs->base + MT7621_SPI_DATA0 + i); 241 242 if (rx_len) { 243 debug("RX-DATA: "); 244 for (i = 0; i < rx_len; i++) { 245 rx_buf[i] = data[i / 4] >> (8 * (i & 3)); 246 debug("%02x ", rx_buf[i]); 247 } 248 debug("\n"); 249 } 250 251 if (tx_buf) 252 tx_buf += chunk_size; 253 if (rx_buf) 254 rx_buf += chunk_size; 255 total_size -= chunk_size; 256 } 257 258 /* Wait until xfer is finished on bus and de-assert CS */ 259 mt7621_spi_wait_till_ready(rs); 260 if (flags & SPI_XFER_END) 261 mt7621_spi_set_cs(rs, spi_chip_select(dev), 0); 262 263 return 0; 264 } 265 266 static int mt7621_spi_probe(struct udevice *dev) 267 { 268 struct mt7621_spi *rs = dev_get_priv(dev); 269 270 rs->base = dev_remap_addr(dev); 271 if (!rs->base) 272 return -EINVAL; 273 274 /* 275 * Read input clock via DT for now. At some point this should be 276 * replaced by implementing a clock driver for this SoC and getting 277 * the SPI frequency via this clock driver. 278 */ 279 rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0); 280 if (!rs->sys_freq) { 281 printf("Please provide clock-frequency!\n"); 282 return -EINVAL; 283 } 284 285 mt7621_spi_reset(rs, 0); 286 287 return 0; 288 } 289 290 static const struct dm_spi_ops mt7621_spi_ops = { 291 .set_mode = mt7621_spi_set_mode, 292 .set_speed = mt7621_spi_set_speed, 293 .xfer = mt7621_spi_xfer, 294 /* 295 * cs_info is not needed, since we require all chip selects to be 296 * in the device tree explicitly 297 */ 298 }; 299 300 static const struct udevice_id mt7621_spi_ids[] = { 301 { .compatible = "ralink,mt7621-spi" }, 302 { } 303 }; 304 305 U_BOOT_DRIVER(mt7621_spi) = { 306 .name = "mt7621_spi", 307 .id = UCLASS_SPI, 308 .of_match = mt7621_spi_ids, 309 .ops = &mt7621_spi_ops, 310 .priv_auto_alloc_size = sizeof(struct mt7621_spi), 311 .probe = mt7621_spi_probe, 312 }; 313