xref: /openbmc/u-boot/drivers/spi/kirkwood_spi.c (revision cbd2fba1) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2009
4  * Marvell Semiconductor <www.marvell.com>
5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6  *
7  * Derived from drivers/spi/mpc8xxx_spi.c
8  */
9 
10 #include <common.h>
11 #include <dm.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <asm/io.h>
15 #include <asm/arch/soc.h>
16 #ifdef CONFIG_KIRKWOOD
17 #include <asm/arch/mpp.h>
18 #endif
19 #include <asm/arch-mvebu/spi.h>
20 
21 static void _spi_cs_activate(struct kwspi_registers *reg)
22 {
23 	setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
24 }
25 
26 static void _spi_cs_deactivate(struct kwspi_registers *reg)
27 {
28 	clrbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
29 }
30 
31 static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
32 		     const void *dout, void *din, unsigned long flags)
33 {
34 	unsigned int tmpdout, tmpdin;
35 	int tm, isread = 0;
36 
37 	debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen);
38 
39 	if (flags & SPI_XFER_BEGIN)
40 		_spi_cs_activate(reg);
41 
42 	/*
43 	 * handle data in 8-bit chunks
44 	 * TBD: 2byte xfer mode to be enabled
45 	 */
46 	clrsetbits_le32(&reg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
47 
48 	while (bitlen > 4) {
49 		debug("loopstart bitlen %d\n", bitlen);
50 		tmpdout = 0;
51 
52 		/* Shift data so it's msb-justified */
53 		if (dout)
54 			tmpdout = *(u32 *)dout & 0xff;
55 
56 		clrbits_le32(&reg->irq_cause, KWSPI_SMEMRDIRQ);
57 		writel(tmpdout, &reg->dout);	/* Write the data out */
58 		debug("*** spi_xfer: ... %08x written, bitlen %d\n",
59 		      tmpdout, bitlen);
60 
61 		/*
62 		 * Wait for SPI transmit to get out
63 		 * or time out (1 second = 1000 ms)
64 		 * The NE event must be read and cleared first
65 		 */
66 		for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
67 			if (readl(&reg->irq_cause) & KWSPI_SMEMRDIRQ) {
68 				isread = 1;
69 				tmpdin = readl(&reg->din);
70 				debug("spi_xfer: din %p..%08x read\n",
71 				      din, tmpdin);
72 
73 				if (din) {
74 					*((u8 *)din) = (u8)tmpdin;
75 					din += 1;
76 				}
77 				if (dout)
78 					dout += 1;
79 				bitlen -= 8;
80 			}
81 			if (isread)
82 				break;
83 		}
84 		if (tm >= KWSPI_TIMEOUT)
85 			printf("*** spi_xfer: Time out during SPI transfer\n");
86 
87 		debug("loopend bitlen %d\n", bitlen);
88 	}
89 
90 	if (flags & SPI_XFER_END)
91 		_spi_cs_deactivate(reg);
92 
93 	return 0;
94 }
95 
96 #ifndef CONFIG_DM_SPI
97 
98 static struct kwspi_registers *spireg =
99 	(struct kwspi_registers *)MVEBU_SPI_BASE;
100 
101 #ifdef CONFIG_KIRKWOOD
102 static u32 cs_spi_mpp_back[2];
103 #endif
104 
105 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
106 				unsigned int max_hz, unsigned int mode)
107 {
108 	struct spi_slave *slave;
109 	u32 data;
110 #ifdef CONFIG_KIRKWOOD
111 	static const u32 kwspi_mpp_config[2][2] = {
112 		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
113 		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
114 	};
115 #endif
116 
117 	if (!spi_cs_is_valid(bus, cs))
118 		return NULL;
119 
120 	slave = spi_alloc_slave_base(bus, cs);
121 	if (!slave)
122 		return NULL;
123 
124 	writel(KWSPI_SMEMRDY, &spireg->ctrl);
125 
126 	/* calculate spi clock prescaller using max_hz */
127 	data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
128 	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
129 	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
130 
131 	/* program spi clock prescaller using max_hz */
132 	writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
133 	debug("data = 0x%08x\n", data);
134 
135 	writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
136 	writel(KWSPI_IRQMASK, &spireg->irq_mask);
137 
138 #ifdef CONFIG_KIRKWOOD
139 	/* program mpp registers to select  SPI_CSn */
140 	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
141 #endif
142 
143 	return slave;
144 }
145 
146 void spi_free_slave(struct spi_slave *slave)
147 {
148 #ifdef CONFIG_KIRKWOOD
149 	kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
150 #endif
151 	free(slave);
152 }
153 
154 #if defined(CONFIG_SYS_KW_SPI_MPP)
155 u32 spi_mpp_backup[4];
156 #endif
157 
158 __attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
159 {
160 	return 0;
161 }
162 
163 int spi_claim_bus(struct spi_slave *slave)
164 {
165 #if defined(CONFIG_SYS_KW_SPI_MPP)
166 	u32 config;
167 	u32 spi_mpp_config[4];
168 
169 	config = CONFIG_SYS_KW_SPI_MPP;
170 
171 	if (config & MOSI_MPP6)
172 		spi_mpp_config[0] = MPP6_SPI_MOSI;
173 	else
174 		spi_mpp_config[0] = MPP1_SPI_MOSI;
175 
176 	if (config & SCK_MPP10)
177 		spi_mpp_config[1] = MPP10_SPI_SCK;
178 	else
179 		spi_mpp_config[1] = MPP2_SPI_SCK;
180 
181 	if (config & MISO_MPP11)
182 		spi_mpp_config[2] = MPP11_SPI_MISO;
183 	else
184 		spi_mpp_config[2] = MPP3_SPI_MISO;
185 
186 	spi_mpp_config[3] = 0;
187 	spi_mpp_backup[3] = 0;
188 
189 	/* set new spi mpp and save current mpp config */
190 	kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
191 #endif
192 
193 	return board_spi_claim_bus(slave);
194 }
195 
196 __attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
197 {
198 }
199 
200 void spi_release_bus(struct spi_slave *slave)
201 {
202 #if defined(CONFIG_SYS_KW_SPI_MPP)
203 	kirkwood_mpp_conf(spi_mpp_backup, NULL);
204 #endif
205 
206 	board_spi_release_bus(slave);
207 }
208 
209 #ifndef CONFIG_SPI_CS_IS_VALID
210 /*
211  * you can define this function board specific
212  * define above CONFIG in board specific config file and
213  * provide the function in board specific src file
214  */
215 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
216 {
217 	return bus == 0 && (cs == 0 || cs == 1);
218 }
219 #endif
220 
221 void spi_init(void)
222 {
223 }
224 
225 void spi_cs_activate(struct spi_slave *slave)
226 {
227 	_spi_cs_activate(spireg);
228 }
229 
230 void spi_cs_deactivate(struct spi_slave *slave)
231 {
232 	_spi_cs_deactivate(spireg);
233 }
234 
235 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
236 	     const void *dout, void *din, unsigned long flags)
237 {
238 	return _spi_xfer(spireg, bitlen, dout, din, flags);
239 }
240 
241 #else
242 
243 /* Here now the DM part */
244 
245 struct mvebu_spi_dev {
246 	bool			is_errata_50mhz_ac;
247 };
248 
249 struct mvebu_spi_platdata {
250 	struct kwspi_registers *spireg;
251 	bool is_errata_50mhz_ac;
252 };
253 
254 struct mvebu_spi_priv {
255 	struct kwspi_registers *spireg;
256 };
257 
258 static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
259 {
260 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
261 	struct kwspi_registers *reg = plat->spireg;
262 	u32 data;
263 
264 	/* calculate spi clock prescaller using max_hz */
265 	data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
266 	data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
267 	data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
268 
269 	/* program spi clock prescaler using max_hz */
270 	writel(KWSPI_ADRLEN_3BYTE | data, &reg->cfg);
271 	debug("data = 0x%08x\n", data);
272 
273 	return 0;
274 }
275 
276 static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode)
277 {
278 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
279 	struct kwspi_registers *reg = plat->spireg;
280 	u32 data;
281 
282 	/*
283 	 * Erratum description: (Erratum NO. FE-9144572) The device
284 	 * SPI interface supports frequencies of up to 50 MHz.
285 	 * However, due to this erratum, when the device core clock is
286 	 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
287 	 * clock and CPOL=CPHA=1 there might occur data corruption on
288 	 * reads from the SPI device.
289 	 * Erratum Workaround:
290 	 * Work in one of the following configurations:
291 	 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
292 	 * Register".
293 	 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
294 	 * Register" before setting the interface.
295 	 */
296 	data = readl(&reg->timing1);
297 	data &= ~KW_SPI_TMISO_SAMPLE_MASK;
298 
299 	if (CONFIG_SYS_TCLK == 250000000 &&
300 	    mode & SPI_CPOL &&
301 	    mode & SPI_CPHA)
302 		data |= KW_SPI_TMISO_SAMPLE_2;
303 	else
304 		data |= KW_SPI_TMISO_SAMPLE_1;
305 
306 	writel(data, &reg->timing1);
307 }
308 
309 static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
310 {
311 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
312 	struct kwspi_registers *reg = plat->spireg;
313 	u32 data = readl(&reg->cfg);
314 
315 	data &= ~(KWSPI_CPHA | KWSPI_CPOL | KWSPI_RXLSBF | KWSPI_TXLSBF);
316 
317 	if (mode & SPI_CPHA)
318 		data |= KWSPI_CPHA;
319 	if (mode & SPI_CPOL)
320 		data |= KWSPI_CPOL;
321 	if (mode & SPI_LSB_FIRST)
322 		data |= (KWSPI_RXLSBF | KWSPI_TXLSBF);
323 
324 	writel(data, &reg->cfg);
325 
326 	if (plat->is_errata_50mhz_ac)
327 		mvebu_spi_50mhz_ac_timing_erratum(bus, mode);
328 
329 	return 0;
330 }
331 
332 static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
333 			  const void *dout, void *din, unsigned long flags)
334 {
335 	struct udevice *bus = dev->parent;
336 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
337 
338 	return _spi_xfer(plat->spireg, bitlen, dout, din, flags);
339 }
340 
341 static int mvebu_spi_claim_bus(struct udevice *dev)
342 {
343 	struct udevice *bus = dev->parent;
344 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
345 
346 	/* Configure the chip-select in the CTRL register */
347 	clrsetbits_le32(&plat->spireg->ctrl,
348 			KWSPI_CS_MASK << KWSPI_CS_SHIFT,
349 			spi_chip_select(dev) << KWSPI_CS_SHIFT);
350 
351 	return 0;
352 }
353 
354 static int mvebu_spi_probe(struct udevice *bus)
355 {
356 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
357 	struct kwspi_registers *reg = plat->spireg;
358 
359 	writel(KWSPI_SMEMRDY, &reg->ctrl);
360 	writel(KWSPI_SMEMRDIRQ, &reg->irq_cause);
361 	writel(KWSPI_IRQMASK, &reg->irq_mask);
362 
363 	return 0;
364 }
365 
366 static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
367 {
368 	struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
369 	const struct mvebu_spi_dev *drvdata =
370 		(struct mvebu_spi_dev *)dev_get_driver_data(bus);
371 
372 	plat->spireg = (struct kwspi_registers *)devfdt_get_addr(bus);
373 	plat->is_errata_50mhz_ac = drvdata->is_errata_50mhz_ac;
374 
375 	return 0;
376 }
377 
378 static const struct dm_spi_ops mvebu_spi_ops = {
379 	.claim_bus	= mvebu_spi_claim_bus,
380 	.xfer		= mvebu_spi_xfer,
381 	.set_speed	= mvebu_spi_set_speed,
382 	.set_mode	= mvebu_spi_set_mode,
383 	/*
384 	 * cs_info is not needed, since we require all chip selects to be
385 	 * in the device tree explicitly
386 	 */
387 };
388 
389 static const struct mvebu_spi_dev armada_spi_dev_data = {
390 	.is_errata_50mhz_ac = false,
391 };
392 
393 static const struct mvebu_spi_dev armada_xp_spi_dev_data = {
394 	.is_errata_50mhz_ac = false,
395 };
396 
397 static const struct mvebu_spi_dev armada_375_spi_dev_data = {
398 	.is_errata_50mhz_ac = false,
399 };
400 
401 static const struct mvebu_spi_dev armada_380_spi_dev_data = {
402 	.is_errata_50mhz_ac = true,
403 };
404 
405 static const struct udevice_id mvebu_spi_ids[] = {
406 	{
407 		.compatible = "marvell,orion-spi",
408 		.data = (ulong)&armada_spi_dev_data,
409 	},
410 	{
411 		.compatible = "marvell,armada-375-spi",
412 		.data = (ulong)&armada_375_spi_dev_data
413 	},
414 	{
415 		.compatible = "marvell,armada-380-spi",
416 		.data = (ulong)&armada_380_spi_dev_data
417 	},
418 	{
419 		.compatible = "marvell,armada-xp-spi",
420 		.data = (ulong)&armada_xp_spi_dev_data
421 	},
422 	{ }
423 };
424 
425 U_BOOT_DRIVER(mvebu_spi) = {
426 	.name = "mvebu_spi",
427 	.id = UCLASS_SPI,
428 	.of_match = mvebu_spi_ids,
429 	.ops = &mvebu_spi_ops,
430 	.ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
431 	.platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
432 	.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
433 	.probe = mvebu_spi_probe,
434 };
435 #endif
436