1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 struct ich7_spi_regs { 10 uint16_t spis; 11 uint16_t spic; 12 uint32_t spia; 13 uint64_t spid[8]; 14 uint64_t _pad; 15 uint32_t bbar; 16 uint16_t preop; 17 uint16_t optype; 18 uint8_t opmenu[8]; 19 } __packed; 20 21 struct ich9_spi_regs { 22 uint32_t bfpr; /* 0x00 */ 23 uint16_t hsfs; 24 uint16_t hsfc; 25 uint32_t faddr; 26 uint32_t _reserved0; 27 uint32_t fdata[16]; /* 0x10 */ 28 uint32_t frap; /* 0x50 */ 29 uint32_t freg[5]; 30 uint32_t _reserved1[3]; 31 uint32_t pr[5]; /* 0x74 */ 32 uint32_t _reserved2[2]; 33 uint8_t ssfs; /* 0x90 */ 34 uint8_t ssfc[3]; 35 uint16_t preop; /* 0x94 */ 36 uint16_t optype; 37 uint8_t opmenu[8]; /* 0x98 */ 38 uint32_t bbar; 39 uint8_t _reserved3[12]; 40 uint32_t fdoc; 41 uint32_t fdod; 42 uint8_t _reserved4[8]; 43 uint32_t afc; 44 uint32_t lvscc; 45 uint32_t uvscc; 46 uint8_t _reserved5[4]; 47 uint32_t fpb; 48 uint8_t _reserved6[28]; 49 uint32_t srdl; 50 uint32_t srdc; 51 uint32_t srd; 52 } __packed; 53 54 enum { 55 SPIS_SCIP = 0x0001, 56 SPIS_GRANT = 0x0002, 57 SPIS_CDS = 0x0004, 58 SPIS_FCERR = 0x0008, 59 SSFS_AEL = 0x0010, 60 SPIS_LOCK = 0x8000, 61 SPIS_RESERVED_MASK = 0x7ff0, 62 SSFS_RESERVED_MASK = 0x7fe2 63 }; 64 65 enum { 66 SPIC_SCGO = 0x000002, 67 SPIC_ACS = 0x000004, 68 SPIC_SPOP = 0x000008, 69 SPIC_DBC = 0x003f00, 70 SPIC_DS = 0x004000, 71 SPIC_SME = 0x008000, 72 SSFC_SCF_MASK = 0x070000, 73 SSFC_RESERVED = 0xf80000, 74 75 /* Mask for speed byte, biuts 23:16 of SSFC */ 76 SSFC_SCF_33MHZ = 0x01, 77 }; 78 79 enum { 80 HSFS_FDONE = 0x0001, 81 HSFS_FCERR = 0x0002, 82 HSFS_AEL = 0x0004, 83 HSFS_BERASE_MASK = 0x0018, 84 HSFS_BERASE_SHIFT = 3, 85 HSFS_SCIP = 0x0020, 86 HSFS_FDOPSS = 0x2000, 87 HSFS_FDV = 0x4000, 88 HSFS_FLOCKDN = 0x8000 89 }; 90 91 enum { 92 HSFC_FGO = 0x0001, 93 HSFC_FCYCLE_MASK = 0x0006, 94 HSFC_FCYCLE_SHIFT = 1, 95 HSFC_FDBC_MASK = 0x3f00, 96 HSFC_FDBC_SHIFT = 8, 97 HSFC_FSMIE = 0x8000 98 }; 99 100 enum { 101 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, 102 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, 103 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, 104 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 105 }; 106 107 enum { 108 ICH_MAX_CMD_LEN = 5, 109 }; 110 111 struct spi_trans { 112 uint8_t cmd[ICH_MAX_CMD_LEN]; 113 int cmd_len; 114 const uint8_t *out; 115 uint32_t bytesout; 116 uint8_t *in; 117 uint32_t bytesin; 118 uint8_t type; 119 uint8_t opcode; 120 uint32_t offset; 121 }; 122 123 struct ich_spi_slave { 124 struct spi_slave slave; 125 struct spi_trans trans; /* current transaction in progress */ 126 int speed; /* SPI speed in Hz */ 127 }; 128