1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but without any warranty; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 * This file is derived from the flashrom project. 23 */ 24 25 struct ich7_spi_regs { 26 uint16_t spis; 27 uint16_t spic; 28 uint32_t spia; 29 uint64_t spid[8]; 30 uint64_t _pad; 31 uint32_t bbar; 32 uint16_t preop; 33 uint16_t optype; 34 uint8_t opmenu[8]; 35 } __packed; 36 37 struct ich9_spi_regs { 38 uint32_t bfpr; /* 0x00 */ 39 uint16_t hsfs; 40 uint16_t hsfc; 41 uint32_t faddr; 42 uint32_t _reserved0; 43 uint32_t fdata[16]; /* 0x10 */ 44 uint32_t frap; /* 0x50 */ 45 uint32_t freg[5]; 46 uint32_t _reserved1[3]; 47 uint32_t pr[5]; /* 0x74 */ 48 uint32_t _reserved2[2]; 49 uint8_t ssfs; /* 0x90 */ 50 uint8_t ssfc[3]; 51 uint16_t preop; /* 0x94 */ 52 uint16_t optype; 53 uint8_t opmenu[8]; /* 0x98 */ 54 uint32_t bbar; 55 uint8_t _reserved3[12]; 56 uint32_t fdoc; 57 uint32_t fdod; 58 uint8_t _reserved4[8]; 59 uint32_t afc; 60 uint32_t lvscc; 61 uint32_t uvscc; 62 uint8_t _reserved5[4]; 63 uint32_t fpb; 64 uint8_t _reserved6[28]; 65 uint32_t srdl; 66 uint32_t srdc; 67 uint32_t srd; 68 } __packed; 69 70 enum { 71 SPIS_SCIP = 0x0001, 72 SPIS_GRANT = 0x0002, 73 SPIS_CDS = 0x0004, 74 SPIS_FCERR = 0x0008, 75 SSFS_AEL = 0x0010, 76 SPIS_LOCK = 0x8000, 77 SPIS_RESERVED_MASK = 0x7ff0, 78 SSFS_RESERVED_MASK = 0x7fe2 79 }; 80 81 enum { 82 SPIC_SCGO = 0x000002, 83 SPIC_ACS = 0x000004, 84 SPIC_SPOP = 0x000008, 85 SPIC_DBC = 0x003f00, 86 SPIC_DS = 0x004000, 87 SPIC_SME = 0x008000, 88 SSFC_SCF_MASK = 0x070000, 89 SSFC_RESERVED = 0xf80000, 90 91 /* Mask for speed byte, biuts 23:16 of SSFC */ 92 SSFC_SCF_33MHZ = 0x01, 93 }; 94 95 enum { 96 HSFS_FDONE = 0x0001, 97 HSFS_FCERR = 0x0002, 98 HSFS_AEL = 0x0004, 99 HSFS_BERASE_MASK = 0x0018, 100 HSFS_BERASE_SHIFT = 3, 101 HSFS_SCIP = 0x0020, 102 HSFS_FDOPSS = 0x2000, 103 HSFS_FDV = 0x4000, 104 HSFS_FLOCKDN = 0x8000 105 }; 106 107 enum { 108 HSFC_FGO = 0x0001, 109 HSFC_FCYCLE_MASK = 0x0006, 110 HSFC_FCYCLE_SHIFT = 1, 111 HSFC_FDBC_MASK = 0x3f00, 112 HSFC_FDBC_SHIFT = 8, 113 HSFC_FSMIE = 0x8000 114 }; 115 116 enum { 117 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, 118 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, 119 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, 120 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 121 }; 122 123 enum { 124 ICH_MAX_CMD_LEN = 5, 125 }; 126 127 struct spi_trans { 128 uint8_t cmd[ICH_MAX_CMD_LEN]; 129 int cmd_len; 130 const uint8_t *out; 131 uint32_t bytesout; 132 uint8_t *in; 133 uint32_t bytesin; 134 uint8_t type; 135 uint8_t opcode; 136 uint32_t offset; 137 }; 138 139 struct ich_spi_slave { 140 struct spi_slave slave; 141 struct spi_trans trans; /* current transaction in progress */ 142 int speed; /* SPI speed in Hz */ 143 }; 144