1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 struct ich7_spi_regs { 10 uint16_t spis; 11 uint16_t spic; 12 uint32_t spia; 13 uint64_t spid[8]; 14 uint64_t _pad; 15 uint32_t bbar; 16 uint16_t preop; 17 uint16_t optype; 18 uint8_t opmenu[8]; 19 } __packed; 20 21 struct ich9_spi_regs { 22 uint32_t bfpr; /* 0x00 */ 23 uint16_t hsfs; 24 uint16_t hsfc; 25 uint32_t faddr; 26 uint32_t _reserved0; 27 uint32_t fdata[16]; /* 0x10 */ 28 uint32_t frap; /* 0x50 */ 29 uint32_t freg[5]; 30 uint32_t _reserved1[3]; 31 uint32_t pr[5]; /* 0x74 */ 32 uint32_t _reserved2[2]; 33 uint8_t ssfs; /* 0x90 */ 34 uint8_t ssfc[3]; 35 uint16_t preop; /* 0x94 */ 36 uint16_t optype; 37 uint8_t opmenu[8]; /* 0x98 */ 38 uint32_t bbar; 39 uint8_t _reserved3[12]; 40 uint32_t fdoc; /* 0xb0 */ 41 uint32_t fdod; 42 uint8_t _reserved4[8]; 43 uint32_t afc; /* 0xc0 */ 44 uint32_t lvscc; 45 uint32_t uvscc; 46 uint8_t _reserved5[4]; 47 uint32_t fpb; /* 0xd0 */ 48 uint8_t _reserved6[28]; 49 uint32_t srdl; /* 0xf0 */ 50 uint32_t srdc; 51 uint32_t scs; 52 uint32_t bcr; 53 } __packed; 54 55 enum { 56 SPIS_SCIP = 0x0001, 57 SPIS_GRANT = 0x0002, 58 SPIS_CDS = 0x0004, 59 SPIS_FCERR = 0x0008, 60 SSFS_AEL = 0x0010, 61 SPIS_LOCK = 0x8000, 62 SPIS_RESERVED_MASK = 0x7ff0, 63 SSFS_RESERVED_MASK = 0x7fe2 64 }; 65 66 enum { 67 SPIC_SCGO = 0x000002, 68 SPIC_ACS = 0x000004, 69 SPIC_SPOP = 0x000008, 70 SPIC_DBC = 0x003f00, 71 SPIC_DS = 0x004000, 72 SPIC_SME = 0x008000, 73 SSFC_SCF_MASK = 0x070000, 74 SSFC_RESERVED = 0xf80000, 75 76 /* Mask for speed byte, biuts 23:16 of SSFC */ 77 SSFC_SCF_33MHZ = 0x01, 78 }; 79 80 enum { 81 HSFS_FDONE = 0x0001, 82 HSFS_FCERR = 0x0002, 83 HSFS_AEL = 0x0004, 84 HSFS_BERASE_MASK = 0x0018, 85 HSFS_BERASE_SHIFT = 3, 86 HSFS_SCIP = 0x0020, 87 HSFS_FDOPSS = 0x2000, 88 HSFS_FDV = 0x4000, 89 HSFS_FLOCKDN = 0x8000 90 }; 91 92 enum { 93 HSFC_FGO = 0x0001, 94 HSFC_FCYCLE_MASK = 0x0006, 95 HSFC_FCYCLE_SHIFT = 1, 96 HSFC_FDBC_MASK = 0x3f00, 97 HSFC_FDBC_SHIFT = 8, 98 HSFC_FSMIE = 0x8000 99 }; 100 101 enum { 102 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, 103 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, 104 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, 105 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 106 }; 107 108 enum { 109 ICH_MAX_CMD_LEN = 5, 110 }; 111 112 struct spi_trans { 113 uint8_t cmd[ICH_MAX_CMD_LEN]; 114 int cmd_len; 115 const uint8_t *out; 116 uint32_t bytesout; 117 uint8_t *in; 118 uint32_t bytesin; 119 uint8_t type; 120 uint8_t opcode; 121 uint32_t offset; 122 }; 123 124 struct ich_spi_slave { 125 struct spi_slave slave; 126 struct spi_trans trans; /* current transaction in progress */ 127 int speed; /* SPI speed in Hz */ 128 }; 129