1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <pci.h> 13 #include <pci_ids.h> 14 #include <asm/io.h> 15 16 #include "ich.h" 17 18 #define SPI_OPCODE_WREN 0x06 19 #define SPI_OPCODE_FAST_READ 0x0b 20 21 struct ich_ctlr { 22 pci_dev_t dev; /* PCI device number */ 23 int ich_version; /* Controller version, 7 or 9 */ 24 int ichspi_lock; 25 int locked; 26 uint8_t *opmenu; 27 int menubytes; 28 void *base; /* Base of register set */ 29 uint16_t *preop; 30 uint16_t *optype; 31 uint32_t *addr; 32 uint8_t *data; 33 unsigned databytes; 34 uint8_t *status; 35 uint16_t *control; 36 uint32_t *bbar; 37 uint32_t *pr; /* only for ich9 */ 38 uint8_t *speed; /* pointer to speed control */ 39 ulong max_speed; /* Maximum bus speed in MHz */ 40 }; 41 42 struct ich_ctlr ctlr; 43 44 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) 45 { 46 return container_of(slave, struct ich_spi_slave, slave); 47 } 48 49 static unsigned int ich_reg(const void *addr) 50 { 51 return (unsigned)(addr - ctlr.base) & 0xffff; 52 } 53 54 static u8 ich_readb(const void *addr) 55 { 56 u8 value = readb(addr); 57 58 debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); 59 60 return value; 61 } 62 63 static u16 ich_readw(const void *addr) 64 { 65 u16 value = readw(addr); 66 67 debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); 68 69 return value; 70 } 71 72 static u32 ich_readl(const void *addr) 73 { 74 u32 value = readl(addr); 75 76 debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); 77 78 return value; 79 } 80 81 static void ich_writeb(u8 value, void *addr) 82 { 83 writeb(value, addr); 84 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); 85 } 86 87 static void ich_writew(u16 value, void *addr) 88 { 89 writew(value, addr); 90 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); 91 } 92 93 static void ich_writel(u32 value, void *addr) 94 { 95 writel(value, addr); 96 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); 97 } 98 99 static void write_reg(const void *value, void *dest, uint32_t size) 100 { 101 memcpy_toio(dest, value, size); 102 } 103 104 static void read_reg(const void *src, void *value, uint32_t size) 105 { 106 memcpy_fromio(value, src, size); 107 } 108 109 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) 110 { 111 const uint32_t bbar_mask = 0x00ffff00; 112 uint32_t ichspi_bbar; 113 114 minaddr &= bbar_mask; 115 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; 116 ichspi_bbar |= minaddr; 117 ich_writel(ichspi_bbar, ctlr->bbar); 118 } 119 120 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 121 { 122 puts("spi_cs_is_valid used but not implemented\n"); 123 return 0; 124 } 125 126 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 127 unsigned int max_hz, unsigned int mode) 128 { 129 struct ich_spi_slave *ich; 130 131 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); 132 if (!ich) { 133 puts("ICH SPI: Out of memory\n"); 134 return NULL; 135 } 136 137 /* 138 * Yes this controller can only write a small number of bytes at 139 * once! The limit is typically 64 bytes. 140 */ 141 ich->slave.max_write_size = ctlr.databytes; 142 ich->speed = max_hz; 143 144 /* 145 * ICH 7 SPI controller only supports array read command 146 * and byte program command for SST flash 147 */ 148 if (ctlr.ich_version == 7) { 149 ich->slave.op_mode_rx = SPI_OPM_RX_AS; 150 ich->slave.op_mode_tx = SPI_OPM_TX_BP; 151 } 152 153 return &ich->slave; 154 } 155 156 struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, 157 int spi_node) 158 { 159 /* We only support a single SPI at present */ 160 return spi_setup_slave(0, 0, 20000000, 0); 161 } 162 163 void spi_free_slave(struct spi_slave *slave) 164 { 165 struct ich_spi_slave *ich = to_ich_spi(slave); 166 167 free(ich); 168 } 169 170 /* 171 * Check if this device ID matches one of supported Intel PCH devices. 172 * 173 * Return the ICH version if there is a match, or zero otherwise. 174 */ 175 static int get_ich_version(uint16_t device_id) 176 { 177 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || 178 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC) 179 return 7; 180 181 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 182 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 183 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 184 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) 185 return 9; 186 187 return 0; 188 } 189 190 /* @return 1 if the SPI flash supports the 33MHz speed */ 191 static int ich9_can_do_33mhz(pci_dev_t dev) 192 { 193 u32 fdod, speed; 194 195 /* Observe SPI Descriptor Component Section 0 */ 196 pci_write_config_dword(dev, 0xb0, 0x1000); 197 198 /* Extract the Write/Erase SPI Frequency from descriptor */ 199 pci_read_config_dword(dev, 0xb4, &fdod); 200 201 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 202 speed = (fdod >> 21) & 7; 203 204 return speed == 1; 205 } 206 207 static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) 208 { 209 int last_bus = pci_last_busno(); 210 int bus; 211 212 if (last_bus == -1) { 213 debug("No PCI busses?\n"); 214 return -1; 215 } 216 217 for (bus = 0; bus <= last_bus; bus++) { 218 uint16_t vendor_id, device_id; 219 uint32_t ids; 220 pci_dev_t dev; 221 222 dev = PCI_BDF(bus, 31, 0); 223 pci_read_config_dword(dev, 0, &ids); 224 vendor_id = ids; 225 device_id = ids >> 16; 226 227 if (vendor_id == PCI_VENDOR_ID_INTEL) { 228 *devp = dev; 229 *ich_versionp = get_ich_version(device_id); 230 return 0; 231 } 232 } 233 234 debug("ICH SPI: No ICH found.\n"); 235 return -1; 236 } 237 238 static int ich_init_controller(struct ich_ctlr *ctlr) 239 { 240 uint8_t *rcrb; /* Root Complex Register Block */ 241 uint32_t rcba; /* Root Complex Base Address */ 242 243 pci_read_config_dword(ctlr->dev, 0xf0, &rcba); 244 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 245 rcrb = (uint8_t *)(rcba & 0xffffc000); 246 if (ctlr->ich_version == 7) { 247 struct ich7_spi_regs *ich7_spi; 248 249 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 250 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; 251 ctlr->opmenu = ich7_spi->opmenu; 252 ctlr->menubytes = sizeof(ich7_spi->opmenu); 253 ctlr->optype = &ich7_spi->optype; 254 ctlr->addr = &ich7_spi->spia; 255 ctlr->data = (uint8_t *)ich7_spi->spid; 256 ctlr->databytes = sizeof(ich7_spi->spid); 257 ctlr->status = (uint8_t *)&ich7_spi->spis; 258 ctlr->control = &ich7_spi->spic; 259 ctlr->bbar = &ich7_spi->bbar; 260 ctlr->preop = &ich7_spi->preop; 261 ctlr->base = ich7_spi; 262 } else if (ctlr->ich_version == 9) { 263 struct ich9_spi_regs *ich9_spi; 264 265 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 266 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 267 ctlr->opmenu = ich9_spi->opmenu; 268 ctlr->menubytes = sizeof(ich9_spi->opmenu); 269 ctlr->optype = &ich9_spi->optype; 270 ctlr->addr = &ich9_spi->faddr; 271 ctlr->data = (uint8_t *)ich9_spi->fdata; 272 ctlr->databytes = sizeof(ich9_spi->fdata); 273 ctlr->status = &ich9_spi->ssfs; 274 ctlr->control = (uint16_t *)ich9_spi->ssfc; 275 ctlr->speed = ich9_spi->ssfc + 2; 276 ctlr->bbar = &ich9_spi->bbar; 277 ctlr->preop = &ich9_spi->preop; 278 ctlr->pr = &ich9_spi->pr[0]; 279 ctlr->base = ich9_spi; 280 } else { 281 debug("ICH SPI: Unrecognized ICH version %d.\n", 282 ctlr->ich_version); 283 return -1; 284 } 285 debug("ICH SPI: Version %d detected\n", ctlr->ich_version); 286 287 /* Work out the maximum speed we can support */ 288 ctlr->max_speed = 20000000; 289 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) 290 ctlr->max_speed = 33000000; 291 292 ich_set_bbar(ctlr, 0); 293 294 return 0; 295 } 296 297 void spi_init(void) 298 { 299 uint8_t bios_cntl; 300 301 if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { 302 printf("ICH SPI: Cannot find device\n"); 303 return; 304 } 305 306 if (ich_init_controller(&ctlr)) { 307 printf("ICH SPI: Cannot setup controller\n"); 308 return; 309 } 310 311 /* 312 * Disable the BIOS write protect so write commands are allowed. On 313 * v9, deassert SMM BIOS Write Protect Disable. 314 */ 315 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); 316 if (ctlr.ich_version == 9) 317 bios_cntl &= ~(1 << 5); 318 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); 319 } 320 321 int spi_claim_bus(struct spi_slave *slave) 322 { 323 /* Handled by ICH automatically. */ 324 return 0; 325 } 326 327 void spi_release_bus(struct spi_slave *slave) 328 { 329 /* Handled by ICH automatically. */ 330 } 331 332 void spi_cs_activate(struct spi_slave *slave) 333 { 334 /* Handled by ICH automatically. */ 335 } 336 337 void spi_cs_deactivate(struct spi_slave *slave) 338 { 339 /* Handled by ICH automatically. */ 340 } 341 342 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 343 { 344 trans->out += bytes; 345 trans->bytesout -= bytes; 346 } 347 348 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 349 { 350 trans->in += bytes; 351 trans->bytesin -= bytes; 352 } 353 354 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 355 { 356 trans->type = 0xFF; 357 358 /* Try to guess spi type from read/write sizes. */ 359 if (trans->bytesin == 0) { 360 if (trans->bytesout + data_bytes > 4) 361 /* 362 * If bytesin = 0 and bytesout > 4, we presume this is 363 * a write data operation, which is accompanied by an 364 * address. 365 */ 366 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 367 else 368 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 369 return; 370 } 371 372 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 373 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 374 return; 375 } 376 377 if (trans->bytesout == 4) /* and bytesin is > 0 */ 378 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 379 380 /* Fast read command is called with 5 bytes instead of 4 */ 381 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 382 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 383 --trans->bytesout; 384 } 385 } 386 387 static int spi_setup_opcode(struct spi_trans *trans) 388 { 389 uint16_t optypes; 390 uint8_t opmenu[ctlr.menubytes]; 391 392 trans->opcode = trans->out[0]; 393 spi_use_out(trans, 1); 394 if (!ctlr.ichspi_lock) { 395 /* The lock is off, so just use index 0. */ 396 ich_writeb(trans->opcode, ctlr.opmenu); 397 optypes = ich_readw(ctlr.optype); 398 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 399 ich_writew(optypes, ctlr.optype); 400 return 0; 401 } else { 402 /* The lock is on. See if what we need is on the menu. */ 403 uint8_t optype; 404 uint16_t opcode_index; 405 406 /* Write Enable is handled as atomic prefix */ 407 if (trans->opcode == SPI_OPCODE_WREN) 408 return 0; 409 410 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); 411 for (opcode_index = 0; opcode_index < ctlr.menubytes; 412 opcode_index++) { 413 if (opmenu[opcode_index] == trans->opcode) 414 break; 415 } 416 417 if (opcode_index == ctlr.menubytes) { 418 printf("ICH SPI: Opcode %x not found\n", 419 trans->opcode); 420 return -1; 421 } 422 423 optypes = ich_readw(ctlr.optype); 424 optype = (optypes >> (opcode_index * 2)) & 0x3; 425 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 426 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 427 trans->bytesout >= 3) { 428 /* We guessed wrong earlier. Fix it up. */ 429 trans->type = optype; 430 } 431 if (optype != trans->type) { 432 printf("ICH SPI: Transaction doesn't fit type %d\n", 433 optype); 434 return -1; 435 } 436 return opcode_index; 437 } 438 } 439 440 static int spi_setup_offset(struct spi_trans *trans) 441 { 442 /* Separate the SPI address and data. */ 443 switch (trans->type) { 444 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 445 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 446 return 0; 447 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 448 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 449 trans->offset = ((uint32_t)trans->out[0] << 16) | 450 ((uint32_t)trans->out[1] << 8) | 451 ((uint32_t)trans->out[2] << 0); 452 spi_use_out(trans, 3); 453 return 1; 454 default: 455 printf("Unrecognized SPI transaction type %#x\n", trans->type); 456 return -1; 457 } 458 } 459 460 /* 461 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 462 * below is true) or 0. In case the wait was for the bit(s) to set - write 463 * those bits back, which would cause resetting them. 464 * 465 * Return the last read status value on success or -1 on failure. 466 */ 467 static int ich_status_poll(u16 bitmask, int wait_til_set) 468 { 469 int timeout = 600000; /* This will result in 6s */ 470 u16 status = 0; 471 472 while (timeout--) { 473 status = ich_readw(ctlr.status); 474 if (wait_til_set ^ ((status & bitmask) == 0)) { 475 if (wait_til_set) 476 ich_writew((status & bitmask), ctlr.status); 477 return status; 478 } 479 udelay(10); 480 } 481 482 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 483 status, bitmask); 484 return -1; 485 } 486 487 /* 488 int spi_xfer(struct spi_slave *slave, const void *dout, 489 unsigned int bitsout, void *din, unsigned int bitsin) 490 */ 491 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 492 void *din, unsigned long flags) 493 { 494 struct ich_spi_slave *ich = to_ich_spi(slave); 495 uint16_t control; 496 int16_t opcode_index; 497 int with_address; 498 int status; 499 int bytes = bitlen / 8; 500 struct spi_trans *trans = &ich->trans; 501 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 502 int using_cmd = 0; 503 504 /* Ee don't support writing partial bytes. */ 505 if (bitlen % 8) { 506 debug("ICH SPI: Accessing partial bytes not supported\n"); 507 return -1; 508 } 509 510 /* An empty end transaction can be ignored */ 511 if (type == SPI_XFER_END && !dout && !din) 512 return 0; 513 514 if (type & SPI_XFER_BEGIN) 515 memset(trans, '\0', sizeof(*trans)); 516 517 /* Dp we need to come back later to finish it? */ 518 if (dout && type == SPI_XFER_BEGIN) { 519 if (bytes > ICH_MAX_CMD_LEN) { 520 debug("ICH SPI: Command length limit exceeded\n"); 521 return -1; 522 } 523 memcpy(trans->cmd, dout, bytes); 524 trans->cmd_len = bytes; 525 debug("ICH SPI: Saved %d bytes\n", bytes); 526 return 0; 527 } 528 529 /* 530 * We process a 'middle' spi_xfer() call, which has no 531 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 532 * an end. We therefore repeat the command. This is because ICH 533 * seems to have no support for this, or because interest (in digging 534 * out the details and creating a special case in the code) is low. 535 */ 536 if (trans->cmd_len) { 537 trans->out = trans->cmd; 538 trans->bytesout = trans->cmd_len; 539 using_cmd = 1; 540 debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 541 } else { 542 trans->out = dout; 543 trans->bytesout = dout ? bytes : 0; 544 } 545 546 trans->in = din; 547 trans->bytesin = din ? bytes : 0; 548 549 /* There has to always at least be an opcode. */ 550 if (!trans->bytesout) { 551 debug("ICH SPI: No opcode for transfer\n"); 552 return -1; 553 } 554 555 if (ich_status_poll(SPIS_SCIP, 0) == -1) 556 return -1; 557 558 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); 559 560 spi_setup_type(trans, using_cmd ? bytes : 0); 561 opcode_index = spi_setup_opcode(trans); 562 if (opcode_index < 0) 563 return -1; 564 with_address = spi_setup_offset(trans); 565 if (with_address < 0) 566 return -1; 567 568 if (trans->opcode == SPI_OPCODE_WREN) { 569 /* 570 * Treat Write Enable as Atomic Pre-Op if possible 571 * in order to prevent the Management Engine from 572 * issuing a transaction between WREN and DATA. 573 */ 574 if (!ctlr.ichspi_lock) 575 ich_writew(trans->opcode, ctlr.preop); 576 return 0; 577 } 578 579 if (ctlr.speed && ctlr.max_speed >= 33000000) { 580 int byte; 581 582 byte = ich_readb(ctlr.speed); 583 if (ich->speed >= 33000000) 584 byte |= SSFC_SCF_33MHZ; 585 else 586 byte &= ~SSFC_SCF_33MHZ; 587 ich_writeb(byte, ctlr.speed); 588 } 589 590 /* See if we have used up the command data */ 591 if (using_cmd && dout && bytes) { 592 trans->out = dout; 593 trans->bytesout = bytes; 594 debug("ICH SPI: Moving to data, %d bytes\n", bytes); 595 } 596 597 /* Preset control fields */ 598 control = ich_readw(ctlr.control); 599 control &= ~SSFC_RESERVED; 600 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 601 602 /* Issue atomic preop cycle if needed */ 603 if (ich_readw(ctlr.preop)) 604 control |= SPIC_ACS; 605 606 if (!trans->bytesout && !trans->bytesin) { 607 /* SPI addresses are 24 bit only */ 608 if (with_address) 609 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 610 611 /* 612 * This is a 'no data' command (like Write Enable), its 613 * bitesout size was 1, decremented to zero while executing 614 * spi_setup_opcode() above. Tell the chip to send the 615 * command. 616 */ 617 ich_writew(control, ctlr.control); 618 619 /* wait for the result */ 620 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 621 if (status == -1) 622 return -1; 623 624 if (status & SPIS_FCERR) { 625 debug("ICH SPI: Command transaction error\n"); 626 return -1; 627 } 628 629 return 0; 630 } 631 632 /* 633 * Check if this is a write command atempting to transfer more bytes 634 * than the controller can handle. Iterations for writes are not 635 * supported here because each SPI write command needs to be preceded 636 * and followed by other SPI commands, and this sequence is controlled 637 * by the SPI chip driver. 638 */ 639 if (trans->bytesout > ctlr.databytes) { 640 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 641 return -1; 642 } 643 644 /* 645 * Read or write up to databytes bytes at a time until everything has 646 * been sent. 647 */ 648 while (trans->bytesout || trans->bytesin) { 649 uint32_t data_length; 650 651 /* SPI addresses are 24 bit only */ 652 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 653 654 if (trans->bytesout) 655 data_length = min(trans->bytesout, ctlr.databytes); 656 else 657 data_length = min(trans->bytesin, ctlr.databytes); 658 659 /* Program data into FDATA0 to N */ 660 if (trans->bytesout) { 661 write_reg(trans->out, ctlr.data, data_length); 662 spi_use_out(trans, data_length); 663 if (with_address) 664 trans->offset += data_length; 665 } 666 667 /* Add proper control fields' values */ 668 control &= ~((ctlr.databytes - 1) << 8); 669 control |= SPIC_DS; 670 control |= (data_length - 1) << 8; 671 672 /* write it */ 673 ich_writew(control, ctlr.control); 674 675 /* Wait for Cycle Done Status or Flash Cycle Error. */ 676 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 677 if (status == -1) 678 return -1; 679 680 if (status & SPIS_FCERR) { 681 debug("ICH SPI: Data transaction error\n"); 682 return -1; 683 } 684 685 if (trans->bytesin) { 686 read_reg(ctlr.data, trans->in, data_length); 687 spi_use_in(trans, data_length); 688 if (with_address) 689 trans->offset += data_length; 690 } 691 } 692 693 /* Clear atomic preop now that xfer is done */ 694 ich_writew(0, ctlr.preop); 695 696 return 0; 697 } 698 699 700 /* 701 * This uses the SPI controller from the Intel Cougar Point and Panther Point 702 * PCH to write-protect portions of the SPI flash until reboot. The changes 703 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 704 * done elsewhere. 705 */ 706 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) 707 { 708 uint32_t tmplong; 709 uint32_t upper_limit; 710 711 if (!ctlr.pr) { 712 printf("%s: operation not supported on this chipset\n", 713 __func__); 714 return -1; 715 } 716 717 if (length == 0 || 718 lower_limit > (0xFFFFFFFFUL - length) + 1 || 719 hint < 0 || hint > 4) { 720 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 721 lower_limit, length, hint); 722 return -1; 723 } 724 725 upper_limit = lower_limit + length - 1; 726 727 /* 728 * Determine bits to write, as follows: 729 * 31 Write-protection enable (includes erase operation) 730 * 30:29 reserved 731 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 732 * 15 Read-protection enable 733 * 14:13 reserved 734 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 735 */ 736 tmplong = 0x80000000 | 737 ((upper_limit & 0x01fff000) << 4) | 738 ((lower_limit & 0x01fff000) >> 12); 739 740 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 741 &ctlr.pr[hint]); 742 ctlr.pr[hint] = tmplong; 743 744 return 0; 745 } 746