1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <spi.h> 13 #include <pci.h> 14 #include <pci_ids.h> 15 #include <asm/io.h> 16 17 #include "ich.h" 18 19 #define SPI_OPCODE_WREN 0x06 20 #define SPI_OPCODE_FAST_READ 0x0b 21 22 struct ich_ctlr { 23 pci_dev_t dev; /* PCI device number */ 24 int ich_version; /* Controller version, 7 or 9 */ 25 bool use_sbase; /* Use SBASE instead of RCB */ 26 int ichspi_lock; 27 int locked; 28 uint8_t *opmenu; 29 int menubytes; 30 void *base; /* Base of register set */ 31 uint16_t *preop; 32 uint16_t *optype; 33 uint32_t *addr; 34 uint8_t *data; 35 unsigned databytes; 36 uint8_t *status; 37 uint16_t *control; 38 uint32_t *bbar; 39 uint32_t *pr; /* only for ich9 */ 40 uint8_t *speed; /* pointer to speed control */ 41 ulong max_speed; /* Maximum bus speed in MHz */ 42 }; 43 44 struct ich_ctlr ctlr; 45 46 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) 47 { 48 return container_of(slave, struct ich_spi_slave, slave); 49 } 50 51 static unsigned int ich_reg(const void *addr) 52 { 53 return (unsigned)(addr - ctlr.base) & 0xffff; 54 } 55 56 static u8 ich_readb(const void *addr) 57 { 58 u8 value = readb(addr); 59 60 debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); 61 62 return value; 63 } 64 65 static u16 ich_readw(const void *addr) 66 { 67 u16 value = readw(addr); 68 69 debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); 70 71 return value; 72 } 73 74 static u32 ich_readl(const void *addr) 75 { 76 u32 value = readl(addr); 77 78 debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); 79 80 return value; 81 } 82 83 static void ich_writeb(u8 value, void *addr) 84 { 85 writeb(value, addr); 86 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); 87 } 88 89 static void ich_writew(u16 value, void *addr) 90 { 91 writew(value, addr); 92 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); 93 } 94 95 static void ich_writel(u32 value, void *addr) 96 { 97 writel(value, addr); 98 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); 99 } 100 101 static void write_reg(const void *value, void *dest, uint32_t size) 102 { 103 memcpy_toio(dest, value, size); 104 } 105 106 static void read_reg(const void *src, void *value, uint32_t size) 107 { 108 memcpy_fromio(value, src, size); 109 } 110 111 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) 112 { 113 const uint32_t bbar_mask = 0x00ffff00; 114 uint32_t ichspi_bbar; 115 116 minaddr &= bbar_mask; 117 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; 118 ichspi_bbar |= minaddr; 119 ich_writel(ichspi_bbar, ctlr->bbar); 120 } 121 122 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 123 { 124 puts("spi_cs_is_valid used but not implemented\n"); 125 return 0; 126 } 127 128 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 129 unsigned int max_hz, unsigned int mode) 130 { 131 struct ich_spi_slave *ich; 132 133 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); 134 if (!ich) { 135 puts("ICH SPI: Out of memory\n"); 136 return NULL; 137 } 138 139 /* 140 * Yes this controller can only write a small number of bytes at 141 * once! The limit is typically 64 bytes. 142 */ 143 ich->slave.max_write_size = ctlr.databytes; 144 ich->speed = max_hz; 145 146 /* 147 * ICH 7 SPI controller only supports array read command 148 * and byte program command for SST flash 149 */ 150 if (ctlr.ich_version == 7 || ctlr.use_sbase) { 151 ich->slave.op_mode_rx = SPI_OPM_RX_AS; 152 ich->slave.op_mode_tx = SPI_OPM_TX_BP; 153 } 154 155 return &ich->slave; 156 } 157 158 struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, 159 int spi_node) 160 { 161 /* We only support a single SPI at present */ 162 return spi_setup_slave(0, 0, 20000000, 0); 163 } 164 165 void spi_free_slave(struct spi_slave *slave) 166 { 167 struct ich_spi_slave *ich = to_ich_spi(slave); 168 169 free(ich); 170 } 171 172 /* 173 * Check if this device ID matches one of supported Intel PCH devices. 174 * 175 * Return the ICH version if there is a match, or zero otherwise. 176 */ 177 static int get_ich_version(uint16_t device_id) 178 { 179 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || 180 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || 181 device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) 182 return 7; 183 184 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 185 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 186 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 187 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || 188 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || 189 device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC) 190 return 9; 191 192 return 0; 193 } 194 195 /* @return 1 if the SPI flash supports the 33MHz speed */ 196 static int ich9_can_do_33mhz(pci_dev_t dev) 197 { 198 u32 fdod, speed; 199 200 /* Observe SPI Descriptor Component Section 0 */ 201 pci_write_config_dword(dev, 0xb0, 0x1000); 202 203 /* Extract the Write/Erase SPI Frequency from descriptor */ 204 pci_read_config_dword(dev, 0xb4, &fdod); 205 206 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 207 speed = (fdod >> 21) & 7; 208 209 return speed == 1; 210 } 211 212 static int ich_find_spi_controller(struct ich_ctlr *ich) 213 { 214 int last_bus = pci_last_busno(); 215 int bus; 216 217 if (last_bus == -1) { 218 debug("No PCI busses?\n"); 219 return -ENODEV; 220 } 221 222 for (bus = 0; bus <= last_bus; bus++) { 223 uint16_t vendor_id, device_id; 224 uint32_t ids; 225 pci_dev_t dev; 226 227 dev = PCI_BDF(bus, 31, 0); 228 pci_read_config_dword(dev, 0, &ids); 229 vendor_id = ids; 230 device_id = ids >> 16; 231 232 if (vendor_id == PCI_VENDOR_ID_INTEL) { 233 ich->dev = dev; 234 ich->ich_version = get_ich_version(device_id); 235 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) 236 ich->use_sbase = true; 237 return ich->ich_version == 0 ? -ENODEV : 0; 238 } 239 } 240 241 debug("ICH SPI: No ICH found.\n"); 242 return -ENODEV; 243 } 244 245 static int ich_init_controller(struct ich_ctlr *ctlr) 246 { 247 uint8_t *rcrb; /* Root Complex Register Block */ 248 uint32_t rcba; /* Root Complex Base Address */ 249 uint32_t sbase_addr; 250 uint8_t *sbase; 251 252 pci_read_config_dword(ctlr->dev, 0xf0, &rcba); 253 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 254 rcrb = (uint8_t *)(rcba & 0xffffc000); 255 256 /* SBASE is similar */ 257 pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr); 258 sbase = (uint8_t *)(sbase_addr & 0xfffffe00); 259 260 if (ctlr->ich_version == 7) { 261 struct ich7_spi_regs *ich7_spi; 262 263 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 264 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; 265 ctlr->opmenu = ich7_spi->opmenu; 266 ctlr->menubytes = sizeof(ich7_spi->opmenu); 267 ctlr->optype = &ich7_spi->optype; 268 ctlr->addr = &ich7_spi->spia; 269 ctlr->data = (uint8_t *)ich7_spi->spid; 270 ctlr->databytes = sizeof(ich7_spi->spid); 271 ctlr->status = (uint8_t *)&ich7_spi->spis; 272 ctlr->control = &ich7_spi->spic; 273 ctlr->bbar = &ich7_spi->bbar; 274 ctlr->preop = &ich7_spi->preop; 275 ctlr->base = ich7_spi; 276 } else if (ctlr->ich_version == 9) { 277 struct ich9_spi_regs *ich9_spi; 278 279 if (ctlr->use_sbase) 280 ich9_spi = (struct ich9_spi_regs *)sbase; 281 else 282 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 283 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 284 ctlr->opmenu = ich9_spi->opmenu; 285 ctlr->menubytes = sizeof(ich9_spi->opmenu); 286 ctlr->optype = &ich9_spi->optype; 287 ctlr->addr = &ich9_spi->faddr; 288 ctlr->data = (uint8_t *)ich9_spi->fdata; 289 ctlr->databytes = sizeof(ich9_spi->fdata); 290 ctlr->status = &ich9_spi->ssfs; 291 ctlr->control = (uint16_t *)ich9_spi->ssfc; 292 ctlr->speed = ich9_spi->ssfc + 2; 293 ctlr->bbar = &ich9_spi->bbar; 294 ctlr->preop = &ich9_spi->preop; 295 ctlr->pr = &ich9_spi->pr[0]; 296 ctlr->base = ich9_spi; 297 } else { 298 debug("ICH SPI: Unrecognized ICH version %d.\n", 299 ctlr->ich_version); 300 return -1; 301 } 302 303 /* Work out the maximum speed we can support */ 304 ctlr->max_speed = 20000000; 305 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) 306 ctlr->max_speed = 33000000; 307 debug("ICH SPI: Version %d detected at %p, speed %ld\n", 308 ctlr->ich_version, ctlr->base, ctlr->max_speed); 309 310 ich_set_bbar(ctlr, 0); 311 312 return 0; 313 } 314 315 void spi_init(void) 316 { 317 uint8_t bios_cntl; 318 319 if (ich_find_spi_controller(&ctlr)) { 320 printf("ICH SPI: Cannot find device\n"); 321 return; 322 } 323 324 if (ich_init_controller(&ctlr)) { 325 printf("ICH SPI: Cannot setup controller\n"); 326 return; 327 } 328 329 /* 330 * Disable the BIOS write protect so write commands are allowed. On 331 * v9, deassert SMM BIOS Write Protect Disable. 332 */ 333 if (ctlr.use_sbase) { 334 struct ich9_spi_regs *ich9_spi; 335 336 ich9_spi = (struct ich9_spi_regs *)ctlr.base; 337 bios_cntl = ich_readb(&ich9_spi->bcr); 338 bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ 339 bios_cntl |= 1; /* Write Protect Disable (WPD) */ 340 ich_writeb(bios_cntl, &ich9_spi->bcr); 341 } else { 342 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); 343 if (ctlr.ich_version == 9) 344 bios_cntl &= ~(1 << 5); 345 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); 346 } 347 } 348 349 int spi_claim_bus(struct spi_slave *slave) 350 { 351 /* Handled by ICH automatically. */ 352 return 0; 353 } 354 355 void spi_release_bus(struct spi_slave *slave) 356 { 357 /* Handled by ICH automatically. */ 358 } 359 360 void spi_cs_activate(struct spi_slave *slave) 361 { 362 /* Handled by ICH automatically. */ 363 } 364 365 void spi_cs_deactivate(struct spi_slave *slave) 366 { 367 /* Handled by ICH automatically. */ 368 } 369 370 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 371 { 372 trans->out += bytes; 373 trans->bytesout -= bytes; 374 } 375 376 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 377 { 378 trans->in += bytes; 379 trans->bytesin -= bytes; 380 } 381 382 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 383 { 384 trans->type = 0xFF; 385 386 /* Try to guess spi type from read/write sizes. */ 387 if (trans->bytesin == 0) { 388 if (trans->bytesout + data_bytes > 4) 389 /* 390 * If bytesin = 0 and bytesout > 4, we presume this is 391 * a write data operation, which is accompanied by an 392 * address. 393 */ 394 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 395 else 396 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 397 return; 398 } 399 400 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 401 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 402 return; 403 } 404 405 if (trans->bytesout == 4) /* and bytesin is > 0 */ 406 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 407 408 /* Fast read command is called with 5 bytes instead of 4 */ 409 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 410 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 411 --trans->bytesout; 412 } 413 } 414 415 static int spi_setup_opcode(struct spi_trans *trans) 416 { 417 uint16_t optypes; 418 uint8_t opmenu[ctlr.menubytes]; 419 420 trans->opcode = trans->out[0]; 421 spi_use_out(trans, 1); 422 if (!ctlr.ichspi_lock) { 423 /* The lock is off, so just use index 0. */ 424 ich_writeb(trans->opcode, ctlr.opmenu); 425 optypes = ich_readw(ctlr.optype); 426 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 427 ich_writew(optypes, ctlr.optype); 428 return 0; 429 } else { 430 /* The lock is on. See if what we need is on the menu. */ 431 uint8_t optype; 432 uint16_t opcode_index; 433 434 /* Write Enable is handled as atomic prefix */ 435 if (trans->opcode == SPI_OPCODE_WREN) 436 return 0; 437 438 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); 439 for (opcode_index = 0; opcode_index < ctlr.menubytes; 440 opcode_index++) { 441 if (opmenu[opcode_index] == trans->opcode) 442 break; 443 } 444 445 if (opcode_index == ctlr.menubytes) { 446 printf("ICH SPI: Opcode %x not found\n", 447 trans->opcode); 448 return -1; 449 } 450 451 optypes = ich_readw(ctlr.optype); 452 optype = (optypes >> (opcode_index * 2)) & 0x3; 453 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 454 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 455 trans->bytesout >= 3) { 456 /* We guessed wrong earlier. Fix it up. */ 457 trans->type = optype; 458 } 459 if (optype != trans->type) { 460 printf("ICH SPI: Transaction doesn't fit type %d\n", 461 optype); 462 return -1; 463 } 464 return opcode_index; 465 } 466 } 467 468 static int spi_setup_offset(struct spi_trans *trans) 469 { 470 /* Separate the SPI address and data. */ 471 switch (trans->type) { 472 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 473 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 474 return 0; 475 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 476 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 477 trans->offset = ((uint32_t)trans->out[0] << 16) | 478 ((uint32_t)trans->out[1] << 8) | 479 ((uint32_t)trans->out[2] << 0); 480 spi_use_out(trans, 3); 481 return 1; 482 default: 483 printf("Unrecognized SPI transaction type %#x\n", trans->type); 484 return -1; 485 } 486 } 487 488 /* 489 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 490 * below is true) or 0. In case the wait was for the bit(s) to set - write 491 * those bits back, which would cause resetting them. 492 * 493 * Return the last read status value on success or -1 on failure. 494 */ 495 static int ich_status_poll(u16 bitmask, int wait_til_set) 496 { 497 int timeout = 600000; /* This will result in 6s */ 498 u16 status = 0; 499 500 while (timeout--) { 501 status = ich_readw(ctlr.status); 502 if (wait_til_set ^ ((status & bitmask) == 0)) { 503 if (wait_til_set) 504 ich_writew((status & bitmask), ctlr.status); 505 return status; 506 } 507 udelay(10); 508 } 509 510 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 511 status, bitmask); 512 return -1; 513 } 514 515 /* 516 int spi_xfer(struct spi_slave *slave, const void *dout, 517 unsigned int bitsout, void *din, unsigned int bitsin) 518 */ 519 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 520 void *din, unsigned long flags) 521 { 522 struct ich_spi_slave *ich = to_ich_spi(slave); 523 uint16_t control; 524 int16_t opcode_index; 525 int with_address; 526 int status; 527 int bytes = bitlen / 8; 528 struct spi_trans *trans = &ich->trans; 529 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 530 int using_cmd = 0; 531 532 /* Ee don't support writing partial bytes. */ 533 if (bitlen % 8) { 534 debug("ICH SPI: Accessing partial bytes not supported\n"); 535 return -1; 536 } 537 538 /* An empty end transaction can be ignored */ 539 if (type == SPI_XFER_END && !dout && !din) 540 return 0; 541 542 if (type & SPI_XFER_BEGIN) 543 memset(trans, '\0', sizeof(*trans)); 544 545 /* Dp we need to come back later to finish it? */ 546 if (dout && type == SPI_XFER_BEGIN) { 547 if (bytes > ICH_MAX_CMD_LEN) { 548 debug("ICH SPI: Command length limit exceeded\n"); 549 return -1; 550 } 551 memcpy(trans->cmd, dout, bytes); 552 trans->cmd_len = bytes; 553 debug("ICH SPI: Saved %d bytes\n", bytes); 554 return 0; 555 } 556 557 /* 558 * We process a 'middle' spi_xfer() call, which has no 559 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 560 * an end. We therefore repeat the command. This is because ICH 561 * seems to have no support for this, or because interest (in digging 562 * out the details and creating a special case in the code) is low. 563 */ 564 if (trans->cmd_len) { 565 trans->out = trans->cmd; 566 trans->bytesout = trans->cmd_len; 567 using_cmd = 1; 568 debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 569 } else { 570 trans->out = dout; 571 trans->bytesout = dout ? bytes : 0; 572 } 573 574 trans->in = din; 575 trans->bytesin = din ? bytes : 0; 576 577 /* There has to always at least be an opcode. */ 578 if (!trans->bytesout) { 579 debug("ICH SPI: No opcode for transfer\n"); 580 return -1; 581 } 582 583 if (ich_status_poll(SPIS_SCIP, 0) == -1) 584 return -1; 585 586 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); 587 588 spi_setup_type(trans, using_cmd ? bytes : 0); 589 opcode_index = spi_setup_opcode(trans); 590 if (opcode_index < 0) 591 return -1; 592 with_address = spi_setup_offset(trans); 593 if (with_address < 0) 594 return -1; 595 596 if (trans->opcode == SPI_OPCODE_WREN) { 597 /* 598 * Treat Write Enable as Atomic Pre-Op if possible 599 * in order to prevent the Management Engine from 600 * issuing a transaction between WREN and DATA. 601 */ 602 if (!ctlr.ichspi_lock) 603 ich_writew(trans->opcode, ctlr.preop); 604 return 0; 605 } 606 607 if (ctlr.speed && ctlr.max_speed >= 33000000) { 608 int byte; 609 610 byte = ich_readb(ctlr.speed); 611 if (ich->speed >= 33000000) 612 byte |= SSFC_SCF_33MHZ; 613 else 614 byte &= ~SSFC_SCF_33MHZ; 615 ich_writeb(byte, ctlr.speed); 616 } 617 618 /* See if we have used up the command data */ 619 if (using_cmd && dout && bytes) { 620 trans->out = dout; 621 trans->bytesout = bytes; 622 debug("ICH SPI: Moving to data, %d bytes\n", bytes); 623 } 624 625 /* Preset control fields */ 626 control = ich_readw(ctlr.control); 627 control &= ~SSFC_RESERVED; 628 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 629 630 /* Issue atomic preop cycle if needed */ 631 if (ich_readw(ctlr.preop)) 632 control |= SPIC_ACS; 633 634 if (!trans->bytesout && !trans->bytesin) { 635 /* SPI addresses are 24 bit only */ 636 if (with_address) 637 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 638 639 /* 640 * This is a 'no data' command (like Write Enable), its 641 * bitesout size was 1, decremented to zero while executing 642 * spi_setup_opcode() above. Tell the chip to send the 643 * command. 644 */ 645 ich_writew(control, ctlr.control); 646 647 /* wait for the result */ 648 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 649 if (status == -1) 650 return -1; 651 652 if (status & SPIS_FCERR) { 653 debug("ICH SPI: Command transaction error\n"); 654 return -1; 655 } 656 657 return 0; 658 } 659 660 /* 661 * Check if this is a write command atempting to transfer more bytes 662 * than the controller can handle. Iterations for writes are not 663 * supported here because each SPI write command needs to be preceded 664 * and followed by other SPI commands, and this sequence is controlled 665 * by the SPI chip driver. 666 */ 667 if (trans->bytesout > ctlr.databytes) { 668 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 669 return -1; 670 } 671 672 /* 673 * Read or write up to databytes bytes at a time until everything has 674 * been sent. 675 */ 676 while (trans->bytesout || trans->bytesin) { 677 uint32_t data_length; 678 679 /* SPI addresses are 24 bit only */ 680 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 681 682 if (trans->bytesout) 683 data_length = min(trans->bytesout, ctlr.databytes); 684 else 685 data_length = min(trans->bytesin, ctlr.databytes); 686 687 /* Program data into FDATA0 to N */ 688 if (trans->bytesout) { 689 write_reg(trans->out, ctlr.data, data_length); 690 spi_use_out(trans, data_length); 691 if (with_address) 692 trans->offset += data_length; 693 } 694 695 /* Add proper control fields' values */ 696 control &= ~((ctlr.databytes - 1) << 8); 697 control |= SPIC_DS; 698 control |= (data_length - 1) << 8; 699 700 /* write it */ 701 ich_writew(control, ctlr.control); 702 703 /* Wait for Cycle Done Status or Flash Cycle Error. */ 704 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 705 if (status == -1) 706 return -1; 707 708 if (status & SPIS_FCERR) { 709 debug("ICH SPI: Data transaction error\n"); 710 return -1; 711 } 712 713 if (trans->bytesin) { 714 read_reg(ctlr.data, trans->in, data_length); 715 spi_use_in(trans, data_length); 716 if (with_address) 717 trans->offset += data_length; 718 } 719 } 720 721 /* Clear atomic preop now that xfer is done */ 722 ich_writew(0, ctlr.preop); 723 724 return 0; 725 } 726 727 728 /* 729 * This uses the SPI controller from the Intel Cougar Point and Panther Point 730 * PCH to write-protect portions of the SPI flash until reboot. The changes 731 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 732 * done elsewhere. 733 */ 734 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) 735 { 736 uint32_t tmplong; 737 uint32_t upper_limit; 738 739 if (!ctlr.pr) { 740 printf("%s: operation not supported on this chipset\n", 741 __func__); 742 return -1; 743 } 744 745 if (length == 0 || 746 lower_limit > (0xFFFFFFFFUL - length) + 1 || 747 hint < 0 || hint > 4) { 748 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 749 lower_limit, length, hint); 750 return -1; 751 } 752 753 upper_limit = lower_limit + length - 1; 754 755 /* 756 * Determine bits to write, as follows: 757 * 31 Write-protection enable (includes erase operation) 758 * 30:29 reserved 759 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 760 * 15 Read-protection enable 761 * 14:13 reserved 762 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 763 */ 764 tmplong = 0x80000000 | 765 ((upper_limit & 0x01fff000) << 4) | 766 ((lower_limit & 0x01fff000) >> 12); 767 768 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 769 &ctlr.pr[hint]); 770 ctlr.pr[hint] = tmplong; 771 772 return 0; 773 } 774