1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <pch.h> 13 #include <pci.h> 14 #include <pci_ids.h> 15 #include <spi.h> 16 #include <asm/io.h> 17 18 #include "ich.h" 19 20 #define SPI_OPCODE_WREN 0x06 21 #define SPI_OPCODE_FAST_READ 0x0b 22 23 #ifdef DEBUG_TRACE 24 #define debug_trace(fmt, args...) debug(fmt, ##args) 25 #else 26 #define debug_trace(x, args...) 27 #endif 28 29 struct ich_spi_platdata { 30 enum pch_version ich_version; /* Controller version, 7 or 9 */ 31 }; 32 33 struct ich_spi_priv { 34 int ichspi_lock; 35 int locked; 36 int opmenu; 37 int menubytes; 38 void *base; /* Base of register set */ 39 int preop; 40 int optype; 41 int addr; 42 int data; 43 unsigned databytes; 44 int status; 45 int control; 46 int bbar; 47 int bcr; 48 uint32_t *pr; /* only for ich9 */ 49 int speed; /* pointer to speed control */ 50 ulong max_speed; /* Maximum bus speed in MHz */ 51 ulong cur_speed; /* Current bus speed */ 52 struct spi_trans trans; /* current transaction in progress */ 53 }; 54 55 static u8 ich_readb(struct ich_spi_priv *priv, int reg) 56 { 57 u8 value = readb(priv->base + reg); 58 59 debug_trace("read %2.2x from %4.4x\n", value, reg); 60 61 return value; 62 } 63 64 static u16 ich_readw(struct ich_spi_priv *priv, int reg) 65 { 66 u16 value = readw(priv->base + reg); 67 68 debug_trace("read %4.4x from %4.4x\n", value, reg); 69 70 return value; 71 } 72 73 static u32 ich_readl(struct ich_spi_priv *priv, int reg) 74 { 75 u32 value = readl(priv->base + reg); 76 77 debug_trace("read %8.8x from %4.4x\n", value, reg); 78 79 return value; 80 } 81 82 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) 83 { 84 writeb(value, priv->base + reg); 85 debug_trace("wrote %2.2x to %4.4x\n", value, reg); 86 } 87 88 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) 89 { 90 writew(value, priv->base + reg); 91 debug_trace("wrote %4.4x to %4.4x\n", value, reg); 92 } 93 94 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) 95 { 96 writel(value, priv->base + reg); 97 debug_trace("wrote %8.8x to %4.4x\n", value, reg); 98 } 99 100 static void write_reg(struct ich_spi_priv *priv, const void *value, 101 int dest_reg, uint32_t size) 102 { 103 memcpy_toio(priv->base + dest_reg, value, size); 104 } 105 106 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, 107 uint32_t size) 108 { 109 memcpy_fromio(value, priv->base + src_reg, size); 110 } 111 112 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) 113 { 114 const uint32_t bbar_mask = 0x00ffff00; 115 uint32_t ichspi_bbar; 116 117 minaddr &= bbar_mask; 118 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; 119 ichspi_bbar |= minaddr; 120 ich_writel(ctlr, ichspi_bbar, ctlr->bbar); 121 } 122 123 /* @return 1 if the SPI flash supports the 33MHz speed */ 124 static int ich9_can_do_33mhz(struct udevice *dev) 125 { 126 u32 fdod, speed; 127 128 /* Observe SPI Descriptor Component Section 0 */ 129 dm_pci_write_config32(dev->parent, 0xb0, 0x1000); 130 131 /* Extract the Write/Erase SPI Frequency from descriptor */ 132 dm_pci_read_config32(dev->parent, 0xb4, &fdod); 133 134 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 135 speed = (fdod >> 21) & 7; 136 137 return speed == 1; 138 } 139 140 static int ich_init_controller(struct udevice *dev, 141 struct ich_spi_platdata *plat, 142 struct ich_spi_priv *ctlr) 143 { 144 ulong sbase_addr; 145 void *sbase; 146 147 /* SBASE is similar */ 148 pch_get_sbase(dev->parent, &sbase_addr); 149 sbase = (void *)sbase_addr; 150 debug("%s: sbase=%p\n", __func__, sbase); 151 152 if (plat->ich_version == PCHV_7) { 153 struct ich7_spi_regs *ich7_spi = sbase; 154 155 ich7_spi = (struct ich7_spi_regs *)sbase; 156 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; 157 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); 158 ctlr->menubytes = sizeof(ich7_spi->opmenu); 159 ctlr->optype = offsetof(struct ich7_spi_regs, optype); 160 ctlr->addr = offsetof(struct ich7_spi_regs, spia); 161 ctlr->data = offsetof(struct ich7_spi_regs, spid); 162 ctlr->databytes = sizeof(ich7_spi->spid); 163 ctlr->status = offsetof(struct ich7_spi_regs, spis); 164 ctlr->control = offsetof(struct ich7_spi_regs, spic); 165 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); 166 ctlr->preop = offsetof(struct ich7_spi_regs, preop); 167 ctlr->base = ich7_spi; 168 } else if (plat->ich_version == PCHV_9) { 169 struct ich9_spi_regs *ich9_spi = sbase; 170 171 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 172 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); 173 ctlr->menubytes = sizeof(ich9_spi->opmenu); 174 ctlr->optype = offsetof(struct ich9_spi_regs, optype); 175 ctlr->addr = offsetof(struct ich9_spi_regs, faddr); 176 ctlr->data = offsetof(struct ich9_spi_regs, fdata); 177 ctlr->databytes = sizeof(ich9_spi->fdata); 178 ctlr->status = offsetof(struct ich9_spi_regs, ssfs); 179 ctlr->control = offsetof(struct ich9_spi_regs, ssfc); 180 ctlr->speed = ctlr->control + 2; 181 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); 182 ctlr->preop = offsetof(struct ich9_spi_regs, preop); 183 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); 184 ctlr->pr = &ich9_spi->pr[0]; 185 ctlr->base = ich9_spi; 186 } else { 187 debug("ICH SPI: Unrecognised ICH version %d\n", 188 plat->ich_version); 189 return -EINVAL; 190 } 191 192 /* Work out the maximum speed we can support */ 193 ctlr->max_speed = 20000000; 194 if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev)) 195 ctlr->max_speed = 33000000; 196 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", 197 plat->ich_version, ctlr->base, ctlr->max_speed); 198 199 ich_set_bbar(ctlr, 0); 200 201 return 0; 202 } 203 204 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 205 { 206 trans->out += bytes; 207 trans->bytesout -= bytes; 208 } 209 210 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 211 { 212 trans->in += bytes; 213 trans->bytesin -= bytes; 214 } 215 216 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 217 { 218 trans->type = 0xFF; 219 220 /* Try to guess spi type from read/write sizes. */ 221 if (trans->bytesin == 0) { 222 if (trans->bytesout + data_bytes > 4) 223 /* 224 * If bytesin = 0 and bytesout > 4, we presume this is 225 * a write data operation, which is accompanied by an 226 * address. 227 */ 228 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 229 else 230 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 231 return; 232 } 233 234 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 235 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 236 return; 237 } 238 239 if (trans->bytesout == 4) /* and bytesin is > 0 */ 240 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 241 242 /* Fast read command is called with 5 bytes instead of 4 */ 243 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 244 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 245 --trans->bytesout; 246 } 247 } 248 249 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) 250 { 251 uint16_t optypes; 252 uint8_t opmenu[ctlr->menubytes]; 253 254 trans->opcode = trans->out[0]; 255 spi_use_out(trans, 1); 256 if (!ctlr->ichspi_lock) { 257 /* The lock is off, so just use index 0. */ 258 ich_writeb(ctlr, trans->opcode, ctlr->opmenu); 259 optypes = ich_readw(ctlr, ctlr->optype); 260 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 261 ich_writew(ctlr, optypes, ctlr->optype); 262 return 0; 263 } else { 264 /* The lock is on. See if what we need is on the menu. */ 265 uint8_t optype; 266 uint16_t opcode_index; 267 268 /* Write Enable is handled as atomic prefix */ 269 if (trans->opcode == SPI_OPCODE_WREN) 270 return 0; 271 272 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); 273 for (opcode_index = 0; opcode_index < ctlr->menubytes; 274 opcode_index++) { 275 if (opmenu[opcode_index] == trans->opcode) 276 break; 277 } 278 279 if (opcode_index == ctlr->menubytes) { 280 printf("ICH SPI: Opcode %x not found\n", 281 trans->opcode); 282 return -EINVAL; 283 } 284 285 optypes = ich_readw(ctlr, ctlr->optype); 286 optype = (optypes >> (opcode_index * 2)) & 0x3; 287 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 288 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 289 trans->bytesout >= 3) { 290 /* We guessed wrong earlier. Fix it up. */ 291 trans->type = optype; 292 } 293 if (optype != trans->type) { 294 printf("ICH SPI: Transaction doesn't fit type %d\n", 295 optype); 296 return -ENOSPC; 297 } 298 return opcode_index; 299 } 300 } 301 302 static int spi_setup_offset(struct spi_trans *trans) 303 { 304 /* Separate the SPI address and data. */ 305 switch (trans->type) { 306 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 307 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 308 return 0; 309 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 310 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 311 trans->offset = ((uint32_t)trans->out[0] << 16) | 312 ((uint32_t)trans->out[1] << 8) | 313 ((uint32_t)trans->out[2] << 0); 314 spi_use_out(trans, 3); 315 return 1; 316 default: 317 printf("Unrecognized SPI transaction type %#x\n", trans->type); 318 return -EPROTO; 319 } 320 } 321 322 /* 323 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 324 * below is true) or 0. In case the wait was for the bit(s) to set - write 325 * those bits back, which would cause resetting them. 326 * 327 * Return the last read status value on success or -1 on failure. 328 */ 329 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, 330 int wait_til_set) 331 { 332 int timeout = 600000; /* This will result in 6s */ 333 u16 status = 0; 334 335 while (timeout--) { 336 status = ich_readw(ctlr, ctlr->status); 337 if (wait_til_set ^ ((status & bitmask) == 0)) { 338 if (wait_til_set) { 339 ich_writew(ctlr, status & bitmask, 340 ctlr->status); 341 } 342 return status; 343 } 344 udelay(10); 345 } 346 347 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 348 status, bitmask); 349 return -ETIMEDOUT; 350 } 351 352 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, 353 const void *dout, void *din, unsigned long flags) 354 { 355 struct udevice *bus = dev_get_parent(dev); 356 struct ich_spi_platdata *plat = dev_get_platdata(bus); 357 struct ich_spi_priv *ctlr = dev_get_priv(bus); 358 uint16_t control; 359 int16_t opcode_index; 360 int with_address; 361 int status; 362 int bytes = bitlen / 8; 363 struct spi_trans *trans = &ctlr->trans; 364 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 365 int using_cmd = 0; 366 int ret; 367 368 /* We don't support writing partial bytes */ 369 if (bitlen % 8) { 370 debug("ICH SPI: Accessing partial bytes not supported\n"); 371 return -EPROTONOSUPPORT; 372 } 373 374 /* An empty end transaction can be ignored */ 375 if (type == SPI_XFER_END && !dout && !din) 376 return 0; 377 378 if (type & SPI_XFER_BEGIN) 379 memset(trans, '\0', sizeof(*trans)); 380 381 /* Dp we need to come back later to finish it? */ 382 if (dout && type == SPI_XFER_BEGIN) { 383 if (bytes > ICH_MAX_CMD_LEN) { 384 debug("ICH SPI: Command length limit exceeded\n"); 385 return -ENOSPC; 386 } 387 memcpy(trans->cmd, dout, bytes); 388 trans->cmd_len = bytes; 389 debug_trace("ICH SPI: Saved %d bytes\n", bytes); 390 return 0; 391 } 392 393 /* 394 * We process a 'middle' spi_xfer() call, which has no 395 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 396 * an end. We therefore repeat the command. This is because ICH 397 * seems to have no support for this, or because interest (in digging 398 * out the details and creating a special case in the code) is low. 399 */ 400 if (trans->cmd_len) { 401 trans->out = trans->cmd; 402 trans->bytesout = trans->cmd_len; 403 using_cmd = 1; 404 debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); 405 } else { 406 trans->out = dout; 407 trans->bytesout = dout ? bytes : 0; 408 } 409 410 trans->in = din; 411 trans->bytesin = din ? bytes : 0; 412 413 /* There has to always at least be an opcode. */ 414 if (!trans->bytesout) { 415 debug("ICH SPI: No opcode for transfer\n"); 416 return -EPROTO; 417 } 418 419 ret = ich_status_poll(ctlr, SPIS_SCIP, 0); 420 if (ret < 0) 421 return ret; 422 423 if (plat->ich_version == PCHV_7) 424 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 425 else 426 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 427 428 spi_setup_type(trans, using_cmd ? bytes : 0); 429 opcode_index = spi_setup_opcode(ctlr, trans); 430 if (opcode_index < 0) 431 return -EINVAL; 432 with_address = spi_setup_offset(trans); 433 if (with_address < 0) 434 return -EINVAL; 435 436 if (trans->opcode == SPI_OPCODE_WREN) { 437 /* 438 * Treat Write Enable as Atomic Pre-Op if possible 439 * in order to prevent the Management Engine from 440 * issuing a transaction between WREN and DATA. 441 */ 442 if (!ctlr->ichspi_lock) 443 ich_writew(ctlr, trans->opcode, ctlr->preop); 444 return 0; 445 } 446 447 if (ctlr->speed && ctlr->max_speed >= 33000000) { 448 int byte; 449 450 byte = ich_readb(ctlr, ctlr->speed); 451 if (ctlr->cur_speed >= 33000000) 452 byte |= SSFC_SCF_33MHZ; 453 else 454 byte &= ~SSFC_SCF_33MHZ; 455 ich_writeb(ctlr, byte, ctlr->speed); 456 } 457 458 /* See if we have used up the command data */ 459 if (using_cmd && dout && bytes) { 460 trans->out = dout; 461 trans->bytesout = bytes; 462 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); 463 } 464 465 /* Preset control fields */ 466 control = ich_readw(ctlr, ctlr->control); 467 control &= ~SSFC_RESERVED; 468 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 469 470 /* Issue atomic preop cycle if needed */ 471 if (ich_readw(ctlr, ctlr->preop)) 472 control |= SPIC_ACS; 473 474 if (!trans->bytesout && !trans->bytesin) { 475 /* SPI addresses are 24 bit only */ 476 if (with_address) { 477 ich_writel(ctlr, trans->offset & 0x00FFFFFF, 478 ctlr->addr); 479 } 480 /* 481 * This is a 'no data' command (like Write Enable), its 482 * bitesout size was 1, decremented to zero while executing 483 * spi_setup_opcode() above. Tell the chip to send the 484 * command. 485 */ 486 ich_writew(ctlr, control, ctlr->control); 487 488 /* wait for the result */ 489 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 490 if (status < 0) 491 return status; 492 493 if (status & SPIS_FCERR) { 494 debug("ICH SPI: Command transaction error\n"); 495 return -EIO; 496 } 497 498 return 0; 499 } 500 501 /* 502 * Check if this is a write command atempting to transfer more bytes 503 * than the controller can handle. Iterations for writes are not 504 * supported here because each SPI write command needs to be preceded 505 * and followed by other SPI commands, and this sequence is controlled 506 * by the SPI chip driver. 507 */ 508 if (trans->bytesout > ctlr->databytes) { 509 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 510 return -EPROTO; 511 } 512 513 /* 514 * Read or write up to databytes bytes at a time until everything has 515 * been sent. 516 */ 517 while (trans->bytesout || trans->bytesin) { 518 uint32_t data_length; 519 520 /* SPI addresses are 24 bit only */ 521 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); 522 523 if (trans->bytesout) 524 data_length = min(trans->bytesout, ctlr->databytes); 525 else 526 data_length = min(trans->bytesin, ctlr->databytes); 527 528 /* Program data into FDATA0 to N */ 529 if (trans->bytesout) { 530 write_reg(ctlr, trans->out, ctlr->data, data_length); 531 spi_use_out(trans, data_length); 532 if (with_address) 533 trans->offset += data_length; 534 } 535 536 /* Add proper control fields' values */ 537 control &= ~((ctlr->databytes - 1) << 8); 538 control |= SPIC_DS; 539 control |= (data_length - 1) << 8; 540 541 /* write it */ 542 ich_writew(ctlr, control, ctlr->control); 543 544 /* Wait for Cycle Done Status or Flash Cycle Error. */ 545 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 546 if (status < 0) 547 return status; 548 549 if (status & SPIS_FCERR) { 550 debug("ICH SPI: Data transaction error %x\n", status); 551 return -EIO; 552 } 553 554 if (trans->bytesin) { 555 read_reg(ctlr, ctlr->data, trans->in, data_length); 556 spi_use_in(trans, data_length); 557 if (with_address) 558 trans->offset += data_length; 559 } 560 } 561 562 /* Clear atomic preop now that xfer is done */ 563 ich_writew(ctlr, 0, ctlr->preop); 564 565 return 0; 566 } 567 568 /* 569 * This uses the SPI controller from the Intel Cougar Point and Panther Point 570 * PCH to write-protect portions of the SPI flash until reboot. The changes 571 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 572 * done elsewhere. 573 */ 574 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, 575 uint32_t length, int hint) 576 { 577 struct udevice *bus = dev->parent; 578 struct ich_spi_priv *ctlr = dev_get_priv(bus); 579 uint32_t tmplong; 580 uint32_t upper_limit; 581 582 if (!ctlr->pr) { 583 printf("%s: operation not supported on this chipset\n", 584 __func__); 585 return -ENOSYS; 586 } 587 588 if (length == 0 || 589 lower_limit > (0xFFFFFFFFUL - length) + 1 || 590 hint < 0 || hint > 4) { 591 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 592 lower_limit, length, hint); 593 return -EPERM; 594 } 595 596 upper_limit = lower_limit + length - 1; 597 598 /* 599 * Determine bits to write, as follows: 600 * 31 Write-protection enable (includes erase operation) 601 * 30:29 reserved 602 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 603 * 15 Read-protection enable 604 * 14:13 reserved 605 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 606 */ 607 tmplong = 0x80000000 | 608 ((upper_limit & 0x01fff000) << 4) | 609 ((lower_limit & 0x01fff000) >> 12); 610 611 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 612 &ctlr->pr[hint]); 613 ctlr->pr[hint] = tmplong; 614 615 return 0; 616 } 617 618 static int ich_spi_probe(struct udevice *dev) 619 { 620 struct ich_spi_platdata *plat = dev_get_platdata(dev); 621 struct ich_spi_priv *priv = dev_get_priv(dev); 622 uint8_t bios_cntl; 623 int ret; 624 625 /* Check the ICH version */ 626 plat->ich_version = pch_get_version(dev->parent); 627 628 ret = ich_init_controller(dev, plat, priv); 629 if (ret) 630 return ret; 631 /* Disable the BIOS write protect so write commands are allowed */ 632 ret = pch_set_spi_protect(dev->parent, false); 633 if (ret == -ENOSYS) { 634 bios_cntl = ich_readb(priv, priv->bcr); 635 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ 636 bios_cntl |= 1; /* Write Protect Disable (WPD) */ 637 ich_writeb(priv, bios_cntl, priv->bcr); 638 } else if (ret) { 639 debug("%s: Failed to disable write-protect: err=%d\n", 640 __func__, ret); 641 return ret; 642 } 643 644 priv->cur_speed = priv->max_speed; 645 646 return 0; 647 } 648 649 static int ich_spi_set_speed(struct udevice *bus, uint speed) 650 { 651 struct ich_spi_priv *priv = dev_get_priv(bus); 652 653 priv->cur_speed = speed; 654 655 return 0; 656 } 657 658 static int ich_spi_set_mode(struct udevice *bus, uint mode) 659 { 660 debug("%s: mode=%d\n", __func__, mode); 661 662 return 0; 663 } 664 665 static int ich_spi_child_pre_probe(struct udevice *dev) 666 { 667 struct udevice *bus = dev_get_parent(dev); 668 struct ich_spi_platdata *plat = dev_get_platdata(bus); 669 struct ich_spi_priv *priv = dev_get_priv(bus); 670 struct spi_slave *slave = dev_get_parent_priv(dev); 671 672 /* 673 * Yes this controller can only write a small number of bytes at 674 * once! The limit is typically 64 bytes. 675 */ 676 slave->max_write_size = priv->databytes; 677 /* 678 * ICH 7 SPI controller only supports array read command 679 * and byte program command for SST flash 680 */ 681 if (plat->ich_version == PCHV_7) { 682 slave->mode_rx = SPI_RX_SLOW; 683 slave->mode = SPI_TX_BYTE; 684 } 685 686 return 0; 687 } 688 689 static const struct dm_spi_ops ich_spi_ops = { 690 .xfer = ich_spi_xfer, 691 .set_speed = ich_spi_set_speed, 692 .set_mode = ich_spi_set_mode, 693 /* 694 * cs_info is not needed, since we require all chip selects to be 695 * in the device tree explicitly 696 */ 697 }; 698 699 static const struct udevice_id ich_spi_ids[] = { 700 { .compatible = "intel,ich-spi" }, 701 { } 702 }; 703 704 U_BOOT_DRIVER(ich_spi) = { 705 .name = "ich_spi", 706 .id = UCLASS_SPI, 707 .of_match = ich_spi_ids, 708 .ops = &ich_spi_ops, 709 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), 710 .priv_auto_alloc_size = sizeof(struct ich_spi_priv), 711 .child_pre_probe = ich_spi_child_pre_probe, 712 .probe = ich_spi_probe, 713 }; 714