1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <pci.h> 13 #include <pci_ids.h> 14 #include <asm/io.h> 15 16 #include "ich.h" 17 18 #define SPI_OPCODE_WREN 0x06 19 #define SPI_OPCODE_FAST_READ 0x0b 20 21 struct ich_ctlr { 22 pci_dev_t dev; /* PCI device number */ 23 int ich_version; /* Controller version, 7 or 9 */ 24 int ichspi_lock; 25 int locked; 26 uint8_t *opmenu; 27 int menubytes; 28 void *base; /* Base of register set */ 29 uint16_t *preop; 30 uint16_t *optype; 31 uint32_t *addr; 32 uint8_t *data; 33 unsigned databytes; 34 uint8_t *status; 35 uint16_t *control; 36 uint32_t *bbar; 37 uint32_t *pr; /* only for ich9 */ 38 uint8_t *speed; /* pointer to speed control */ 39 ulong max_speed; /* Maximum bus speed in MHz */ 40 }; 41 42 struct ich_ctlr ctlr; 43 44 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) 45 { 46 return container_of(slave, struct ich_spi_slave, slave); 47 } 48 49 static unsigned int ich_reg(const void *addr) 50 { 51 return (unsigned)(addr - ctlr.base) & 0xffff; 52 } 53 54 static u8 ich_readb(const void *addr) 55 { 56 u8 value = readb(addr); 57 58 debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); 59 60 return value; 61 } 62 63 static u16 ich_readw(const void *addr) 64 { 65 u16 value = readw(addr); 66 67 debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); 68 69 return value; 70 } 71 72 static u32 ich_readl(const void *addr) 73 { 74 u32 value = readl(addr); 75 76 debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); 77 78 return value; 79 } 80 81 static void ich_writeb(u8 value, void *addr) 82 { 83 writeb(value, addr); 84 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); 85 } 86 87 static void ich_writew(u16 value, void *addr) 88 { 89 writew(value, addr); 90 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); 91 } 92 93 static void ich_writel(u32 value, void *addr) 94 { 95 writel(value, addr); 96 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); 97 } 98 99 static void write_reg(const void *value, void *dest, uint32_t size) 100 { 101 memcpy_toio(dest, value, size); 102 } 103 104 static void read_reg(const void *src, void *value, uint32_t size) 105 { 106 memcpy_fromio(value, src, size); 107 } 108 109 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) 110 { 111 const uint32_t bbar_mask = 0x00ffff00; 112 uint32_t ichspi_bbar; 113 114 minaddr &= bbar_mask; 115 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; 116 ichspi_bbar |= minaddr; 117 ich_writel(ichspi_bbar, ctlr->bbar); 118 } 119 120 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 121 { 122 puts("spi_cs_is_valid used but not implemented\n"); 123 return 0; 124 } 125 126 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 127 unsigned int max_hz, unsigned int mode) 128 { 129 struct ich_spi_slave *ich; 130 131 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); 132 if (!ich) { 133 puts("ICH SPI: Out of memory\n"); 134 return NULL; 135 } 136 137 /* 138 * Yes this controller can only write a small number of bytes at 139 * once! The limit is typically 64 bytes. 140 */ 141 ich->slave.max_write_size = ctlr.databytes; 142 ich->speed = max_hz; 143 144 /* 145 * ICH 7 SPI controller only supports array read command 146 * and byte program command for SST flash 147 */ 148 if (ctlr.ich_version == 7) { 149 ich->slave.op_mode_rx = SPI_OPM_RX_AS; 150 ich->slave.op_mode_tx = SPI_OPM_TX_BP; 151 } 152 153 return &ich->slave; 154 } 155 156 void spi_free_slave(struct spi_slave *slave) 157 { 158 struct ich_spi_slave *ich = to_ich_spi(slave); 159 160 free(ich); 161 } 162 163 /* 164 * Check if this device ID matches one of supported Intel PCH devices. 165 * 166 * Return the ICH version if there is a match, or zero otherwise. 167 */ 168 static int get_ich_version(uint16_t device_id) 169 { 170 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || 171 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC) 172 return 7; 173 174 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 175 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 176 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 177 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) 178 return 9; 179 180 return 0; 181 } 182 183 /* @return 1 if the SPI flash supports the 33MHz speed */ 184 static int ich9_can_do_33mhz(pci_dev_t dev) 185 { 186 u32 fdod, speed; 187 188 /* Observe SPI Descriptor Component Section 0 */ 189 pci_write_config_dword(dev, 0xb0, 0x1000); 190 191 /* Extract the Write/Erase SPI Frequency from descriptor */ 192 pci_read_config_dword(dev, 0xb4, &fdod); 193 194 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 195 speed = (fdod >> 21) & 7; 196 197 return speed == 1; 198 } 199 200 static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) 201 { 202 int last_bus = pci_last_busno(); 203 int bus; 204 205 if (last_bus == -1) { 206 debug("No PCI busses?\n"); 207 return -1; 208 } 209 210 for (bus = 0; bus <= last_bus; bus++) { 211 uint16_t vendor_id, device_id; 212 uint32_t ids; 213 pci_dev_t dev; 214 215 dev = PCI_BDF(bus, 31, 0); 216 pci_read_config_dword(dev, 0, &ids); 217 vendor_id = ids; 218 device_id = ids >> 16; 219 220 if (vendor_id == PCI_VENDOR_ID_INTEL) { 221 *devp = dev; 222 *ich_versionp = get_ich_version(device_id); 223 return 0; 224 } 225 } 226 227 debug("ICH SPI: No ICH found.\n"); 228 return -1; 229 } 230 231 static int ich_init_controller(struct ich_ctlr *ctlr) 232 { 233 uint8_t *rcrb; /* Root Complex Register Block */ 234 uint32_t rcba; /* Root Complex Base Address */ 235 236 pci_read_config_dword(ctlr->dev, 0xf0, &rcba); 237 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 238 rcrb = (uint8_t *)(rcba & 0xffffc000); 239 if (ctlr->ich_version == 7) { 240 struct ich7_spi_regs *ich7_spi; 241 242 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 243 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; 244 ctlr->opmenu = ich7_spi->opmenu; 245 ctlr->menubytes = sizeof(ich7_spi->opmenu); 246 ctlr->optype = &ich7_spi->optype; 247 ctlr->addr = &ich7_spi->spia; 248 ctlr->data = (uint8_t *)ich7_spi->spid; 249 ctlr->databytes = sizeof(ich7_spi->spid); 250 ctlr->status = (uint8_t *)&ich7_spi->spis; 251 ctlr->control = &ich7_spi->spic; 252 ctlr->bbar = &ich7_spi->bbar; 253 ctlr->preop = &ich7_spi->preop; 254 ctlr->base = ich7_spi; 255 } else if (ctlr->ich_version == 9) { 256 struct ich9_spi_regs *ich9_spi; 257 258 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 259 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 260 ctlr->opmenu = ich9_spi->opmenu; 261 ctlr->menubytes = sizeof(ich9_spi->opmenu); 262 ctlr->optype = &ich9_spi->optype; 263 ctlr->addr = &ich9_spi->faddr; 264 ctlr->data = (uint8_t *)ich9_spi->fdata; 265 ctlr->databytes = sizeof(ich9_spi->fdata); 266 ctlr->status = &ich9_spi->ssfs; 267 ctlr->control = (uint16_t *)ich9_spi->ssfc; 268 ctlr->speed = ich9_spi->ssfc + 2; 269 ctlr->bbar = &ich9_spi->bbar; 270 ctlr->preop = &ich9_spi->preop; 271 ctlr->pr = &ich9_spi->pr[0]; 272 ctlr->base = ich9_spi; 273 } else { 274 debug("ICH SPI: Unrecognized ICH version %d.\n", 275 ctlr->ich_version); 276 return -1; 277 } 278 debug("ICH SPI: Version %d detected\n", ctlr->ich_version); 279 280 /* Work out the maximum speed we can support */ 281 ctlr->max_speed = 20000000; 282 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) 283 ctlr->max_speed = 33000000; 284 285 ich_set_bbar(ctlr, 0); 286 287 return 0; 288 } 289 290 void spi_init(void) 291 { 292 uint8_t bios_cntl; 293 294 if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { 295 printf("ICH SPI: Cannot find device\n"); 296 return; 297 } 298 299 if (ich_init_controller(&ctlr)) { 300 printf("ICH SPI: Cannot setup controller\n"); 301 return; 302 } 303 304 /* 305 * Disable the BIOS write protect so write commands are allowed. On 306 * v9, deassert SMM BIOS Write Protect Disable. 307 */ 308 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); 309 if (ctlr.ich_version == 9) 310 bios_cntl &= ~(1 << 5); 311 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); 312 } 313 314 int spi_claim_bus(struct spi_slave *slave) 315 { 316 /* Handled by ICH automatically. */ 317 return 0; 318 } 319 320 void spi_release_bus(struct spi_slave *slave) 321 { 322 /* Handled by ICH automatically. */ 323 } 324 325 void spi_cs_activate(struct spi_slave *slave) 326 { 327 /* Handled by ICH automatically. */ 328 } 329 330 void spi_cs_deactivate(struct spi_slave *slave) 331 { 332 /* Handled by ICH automatically. */ 333 } 334 335 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 336 { 337 trans->out += bytes; 338 trans->bytesout -= bytes; 339 } 340 341 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 342 { 343 trans->in += bytes; 344 trans->bytesin -= bytes; 345 } 346 347 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 348 { 349 trans->type = 0xFF; 350 351 /* Try to guess spi type from read/write sizes. */ 352 if (trans->bytesin == 0) { 353 if (trans->bytesout + data_bytes > 4) 354 /* 355 * If bytesin = 0 and bytesout > 4, we presume this is 356 * a write data operation, which is accompanied by an 357 * address. 358 */ 359 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 360 else 361 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 362 return; 363 } 364 365 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 366 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 367 return; 368 } 369 370 if (trans->bytesout == 4) /* and bytesin is > 0 */ 371 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 372 373 /* Fast read command is called with 5 bytes instead of 4 */ 374 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 375 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 376 --trans->bytesout; 377 } 378 } 379 380 static int spi_setup_opcode(struct spi_trans *trans) 381 { 382 uint16_t optypes; 383 uint8_t opmenu[ctlr.menubytes]; 384 385 trans->opcode = trans->out[0]; 386 spi_use_out(trans, 1); 387 if (!ctlr.ichspi_lock) { 388 /* The lock is off, so just use index 0. */ 389 ich_writeb(trans->opcode, ctlr.opmenu); 390 optypes = ich_readw(ctlr.optype); 391 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 392 ich_writew(optypes, ctlr.optype); 393 return 0; 394 } else { 395 /* The lock is on. See if what we need is on the menu. */ 396 uint8_t optype; 397 uint16_t opcode_index; 398 399 /* Write Enable is handled as atomic prefix */ 400 if (trans->opcode == SPI_OPCODE_WREN) 401 return 0; 402 403 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); 404 for (opcode_index = 0; opcode_index < ctlr.menubytes; 405 opcode_index++) { 406 if (opmenu[opcode_index] == trans->opcode) 407 break; 408 } 409 410 if (opcode_index == ctlr.menubytes) { 411 printf("ICH SPI: Opcode %x not found\n", 412 trans->opcode); 413 return -1; 414 } 415 416 optypes = ich_readw(ctlr.optype); 417 optype = (optypes >> (opcode_index * 2)) & 0x3; 418 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 419 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 420 trans->bytesout >= 3) { 421 /* We guessed wrong earlier. Fix it up. */ 422 trans->type = optype; 423 } 424 if (optype != trans->type) { 425 printf("ICH SPI: Transaction doesn't fit type %d\n", 426 optype); 427 return -1; 428 } 429 return opcode_index; 430 } 431 } 432 433 static int spi_setup_offset(struct spi_trans *trans) 434 { 435 /* Separate the SPI address and data. */ 436 switch (trans->type) { 437 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 438 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 439 return 0; 440 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 441 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 442 trans->offset = ((uint32_t)trans->out[0] << 16) | 443 ((uint32_t)trans->out[1] << 8) | 444 ((uint32_t)trans->out[2] << 0); 445 spi_use_out(trans, 3); 446 return 1; 447 default: 448 printf("Unrecognized SPI transaction type %#x\n", trans->type); 449 return -1; 450 } 451 } 452 453 /* 454 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 455 * below is true) or 0. In case the wait was for the bit(s) to set - write 456 * those bits back, which would cause resetting them. 457 * 458 * Return the last read status value on success or -1 on failure. 459 */ 460 static int ich_status_poll(u16 bitmask, int wait_til_set) 461 { 462 int timeout = 600000; /* This will result in 6s */ 463 u16 status = 0; 464 465 while (timeout--) { 466 status = ich_readw(ctlr.status); 467 if (wait_til_set ^ ((status & bitmask) == 0)) { 468 if (wait_til_set) 469 ich_writew((status & bitmask), ctlr.status); 470 return status; 471 } 472 udelay(10); 473 } 474 475 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 476 status, bitmask); 477 return -1; 478 } 479 480 /* 481 int spi_xfer(struct spi_slave *slave, const void *dout, 482 unsigned int bitsout, void *din, unsigned int bitsin) 483 */ 484 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 485 void *din, unsigned long flags) 486 { 487 struct ich_spi_slave *ich = to_ich_spi(slave); 488 uint16_t control; 489 int16_t opcode_index; 490 int with_address; 491 int status; 492 int bytes = bitlen / 8; 493 struct spi_trans *trans = &ich->trans; 494 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 495 int using_cmd = 0; 496 497 /* Ee don't support writing partial bytes. */ 498 if (bitlen % 8) { 499 debug("ICH SPI: Accessing partial bytes not supported\n"); 500 return -1; 501 } 502 503 /* An empty end transaction can be ignored */ 504 if (type == SPI_XFER_END && !dout && !din) 505 return 0; 506 507 if (type & SPI_XFER_BEGIN) 508 memset(trans, '\0', sizeof(*trans)); 509 510 /* Dp we need to come back later to finish it? */ 511 if (dout && type == SPI_XFER_BEGIN) { 512 if (bytes > ICH_MAX_CMD_LEN) { 513 debug("ICH SPI: Command length limit exceeded\n"); 514 return -1; 515 } 516 memcpy(trans->cmd, dout, bytes); 517 trans->cmd_len = bytes; 518 debug("ICH SPI: Saved %d bytes\n", bytes); 519 return 0; 520 } 521 522 /* 523 * We process a 'middle' spi_xfer() call, which has no 524 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 525 * an end. We therefore repeat the command. This is because ICH 526 * seems to have no support for this, or because interest (in digging 527 * out the details and creating a special case in the code) is low. 528 */ 529 if (trans->cmd_len) { 530 trans->out = trans->cmd; 531 trans->bytesout = trans->cmd_len; 532 using_cmd = 1; 533 debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 534 } else { 535 trans->out = dout; 536 trans->bytesout = dout ? bytes : 0; 537 } 538 539 trans->in = din; 540 trans->bytesin = din ? bytes : 0; 541 542 /* There has to always at least be an opcode. */ 543 if (!trans->bytesout) { 544 debug("ICH SPI: No opcode for transfer\n"); 545 return -1; 546 } 547 548 if (ich_status_poll(SPIS_SCIP, 0) == -1) 549 return -1; 550 551 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); 552 553 spi_setup_type(trans, using_cmd ? bytes : 0); 554 opcode_index = spi_setup_opcode(trans); 555 if (opcode_index < 0) 556 return -1; 557 with_address = spi_setup_offset(trans); 558 if (with_address < 0) 559 return -1; 560 561 if (trans->opcode == SPI_OPCODE_WREN) { 562 /* 563 * Treat Write Enable as Atomic Pre-Op if possible 564 * in order to prevent the Management Engine from 565 * issuing a transaction between WREN and DATA. 566 */ 567 if (!ctlr.ichspi_lock) 568 ich_writew(trans->opcode, ctlr.preop); 569 return 0; 570 } 571 572 if (ctlr.speed && ctlr.max_speed >= 33000000) { 573 int byte; 574 575 byte = ich_readb(ctlr.speed); 576 if (ich->speed >= 33000000) 577 byte |= SSFC_SCF_33MHZ; 578 else 579 byte &= ~SSFC_SCF_33MHZ; 580 ich_writeb(byte, ctlr.speed); 581 } 582 583 /* See if we have used up the command data */ 584 if (using_cmd && dout && bytes) { 585 trans->out = dout; 586 trans->bytesout = bytes; 587 debug("ICH SPI: Moving to data, %d bytes\n", bytes); 588 } 589 590 /* Preset control fields */ 591 control = ich_readw(ctlr.control); 592 control &= ~SSFC_RESERVED; 593 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 594 595 /* Issue atomic preop cycle if needed */ 596 if (ich_readw(ctlr.preop)) 597 control |= SPIC_ACS; 598 599 if (!trans->bytesout && !trans->bytesin) { 600 /* SPI addresses are 24 bit only */ 601 if (with_address) 602 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 603 604 /* 605 * This is a 'no data' command (like Write Enable), its 606 * bitesout size was 1, decremented to zero while executing 607 * spi_setup_opcode() above. Tell the chip to send the 608 * command. 609 */ 610 ich_writew(control, ctlr.control); 611 612 /* wait for the result */ 613 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 614 if (status == -1) 615 return -1; 616 617 if (status & SPIS_FCERR) { 618 debug("ICH SPI: Command transaction error\n"); 619 return -1; 620 } 621 622 return 0; 623 } 624 625 /* 626 * Check if this is a write command atempting to transfer more bytes 627 * than the controller can handle. Iterations for writes are not 628 * supported here because each SPI write command needs to be preceded 629 * and followed by other SPI commands, and this sequence is controlled 630 * by the SPI chip driver. 631 */ 632 if (trans->bytesout > ctlr.databytes) { 633 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 634 return -1; 635 } 636 637 /* 638 * Read or write up to databytes bytes at a time until everything has 639 * been sent. 640 */ 641 while (trans->bytesout || trans->bytesin) { 642 uint32_t data_length; 643 644 /* SPI addresses are 24 bit only */ 645 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 646 647 if (trans->bytesout) 648 data_length = min(trans->bytesout, ctlr.databytes); 649 else 650 data_length = min(trans->bytesin, ctlr.databytes); 651 652 /* Program data into FDATA0 to N */ 653 if (trans->bytesout) { 654 write_reg(trans->out, ctlr.data, data_length); 655 spi_use_out(trans, data_length); 656 if (with_address) 657 trans->offset += data_length; 658 } 659 660 /* Add proper control fields' values */ 661 control &= ~((ctlr.databytes - 1) << 8); 662 control |= SPIC_DS; 663 control |= (data_length - 1) << 8; 664 665 /* write it */ 666 ich_writew(control, ctlr.control); 667 668 /* Wait for Cycle Done Status or Flash Cycle Error. */ 669 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 670 if (status == -1) 671 return -1; 672 673 if (status & SPIS_FCERR) { 674 debug("ICH SPI: Data transaction error\n"); 675 return -1; 676 } 677 678 if (trans->bytesin) { 679 read_reg(ctlr.data, trans->in, data_length); 680 spi_use_in(trans, data_length); 681 if (with_address) 682 trans->offset += data_length; 683 } 684 } 685 686 /* Clear atomic preop now that xfer is done */ 687 ich_writew(0, ctlr.preop); 688 689 return 0; 690 } 691 692 693 /* 694 * This uses the SPI controller from the Intel Cougar Point and Panther Point 695 * PCH to write-protect portions of the SPI flash until reboot. The changes 696 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 697 * done elsewhere. 698 */ 699 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) 700 { 701 uint32_t tmplong; 702 uint32_t upper_limit; 703 704 if (!ctlr.pr) { 705 printf("%s: operation not supported on this chipset\n", 706 __func__); 707 return -1; 708 } 709 710 if (length == 0 || 711 lower_limit > (0xFFFFFFFFUL - length) + 1 || 712 hint < 0 || hint > 4) { 713 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 714 lower_limit, length, hint); 715 return -1; 716 } 717 718 upper_limit = lower_limit + length - 1; 719 720 /* 721 * Determine bits to write, as follows: 722 * 31 Write-protection enable (includes erase operation) 723 * 30:29 reserved 724 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 725 * 15 Read-protection enable 726 * 14:13 reserved 727 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 728 */ 729 tmplong = 0x80000000 | 730 ((upper_limit & 0x01fff000) << 4) | 731 ((lower_limit & 0x01fff000) >> 12); 732 733 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 734 &ctlr.pr[hint]); 735 ctlr.pr[hint] = tmplong; 736 737 return 0; 738 } 739