1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but without any warranty; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 * This file is derived from the flashrom project. 20 */ 21 22 #include <common.h> 23 #include <malloc.h> 24 #include <spi.h> 25 #include <pci.h> 26 #include <pci_ids.h> 27 #include <asm/io.h> 28 29 #include "ich.h" 30 31 #define SPI_OPCODE_WREN 0x06 32 #define SPI_OPCODE_FAST_READ 0x0b 33 34 struct ich_ctlr { 35 pci_dev_t dev; /* PCI device number */ 36 int ich_version; /* Controller version, 7 or 9 */ 37 int ichspi_lock; 38 int locked; 39 uint8_t *opmenu; 40 int menubytes; 41 void *base; /* Base of register set */ 42 uint16_t *preop; 43 uint16_t *optype; 44 uint32_t *addr; 45 uint8_t *data; 46 unsigned databytes; 47 uint8_t *status; 48 uint16_t *control; 49 uint32_t *bbar; 50 uint32_t *pr; /* only for ich9 */ 51 uint8_t *speed; /* pointer to speed control */ 52 ulong max_speed; /* Maximum bus speed in MHz */ 53 }; 54 55 struct ich_ctlr ctlr; 56 57 static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) 58 { 59 return container_of(slave, struct ich_spi_slave, slave); 60 } 61 62 static unsigned int ich_reg(const void *addr) 63 { 64 return (unsigned)(addr - ctlr.base) & 0xffff; 65 } 66 67 static u8 ich_readb(const void *addr) 68 { 69 u8 value = readb(addr); 70 71 debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); 72 73 return value; 74 } 75 76 static u16 ich_readw(const void *addr) 77 { 78 u16 value = readw(addr); 79 80 debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); 81 82 return value; 83 } 84 85 static u32 ich_readl(const void *addr) 86 { 87 u32 value = readl(addr); 88 89 debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); 90 91 return value; 92 } 93 94 static void ich_writeb(u8 value, void *addr) 95 { 96 writeb(value, addr); 97 debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); 98 } 99 100 static void ich_writew(u16 value, void *addr) 101 { 102 writew(value, addr); 103 debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); 104 } 105 106 static void ich_writel(u32 value, void *addr) 107 { 108 writel(value, addr); 109 debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); 110 } 111 112 static void write_reg(const void *value, void *dest, uint32_t size) 113 { 114 memcpy_toio(dest, value, size); 115 } 116 117 static void read_reg(const void *src, void *value, uint32_t size) 118 { 119 memcpy_fromio(value, src, size); 120 } 121 122 static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) 123 { 124 const uint32_t bbar_mask = 0x00ffff00; 125 uint32_t ichspi_bbar; 126 127 minaddr &= bbar_mask; 128 ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; 129 ichspi_bbar |= minaddr; 130 ich_writel(ichspi_bbar, ctlr->bbar); 131 } 132 133 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 134 { 135 puts("spi_cs_is_valid used but not implemented\n"); 136 return 0; 137 } 138 139 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 140 unsigned int max_hz, unsigned int mode) 141 { 142 struct ich_spi_slave *ich; 143 144 ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); 145 if (!ich) { 146 puts("ICH SPI: Out of memory\n"); 147 return NULL; 148 } 149 150 /* 151 * Yes this controller can only write a small number of bytes at 152 * once! The limit is typically 64 bytes. 153 */ 154 ich->slave.max_write_size = ctlr.databytes; 155 ich->speed = max_hz; 156 157 return &ich->slave; 158 } 159 160 void spi_free_slave(struct spi_slave *slave) 161 { 162 struct ich_spi_slave *ich = to_ich_spi(slave); 163 164 free(ich); 165 } 166 167 /* 168 * Check if this device ID matches one of supported Intel PCH devices. 169 * 170 * Return the ICH version if there is a match, or zero otherwise. 171 */ 172 static int get_ich_version(uint16_t device_id) 173 { 174 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) 175 return 7; 176 177 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 178 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 179 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 180 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) 181 return 9; 182 183 return 0; 184 } 185 186 /* @return 1 if the SPI flash supports the 33MHz speed */ 187 static int ich9_can_do_33mhz(pci_dev_t dev) 188 { 189 u32 fdod, speed; 190 191 /* Observe SPI Descriptor Component Section 0 */ 192 pci_write_config_dword(dev, 0xb0, 0x1000); 193 194 /* Extract the Write/Erase SPI Frequency from descriptor */ 195 pci_read_config_dword(dev, 0xb4, &fdod); 196 197 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 198 speed = (fdod >> 21) & 7; 199 200 return speed == 1; 201 } 202 203 static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) 204 { 205 int last_bus = pci_last_busno(); 206 int bus; 207 208 if (last_bus == -1) { 209 debug("No PCI busses?\n"); 210 return -1; 211 } 212 213 for (bus = 0; bus <= last_bus; bus++) { 214 uint16_t vendor_id, device_id; 215 uint32_t ids; 216 pci_dev_t dev; 217 218 dev = PCI_BDF(bus, 31, 0); 219 pci_read_config_dword(dev, 0, &ids); 220 vendor_id = ids; 221 device_id = ids >> 16; 222 223 if (vendor_id == PCI_VENDOR_ID_INTEL) { 224 *devp = dev; 225 *ich_versionp = get_ich_version(device_id); 226 return 0; 227 } 228 } 229 230 debug("ICH SPI: No ICH found.\n"); 231 return -1; 232 } 233 234 static int ich_init_controller(struct ich_ctlr *ctlr) 235 { 236 uint8_t *rcrb; /* Root Complex Register Block */ 237 uint32_t rcba; /* Root Complex Base Address */ 238 239 pci_read_config_dword(ctlr->dev, 0xf0, &rcba); 240 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 241 rcrb = (uint8_t *)(rcba & 0xffffc000); 242 if (ctlr->ich_version == 7) { 243 struct ich7_spi_regs *ich7_spi; 244 245 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 246 ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; 247 ctlr->opmenu = ich7_spi->opmenu; 248 ctlr->menubytes = sizeof(ich7_spi->opmenu); 249 ctlr->optype = &ich7_spi->optype; 250 ctlr->addr = &ich7_spi->spia; 251 ctlr->data = (uint8_t *)ich7_spi->spid; 252 ctlr->databytes = sizeof(ich7_spi->spid); 253 ctlr->status = (uint8_t *)&ich7_spi->spis; 254 ctlr->control = &ich7_spi->spic; 255 ctlr->bbar = &ich7_spi->bbar; 256 ctlr->preop = &ich7_spi->preop; 257 ctlr->base = ich7_spi; 258 } else if (ctlr->ich_version == 9) { 259 struct ich9_spi_regs *ich9_spi; 260 261 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 262 ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 263 ctlr->opmenu = ich9_spi->opmenu; 264 ctlr->menubytes = sizeof(ich9_spi->opmenu); 265 ctlr->optype = &ich9_spi->optype; 266 ctlr->addr = &ich9_spi->faddr; 267 ctlr->data = (uint8_t *)ich9_spi->fdata; 268 ctlr->databytes = sizeof(ich9_spi->fdata); 269 ctlr->status = &ich9_spi->ssfs; 270 ctlr->control = (uint16_t *)ich9_spi->ssfc; 271 ctlr->speed = ich9_spi->ssfc + 2; 272 ctlr->bbar = &ich9_spi->bbar; 273 ctlr->preop = &ich9_spi->preop; 274 ctlr->pr = &ich9_spi->pr[0]; 275 ctlr->base = ich9_spi; 276 } else { 277 debug("ICH SPI: Unrecognized ICH version %d.\n", 278 ctlr->ich_version); 279 return -1; 280 } 281 debug("ICH SPI: Version %d detected\n", ctlr->ich_version); 282 283 /* Work out the maximum speed we can support */ 284 ctlr->max_speed = 20000000; 285 if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) 286 ctlr->max_speed = 33000000; 287 288 ich_set_bbar(ctlr, 0); 289 290 return 0; 291 } 292 293 void spi_init(void) 294 { 295 uint8_t bios_cntl; 296 297 if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { 298 printf("ICH SPI: Cannot find device\n"); 299 return; 300 } 301 302 if (ich_init_controller(&ctlr)) { 303 printf("ICH SPI: Cannot setup controller\n"); 304 return; 305 } 306 307 /* 308 * Disable the BIOS write protect so write commands are allowed. On 309 * v9, deassert SMM BIOS Write Protect Disable. 310 */ 311 pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); 312 if (ctlr.ich_version == 9) 313 bios_cntl &= ~(1 << 5); 314 pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); 315 } 316 317 int spi_claim_bus(struct spi_slave *slave) 318 { 319 /* Handled by ICH automatically. */ 320 return 0; 321 } 322 323 void spi_release_bus(struct spi_slave *slave) 324 { 325 /* Handled by ICH automatically. */ 326 } 327 328 void spi_cs_activate(struct spi_slave *slave) 329 { 330 /* Handled by ICH automatically. */ 331 } 332 333 void spi_cs_deactivate(struct spi_slave *slave) 334 { 335 /* Handled by ICH automatically. */ 336 } 337 338 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 339 { 340 trans->out += bytes; 341 trans->bytesout -= bytes; 342 } 343 344 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 345 { 346 trans->in += bytes; 347 trans->bytesin -= bytes; 348 } 349 350 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 351 { 352 trans->type = 0xFF; 353 354 /* Try to guess spi type from read/write sizes. */ 355 if (trans->bytesin == 0) { 356 if (trans->bytesout + data_bytes > 4) 357 /* 358 * If bytesin = 0 and bytesout > 4, we presume this is 359 * a write data operation, which is accompanied by an 360 * address. 361 */ 362 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 363 else 364 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 365 return; 366 } 367 368 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 369 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 370 return; 371 } 372 373 if (trans->bytesout == 4) /* and bytesin is > 0 */ 374 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 375 376 /* Fast read command is called with 5 bytes instead of 4 */ 377 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 378 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 379 --trans->bytesout; 380 } 381 } 382 383 static int spi_setup_opcode(struct spi_trans *trans) 384 { 385 uint16_t optypes; 386 uint8_t opmenu[ctlr.menubytes]; 387 388 trans->opcode = trans->out[0]; 389 spi_use_out(trans, 1); 390 if (!ctlr.ichspi_lock) { 391 /* The lock is off, so just use index 0. */ 392 ich_writeb(trans->opcode, ctlr.opmenu); 393 optypes = ich_readw(ctlr.optype); 394 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 395 ich_writew(optypes, ctlr.optype); 396 return 0; 397 } else { 398 /* The lock is on. See if what we need is on the menu. */ 399 uint8_t optype; 400 uint16_t opcode_index; 401 402 /* Write Enable is handled as atomic prefix */ 403 if (trans->opcode == SPI_OPCODE_WREN) 404 return 0; 405 406 read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); 407 for (opcode_index = 0; opcode_index < ctlr.menubytes; 408 opcode_index++) { 409 if (opmenu[opcode_index] == trans->opcode) 410 break; 411 } 412 413 if (opcode_index == ctlr.menubytes) { 414 printf("ICH SPI: Opcode %x not found\n", 415 trans->opcode); 416 return -1; 417 } 418 419 optypes = ich_readw(ctlr.optype); 420 optype = (optypes >> (opcode_index * 2)) & 0x3; 421 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 422 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 423 trans->bytesout >= 3) { 424 /* We guessed wrong earlier. Fix it up. */ 425 trans->type = optype; 426 } 427 if (optype != trans->type) { 428 printf("ICH SPI: Transaction doesn't fit type %d\n", 429 optype); 430 return -1; 431 } 432 return opcode_index; 433 } 434 } 435 436 static int spi_setup_offset(struct spi_trans *trans) 437 { 438 /* Separate the SPI address and data. */ 439 switch (trans->type) { 440 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 441 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 442 return 0; 443 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 444 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 445 trans->offset = ((uint32_t)trans->out[0] << 16) | 446 ((uint32_t)trans->out[1] << 8) | 447 ((uint32_t)trans->out[2] << 0); 448 spi_use_out(trans, 3); 449 return 1; 450 default: 451 printf("Unrecognized SPI transaction type %#x\n", trans->type); 452 return -1; 453 } 454 } 455 456 /* 457 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 458 * below is true) or 0. In case the wait was for the bit(s) to set - write 459 * those bits back, which would cause resetting them. 460 * 461 * Return the last read status value on success or -1 on failure. 462 */ 463 static int ich_status_poll(u16 bitmask, int wait_til_set) 464 { 465 int timeout = 600000; /* This will result in 6s */ 466 u16 status = 0; 467 468 while (timeout--) { 469 status = ich_readw(ctlr.status); 470 if (wait_til_set ^ ((status & bitmask) == 0)) { 471 if (wait_til_set) 472 ich_writew((status & bitmask), ctlr.status); 473 return status; 474 } 475 udelay(10); 476 } 477 478 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 479 status, bitmask); 480 return -1; 481 } 482 483 /* 484 int spi_xfer(struct spi_slave *slave, const void *dout, 485 unsigned int bitsout, void *din, unsigned int bitsin) 486 */ 487 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 488 void *din, unsigned long flags) 489 { 490 struct ich_spi_slave *ich = to_ich_spi(slave); 491 uint16_t control; 492 int16_t opcode_index; 493 int with_address; 494 int status; 495 int bytes = bitlen / 8; 496 struct spi_trans *trans = &ich->trans; 497 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 498 int using_cmd = 0; 499 /* Align read transactions to 64-byte boundaries */ 500 char buff[ctlr.databytes]; 501 502 /* Ee don't support writing partial bytes. */ 503 if (bitlen % 8) { 504 debug("ICH SPI: Accessing partial bytes not supported\n"); 505 return -1; 506 } 507 508 /* An empty end transaction can be ignored */ 509 if (type == SPI_XFER_END && !dout && !din) 510 return 0; 511 512 if (type & SPI_XFER_BEGIN) 513 memset(trans, '\0', sizeof(*trans)); 514 515 /* Dp we need to come back later to finish it? */ 516 if (dout && type == SPI_XFER_BEGIN) { 517 if (bytes > ICH_MAX_CMD_LEN) { 518 debug("ICH SPI: Command length limit exceeded\n"); 519 return -1; 520 } 521 memcpy(trans->cmd, dout, bytes); 522 trans->cmd_len = bytes; 523 debug("ICH SPI: Saved %d bytes\n", bytes); 524 return 0; 525 } 526 527 /* 528 * We process a 'middle' spi_xfer() call, which has no 529 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 530 * an end. We therefore repeat the command. This is because ICH 531 * seems to have no support for this, or because interest (in digging 532 * out the details and creating a special case in the code) is low. 533 */ 534 if (trans->cmd_len) { 535 trans->out = trans->cmd; 536 trans->bytesout = trans->cmd_len; 537 using_cmd = 1; 538 debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 539 } else { 540 trans->out = dout; 541 trans->bytesout = dout ? bytes : 0; 542 } 543 544 trans->in = din; 545 trans->bytesin = din ? bytes : 0; 546 547 /* There has to always at least be an opcode. */ 548 if (!trans->bytesout) { 549 debug("ICH SPI: No opcode for transfer\n"); 550 return -1; 551 } 552 553 if (ich_status_poll(SPIS_SCIP, 0) == -1) 554 return -1; 555 556 ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); 557 558 spi_setup_type(trans, using_cmd ? bytes : 0); 559 opcode_index = spi_setup_opcode(trans); 560 if (opcode_index < 0) 561 return -1; 562 with_address = spi_setup_offset(trans); 563 if (with_address < 0) 564 return -1; 565 566 if (trans->opcode == SPI_OPCODE_WREN) { 567 /* 568 * Treat Write Enable as Atomic Pre-Op if possible 569 * in order to prevent the Management Engine from 570 * issuing a transaction between WREN and DATA. 571 */ 572 if (!ctlr.ichspi_lock) 573 ich_writew(trans->opcode, ctlr.preop); 574 return 0; 575 } 576 577 if (ctlr.speed && ctlr.max_speed >= 33000000) { 578 int byte; 579 580 byte = ich_readb(ctlr.speed); 581 if (ich->speed >= 33000000) 582 byte |= SSFC_SCF_33MHZ; 583 else 584 byte &= ~SSFC_SCF_33MHZ; 585 ich_writeb(byte, ctlr.speed); 586 } 587 588 /* See if we have used up the command data */ 589 if (using_cmd && dout && bytes) { 590 trans->out = dout; 591 trans->bytesout = bytes; 592 debug("ICH SPI: Moving to data, %d bytes\n", bytes); 593 } 594 595 /* Preset control fields */ 596 control = ich_readw(ctlr.control); 597 control &= ~SSFC_RESERVED; 598 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 599 600 /* Issue atomic preop cycle if needed */ 601 if (ich_readw(ctlr.preop)) 602 control |= SPIC_ACS; 603 604 if (!trans->bytesout && !trans->bytesin) { 605 /* SPI addresses are 24 bit only */ 606 if (with_address) 607 ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); 608 609 /* 610 * This is a 'no data' command (like Write Enable), its 611 * bitesout size was 1, decremented to zero while executing 612 * spi_setup_opcode() above. Tell the chip to send the 613 * command. 614 */ 615 ich_writew(control, ctlr.control); 616 617 /* wait for the result */ 618 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 619 if (status == -1) 620 return -1; 621 622 if (status & SPIS_FCERR) { 623 debug("ICH SPI: Command transaction error\n"); 624 return -1; 625 } 626 627 return 0; 628 } 629 630 /* 631 * Check if this is a write command atempting to transfer more bytes 632 * than the controller can handle. Iterations for writes are not 633 * supported here because each SPI write command needs to be preceded 634 * and followed by other SPI commands, and this sequence is controlled 635 * by the SPI chip driver. 636 */ 637 if (trans->bytesout > ctlr.databytes) { 638 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 639 return -1; 640 } 641 642 /* 643 * Read or write up to databytes bytes at a time until everything has 644 * been sent. 645 */ 646 while (trans->bytesout || trans->bytesin) { 647 uint32_t data_length; 648 uint32_t aligned_offset; 649 uint32_t diff; 650 651 aligned_offset = trans->offset & ~(ctlr.databytes - 1); 652 diff = trans->offset - aligned_offset; 653 654 /* SPI addresses are 24 bit only */ 655 ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr); 656 657 if (trans->bytesout) 658 data_length = min(trans->bytesout, ctlr.databytes); 659 else 660 data_length = min(trans->bytesin, ctlr.databytes); 661 662 /* Program data into FDATA0 to N */ 663 if (trans->bytesout) { 664 write_reg(trans->out, ctlr.data, data_length); 665 spi_use_out(trans, data_length); 666 if (with_address) 667 trans->offset += data_length; 668 } 669 670 /* Add proper control fields' values */ 671 control &= ~((ctlr.databytes - 1) << 8); 672 control |= SPIC_DS; 673 control |= (data_length - 1) << 8; 674 675 /* write it */ 676 ich_writew(control, ctlr.control); 677 678 /* Wait for Cycle Done Status or Flash Cycle Error. */ 679 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); 680 if (status == -1) 681 return -1; 682 683 if (status & SPIS_FCERR) { 684 debug("ICH SPI: Data transaction error\n"); 685 return -1; 686 } 687 688 if (trans->bytesin) { 689 if (diff) { 690 data_length -= diff; 691 read_reg(ctlr.data, buff, ctlr.databytes); 692 memcpy(trans->in, buff + diff, data_length); 693 } else { 694 read_reg(ctlr.data, trans->in, data_length); 695 } 696 spi_use_in(trans, data_length); 697 if (with_address) 698 trans->offset += data_length; 699 } 700 } 701 702 /* Clear atomic preop now that xfer is done */ 703 ich_writew(0, ctlr.preop); 704 705 return 0; 706 } 707 708 709 /* 710 * This uses the SPI controller from the Intel Cougar Point and Panther Point 711 * PCH to write-protect portions of the SPI flash until reboot. The changes 712 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 713 * done elsewhere. 714 */ 715 int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) 716 { 717 uint32_t tmplong; 718 uint32_t upper_limit; 719 720 if (!ctlr.pr) { 721 printf("%s: operation not supported on this chipset\n", 722 __func__); 723 return -1; 724 } 725 726 if (length == 0 || 727 lower_limit > (0xFFFFFFFFUL - length) + 1 || 728 hint < 0 || hint > 4) { 729 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 730 lower_limit, length, hint); 731 return -1; 732 } 733 734 upper_limit = lower_limit + length - 1; 735 736 /* 737 * Determine bits to write, as follows: 738 * 31 Write-protection enable (includes erase operation) 739 * 30:29 reserved 740 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 741 * 15 Read-protection enable 742 * 14:13 reserved 743 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 744 */ 745 tmplong = 0x80000000 | 746 ((upper_limit & 0x01fff000) << 4) | 747 ((lower_limit & 0x01fff000) >> 12); 748 749 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 750 &ctlr.pr[hint]); 751 ctlr.pr[hint] = tmplong; 752 753 return 0; 754 } 755