1 /* 2 * Copyright (c) 2011-12 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * This file is derived from the flashrom project. 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <malloc.h> 13 #include <pch.h> 14 #include <pci.h> 15 #include <pci_ids.h> 16 #include <spi.h> 17 #include <asm/io.h> 18 19 #include "ich.h" 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #ifdef DEBUG_TRACE 24 #define debug_trace(fmt, args...) debug(fmt, ##args) 25 #else 26 #define debug_trace(x, args...) 27 #endif 28 29 static u8 ich_readb(struct ich_spi_priv *priv, int reg) 30 { 31 u8 value = readb(priv->base + reg); 32 33 debug_trace("read %2.2x from %4.4x\n", value, reg); 34 35 return value; 36 } 37 38 static u16 ich_readw(struct ich_spi_priv *priv, int reg) 39 { 40 u16 value = readw(priv->base + reg); 41 42 debug_trace("read %4.4x from %4.4x\n", value, reg); 43 44 return value; 45 } 46 47 static u32 ich_readl(struct ich_spi_priv *priv, int reg) 48 { 49 u32 value = readl(priv->base + reg); 50 51 debug_trace("read %8.8x from %4.4x\n", value, reg); 52 53 return value; 54 } 55 56 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) 57 { 58 writeb(value, priv->base + reg); 59 debug_trace("wrote %2.2x to %4.4x\n", value, reg); 60 } 61 62 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) 63 { 64 writew(value, priv->base + reg); 65 debug_trace("wrote %4.4x to %4.4x\n", value, reg); 66 } 67 68 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) 69 { 70 writel(value, priv->base + reg); 71 debug_trace("wrote %8.8x to %4.4x\n", value, reg); 72 } 73 74 static void write_reg(struct ich_spi_priv *priv, const void *value, 75 int dest_reg, uint32_t size) 76 { 77 memcpy_toio(priv->base + dest_reg, value, size); 78 } 79 80 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, 81 uint32_t size) 82 { 83 memcpy_fromio(value, priv->base + src_reg, size); 84 } 85 86 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) 87 { 88 const uint32_t bbar_mask = 0x00ffff00; 89 uint32_t ichspi_bbar; 90 91 minaddr &= bbar_mask; 92 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; 93 ichspi_bbar |= minaddr; 94 ich_writel(ctlr, ichspi_bbar, ctlr->bbar); 95 } 96 97 /* @return 1 if the SPI flash supports the 33MHz speed */ 98 static int ich9_can_do_33mhz(struct udevice *dev) 99 { 100 u32 fdod, speed; 101 102 /* Observe SPI Descriptor Component Section 0 */ 103 dm_pci_write_config32(dev->parent, 0xb0, 0x1000); 104 105 /* Extract the Write/Erase SPI Frequency from descriptor */ 106 dm_pci_read_config32(dev->parent, 0xb4, &fdod); 107 108 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 109 speed = (fdod >> 21) & 7; 110 111 return speed == 1; 112 } 113 114 static int ich_init_controller(struct udevice *dev, 115 struct ich_spi_platdata *plat, 116 struct ich_spi_priv *ctlr) 117 { 118 ulong sbase_addr; 119 void *sbase; 120 121 /* SBASE is similar */ 122 pch_get_spi_base(dev->parent, &sbase_addr); 123 sbase = (void *)sbase_addr; 124 debug("%s: sbase=%p\n", __func__, sbase); 125 126 if (plat->ich_version == ICHV_7) { 127 struct ich7_spi_regs *ich7_spi = sbase; 128 129 ich7_spi = (struct ich7_spi_regs *)sbase; 130 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; 131 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); 132 ctlr->menubytes = sizeof(ich7_spi->opmenu); 133 ctlr->optype = offsetof(struct ich7_spi_regs, optype); 134 ctlr->addr = offsetof(struct ich7_spi_regs, spia); 135 ctlr->data = offsetof(struct ich7_spi_regs, spid); 136 ctlr->databytes = sizeof(ich7_spi->spid); 137 ctlr->status = offsetof(struct ich7_spi_regs, spis); 138 ctlr->control = offsetof(struct ich7_spi_regs, spic); 139 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); 140 ctlr->preop = offsetof(struct ich7_spi_regs, preop); 141 ctlr->base = ich7_spi; 142 } else if (plat->ich_version == ICHV_9) { 143 struct ich9_spi_regs *ich9_spi = sbase; 144 145 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 146 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); 147 ctlr->menubytes = sizeof(ich9_spi->opmenu); 148 ctlr->optype = offsetof(struct ich9_spi_regs, optype); 149 ctlr->addr = offsetof(struct ich9_spi_regs, faddr); 150 ctlr->data = offsetof(struct ich9_spi_regs, fdata); 151 ctlr->databytes = sizeof(ich9_spi->fdata); 152 ctlr->status = offsetof(struct ich9_spi_regs, ssfs); 153 ctlr->control = offsetof(struct ich9_spi_regs, ssfc); 154 ctlr->speed = ctlr->control + 2; 155 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); 156 ctlr->preop = offsetof(struct ich9_spi_regs, preop); 157 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); 158 ctlr->pr = &ich9_spi->pr[0]; 159 ctlr->base = ich9_spi; 160 } else { 161 debug("ICH SPI: Unrecognised ICH version %d\n", 162 plat->ich_version); 163 return -EINVAL; 164 } 165 166 /* Work out the maximum speed we can support */ 167 ctlr->max_speed = 20000000; 168 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) 169 ctlr->max_speed = 33000000; 170 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", 171 plat->ich_version, ctlr->base, ctlr->max_speed); 172 173 ich_set_bbar(ctlr, 0); 174 175 return 0; 176 } 177 178 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 179 { 180 trans->out += bytes; 181 trans->bytesout -= bytes; 182 } 183 184 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 185 { 186 trans->in += bytes; 187 trans->bytesin -= bytes; 188 } 189 190 static void spi_setup_type(struct spi_trans *trans, int data_bytes) 191 { 192 trans->type = 0xFF; 193 194 /* Try to guess spi type from read/write sizes */ 195 if (trans->bytesin == 0) { 196 if (trans->bytesout + data_bytes > 4) 197 /* 198 * If bytesin = 0 and bytesout > 4, we presume this is 199 * a write data operation, which is accompanied by an 200 * address. 201 */ 202 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 203 else 204 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 205 return; 206 } 207 208 if (trans->bytesout == 1) { /* and bytesin is > 0 */ 209 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 210 return; 211 } 212 213 if (trans->bytesout == 4) /* and bytesin is > 0 */ 214 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 215 216 /* Fast read command is called with 5 bytes instead of 4 */ 217 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 218 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 219 --trans->bytesout; 220 } 221 } 222 223 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) 224 { 225 uint16_t optypes; 226 uint8_t opmenu[ctlr->menubytes]; 227 228 trans->opcode = trans->out[0]; 229 spi_use_out(trans, 1); 230 if (!ctlr->ichspi_lock) { 231 /* The lock is off, so just use index 0. */ 232 ich_writeb(ctlr, trans->opcode, ctlr->opmenu); 233 optypes = ich_readw(ctlr, ctlr->optype); 234 optypes = (optypes & 0xfffc) | (trans->type & 0x3); 235 ich_writew(ctlr, optypes, ctlr->optype); 236 return 0; 237 } else { 238 /* The lock is on. See if what we need is on the menu. */ 239 uint8_t optype; 240 uint16_t opcode_index; 241 242 /* Write Enable is handled as atomic prefix */ 243 if (trans->opcode == SPI_OPCODE_WREN) 244 return 0; 245 246 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); 247 for (opcode_index = 0; opcode_index < ctlr->menubytes; 248 opcode_index++) { 249 if (opmenu[opcode_index] == trans->opcode) 250 break; 251 } 252 253 if (opcode_index == ctlr->menubytes) { 254 printf("ICH SPI: Opcode %x not found\n", 255 trans->opcode); 256 return -EINVAL; 257 } 258 259 optypes = ich_readw(ctlr, ctlr->optype); 260 optype = (optypes >> (opcode_index * 2)) & 0x3; 261 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 262 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 263 trans->bytesout >= 3) { 264 /* We guessed wrong earlier. Fix it up. */ 265 trans->type = optype; 266 } 267 if (optype != trans->type) { 268 printf("ICH SPI: Transaction doesn't fit type %d\n", 269 optype); 270 return -ENOSPC; 271 } 272 return opcode_index; 273 } 274 } 275 276 static int spi_setup_offset(struct spi_trans *trans) 277 { 278 /* Separate the SPI address and data */ 279 switch (trans->type) { 280 case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 281 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 282 return 0; 283 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 284 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 285 trans->offset = ((uint32_t)trans->out[0] << 16) | 286 ((uint32_t)trans->out[1] << 8) | 287 ((uint32_t)trans->out[2] << 0); 288 spi_use_out(trans, 3); 289 return 1; 290 default: 291 printf("Unrecognized SPI transaction type %#x\n", trans->type); 292 return -EPROTO; 293 } 294 } 295 296 /* 297 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 298 * below is true) or 0. In case the wait was for the bit(s) to set - write 299 * those bits back, which would cause resetting them. 300 * 301 * Return the last read status value on success or -1 on failure. 302 */ 303 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, 304 int wait_til_set) 305 { 306 int timeout = 600000; /* This will result in 6s */ 307 u16 status = 0; 308 309 while (timeout--) { 310 status = ich_readw(ctlr, ctlr->status); 311 if (wait_til_set ^ ((status & bitmask) == 0)) { 312 if (wait_til_set) { 313 ich_writew(ctlr, status & bitmask, 314 ctlr->status); 315 } 316 return status; 317 } 318 udelay(10); 319 } 320 321 printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 322 status, bitmask); 323 return -ETIMEDOUT; 324 } 325 326 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, 327 const void *dout, void *din, unsigned long flags) 328 { 329 struct udevice *bus = dev_get_parent(dev); 330 struct ich_spi_platdata *plat = dev_get_platdata(bus); 331 struct ich_spi_priv *ctlr = dev_get_priv(bus); 332 uint16_t control; 333 int16_t opcode_index; 334 int with_address; 335 int status; 336 int bytes = bitlen / 8; 337 struct spi_trans *trans = &ctlr->trans; 338 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 339 int using_cmd = 0; 340 int ret; 341 342 /* We don't support writing partial bytes */ 343 if (bitlen % 8) { 344 debug("ICH SPI: Accessing partial bytes not supported\n"); 345 return -EPROTONOSUPPORT; 346 } 347 348 /* An empty end transaction can be ignored */ 349 if (type == SPI_XFER_END && !dout && !din) 350 return 0; 351 352 if (type & SPI_XFER_BEGIN) 353 memset(trans, '\0', sizeof(*trans)); 354 355 /* Dp we need to come back later to finish it? */ 356 if (dout && type == SPI_XFER_BEGIN) { 357 if (bytes > ICH_MAX_CMD_LEN) { 358 debug("ICH SPI: Command length limit exceeded\n"); 359 return -ENOSPC; 360 } 361 memcpy(trans->cmd, dout, bytes); 362 trans->cmd_len = bytes; 363 debug_trace("ICH SPI: Saved %d bytes\n", bytes); 364 return 0; 365 } 366 367 /* 368 * We process a 'middle' spi_xfer() call, which has no 369 * SPI_XFER_BEGIN/END, as an independent transaction as if it had 370 * an end. We therefore repeat the command. This is because ICH 371 * seems to have no support for this, or because interest (in digging 372 * out the details and creating a special case in the code) is low. 373 */ 374 if (trans->cmd_len) { 375 trans->out = trans->cmd; 376 trans->bytesout = trans->cmd_len; 377 using_cmd = 1; 378 debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); 379 } else { 380 trans->out = dout; 381 trans->bytesout = dout ? bytes : 0; 382 } 383 384 trans->in = din; 385 trans->bytesin = din ? bytes : 0; 386 387 /* There has to always at least be an opcode */ 388 if (!trans->bytesout) { 389 debug("ICH SPI: No opcode for transfer\n"); 390 return -EPROTO; 391 } 392 393 ret = ich_status_poll(ctlr, SPIS_SCIP, 0); 394 if (ret < 0) 395 return ret; 396 397 if (plat->ich_version == ICHV_7) 398 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 399 else 400 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 401 402 spi_setup_type(trans, using_cmd ? bytes : 0); 403 opcode_index = spi_setup_opcode(ctlr, trans); 404 if (opcode_index < 0) 405 return -EINVAL; 406 with_address = spi_setup_offset(trans); 407 if (with_address < 0) 408 return -EINVAL; 409 410 if (trans->opcode == SPI_OPCODE_WREN) { 411 /* 412 * Treat Write Enable as Atomic Pre-Op if possible 413 * in order to prevent the Management Engine from 414 * issuing a transaction between WREN and DATA. 415 */ 416 if (!ctlr->ichspi_lock) 417 ich_writew(ctlr, trans->opcode, ctlr->preop); 418 return 0; 419 } 420 421 if (ctlr->speed && ctlr->max_speed >= 33000000) { 422 int byte; 423 424 byte = ich_readb(ctlr, ctlr->speed); 425 if (ctlr->cur_speed >= 33000000) 426 byte |= SSFC_SCF_33MHZ; 427 else 428 byte &= ~SSFC_SCF_33MHZ; 429 ich_writeb(ctlr, byte, ctlr->speed); 430 } 431 432 /* See if we have used up the command data */ 433 if (using_cmd && dout && bytes) { 434 trans->out = dout; 435 trans->bytesout = bytes; 436 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); 437 } 438 439 /* Preset control fields */ 440 control = ich_readw(ctlr, ctlr->control); 441 control &= ~SSFC_RESERVED; 442 control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 443 444 /* Issue atomic preop cycle if needed */ 445 if (ich_readw(ctlr, ctlr->preop)) 446 control |= SPIC_ACS; 447 448 if (!trans->bytesout && !trans->bytesin) { 449 /* SPI addresses are 24 bit only */ 450 if (with_address) { 451 ich_writel(ctlr, trans->offset & 0x00FFFFFF, 452 ctlr->addr); 453 } 454 /* 455 * This is a 'no data' command (like Write Enable), its 456 * bitesout size was 1, decremented to zero while executing 457 * spi_setup_opcode() above. Tell the chip to send the 458 * command. 459 */ 460 ich_writew(ctlr, control, ctlr->control); 461 462 /* wait for the result */ 463 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 464 if (status < 0) 465 return status; 466 467 if (status & SPIS_FCERR) { 468 debug("ICH SPI: Command transaction error\n"); 469 return -EIO; 470 } 471 472 return 0; 473 } 474 475 /* 476 * Check if this is a write command atempting to transfer more bytes 477 * than the controller can handle. Iterations for writes are not 478 * supported here because each SPI write command needs to be preceded 479 * and followed by other SPI commands, and this sequence is controlled 480 * by the SPI chip driver. 481 */ 482 if (trans->bytesout > ctlr->databytes) { 483 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 484 return -EPROTO; 485 } 486 487 /* 488 * Read or write up to databytes bytes at a time until everything has 489 * been sent. 490 */ 491 while (trans->bytesout || trans->bytesin) { 492 uint32_t data_length; 493 494 /* SPI addresses are 24 bit only */ 495 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); 496 497 if (trans->bytesout) 498 data_length = min(trans->bytesout, ctlr->databytes); 499 else 500 data_length = min(trans->bytesin, ctlr->databytes); 501 502 /* Program data into FDATA0 to N */ 503 if (trans->bytesout) { 504 write_reg(ctlr, trans->out, ctlr->data, data_length); 505 spi_use_out(trans, data_length); 506 if (with_address) 507 trans->offset += data_length; 508 } 509 510 /* Add proper control fields' values */ 511 control &= ~((ctlr->databytes - 1) << 8); 512 control |= SPIC_DS; 513 control |= (data_length - 1) << 8; 514 515 /* write it */ 516 ich_writew(ctlr, control, ctlr->control); 517 518 /* Wait for Cycle Done Status or Flash Cycle Error */ 519 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 520 if (status < 0) 521 return status; 522 523 if (status & SPIS_FCERR) { 524 debug("ICH SPI: Data transaction error %x\n", status); 525 return -EIO; 526 } 527 528 if (trans->bytesin) { 529 read_reg(ctlr, ctlr->data, trans->in, data_length); 530 spi_use_in(trans, data_length); 531 if (with_address) 532 trans->offset += data_length; 533 } 534 } 535 536 /* Clear atomic preop now that xfer is done */ 537 ich_writew(ctlr, 0, ctlr->preop); 538 539 return 0; 540 } 541 542 /* 543 * This uses the SPI controller from the Intel Cougar Point and Panther Point 544 * PCH to write-protect portions of the SPI flash until reboot. The changes 545 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 546 * done elsewhere. 547 */ 548 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, 549 uint32_t length, int hint) 550 { 551 struct udevice *bus = dev->parent; 552 struct ich_spi_priv *ctlr = dev_get_priv(bus); 553 uint32_t tmplong; 554 uint32_t upper_limit; 555 556 if (!ctlr->pr) { 557 printf("%s: operation not supported on this chipset\n", 558 __func__); 559 return -ENOSYS; 560 } 561 562 if (length == 0 || 563 lower_limit > (0xFFFFFFFFUL - length) + 1 || 564 hint < 0 || hint > 4) { 565 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 566 lower_limit, length, hint); 567 return -EPERM; 568 } 569 570 upper_limit = lower_limit + length - 1; 571 572 /* 573 * Determine bits to write, as follows: 574 * 31 Write-protection enable (includes erase operation) 575 * 30:29 reserved 576 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 577 * 15 Read-protection enable 578 * 14:13 reserved 579 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 580 */ 581 tmplong = 0x80000000 | 582 ((upper_limit & 0x01fff000) << 4) | 583 ((lower_limit & 0x01fff000) >> 12); 584 585 printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 586 &ctlr->pr[hint]); 587 ctlr->pr[hint] = tmplong; 588 589 return 0; 590 } 591 592 static int ich_spi_probe(struct udevice *dev) 593 { 594 struct ich_spi_platdata *plat = dev_get_platdata(dev); 595 struct ich_spi_priv *priv = dev_get_priv(dev); 596 uint8_t bios_cntl; 597 int ret; 598 599 ret = ich_init_controller(dev, plat, priv); 600 if (ret) 601 return ret; 602 /* Disable the BIOS write protect so write commands are allowed */ 603 ret = pch_set_spi_protect(dev->parent, false); 604 if (ret == -ENOSYS) { 605 bios_cntl = ich_readb(priv, priv->bcr); 606 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ 607 bios_cntl |= 1; /* Write Protect Disable (WPD) */ 608 ich_writeb(priv, bios_cntl, priv->bcr); 609 } else if (ret) { 610 debug("%s: Failed to disable write-protect: err=%d\n", 611 __func__, ret); 612 return ret; 613 } 614 615 priv->cur_speed = priv->max_speed; 616 617 return 0; 618 } 619 620 static int ich_spi_set_speed(struct udevice *bus, uint speed) 621 { 622 struct ich_spi_priv *priv = dev_get_priv(bus); 623 624 priv->cur_speed = speed; 625 626 return 0; 627 } 628 629 static int ich_spi_set_mode(struct udevice *bus, uint mode) 630 { 631 debug("%s: mode=%d\n", __func__, mode); 632 633 return 0; 634 } 635 636 static int ich_spi_child_pre_probe(struct udevice *dev) 637 { 638 struct udevice *bus = dev_get_parent(dev); 639 struct ich_spi_platdata *plat = dev_get_platdata(bus); 640 struct ich_spi_priv *priv = dev_get_priv(bus); 641 struct spi_slave *slave = dev_get_parent_priv(dev); 642 643 /* 644 * Yes this controller can only write a small number of bytes at 645 * once! The limit is typically 64 bytes. 646 */ 647 slave->max_write_size = priv->databytes; 648 /* 649 * ICH 7 SPI controller only supports array read command 650 * and byte program command for SST flash 651 */ 652 if (plat->ich_version == ICHV_7) { 653 slave->mode_rx = SPI_RX_SLOW; 654 slave->mode = SPI_TX_BYTE; 655 } 656 657 return 0; 658 } 659 660 static int ich_spi_ofdata_to_platdata(struct udevice *dev) 661 { 662 struct ich_spi_platdata *plat = dev_get_platdata(dev); 663 int ret; 664 665 ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset, 666 "intel,ich7-spi"); 667 if (ret == 0) { 668 plat->ich_version = ICHV_7; 669 } else { 670 ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset, 671 "intel,ich9-spi"); 672 if (ret == 0) 673 plat->ich_version = ICHV_9; 674 } 675 676 return ret; 677 } 678 679 static const struct dm_spi_ops ich_spi_ops = { 680 .xfer = ich_spi_xfer, 681 .set_speed = ich_spi_set_speed, 682 .set_mode = ich_spi_set_mode, 683 /* 684 * cs_info is not needed, since we require all chip selects to be 685 * in the device tree explicitly 686 */ 687 }; 688 689 static const struct udevice_id ich_spi_ids[] = { 690 { .compatible = "intel,ich7-spi" }, 691 { .compatible = "intel,ich9-spi" }, 692 { } 693 }; 694 695 U_BOOT_DRIVER(ich_spi) = { 696 .name = "ich_spi", 697 .id = UCLASS_SPI, 698 .of_match = ich_spi_ids, 699 .ops = &ich_spi_ops, 700 .ofdata_to_platdata = ich_spi_ofdata_to_platdata, 701 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), 702 .priv_auto_alloc_size = sizeof(struct ich_spi_priv), 703 .child_pre_probe = ich_spi_child_pre_probe, 704 .probe = ich_spi_probe, 705 }; 706