11853030eSSimon Glass /* 21853030eSSimon Glass * Copyright (c) 2011-12 The Chromium OS Authors. 31853030eSSimon Glass * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 51853030eSSimon Glass * 61853030eSSimon Glass * This file is derived from the flashrom project. 71853030eSSimon Glass */ 81853030eSSimon Glass 91853030eSSimon Glass #include <common.h> 10ba457562SSimon Glass #include <dm.h> 115093badbSSimon Glass #include <errno.h> 121853030eSSimon Glass #include <malloc.h> 131853030eSSimon Glass #include <spi.h> 141853030eSSimon Glass #include <pci.h> 151853030eSSimon Glass #include <pci_ids.h> 161853030eSSimon Glass #include <asm/io.h> 171853030eSSimon Glass 181853030eSSimon Glass #include "ich.h" 191853030eSSimon Glass 201853030eSSimon Glass #define SPI_OPCODE_WREN 0x06 211853030eSSimon Glass #define SPI_OPCODE_FAST_READ 0x0b 221853030eSSimon Glass 23ba457562SSimon Glass struct ich_spi_platdata { 241853030eSSimon Glass pci_dev_t dev; /* PCI device number */ 251853030eSSimon Glass int ich_version; /* Controller version, 7 or 9 */ 265093badbSSimon Glass bool use_sbase; /* Use SBASE instead of RCB */ 271853030eSSimon Glass }; 281853030eSSimon Glass 29ba457562SSimon Glass struct ich_spi_priv { 30ba457562SSimon Glass int ichspi_lock; 31ba457562SSimon Glass int locked; 32ba457562SSimon Glass int opmenu; 33ba457562SSimon Glass int menubytes; 34ba457562SSimon Glass void *base; /* Base of register set */ 35ba457562SSimon Glass int preop; 36ba457562SSimon Glass int optype; 37ba457562SSimon Glass int addr; 38ba457562SSimon Glass int data; 39ba457562SSimon Glass unsigned databytes; 40ba457562SSimon Glass int status; 41ba457562SSimon Glass int control; 42ba457562SSimon Glass int bbar; 43ba457562SSimon Glass uint32_t *pr; /* only for ich9 */ 44ba457562SSimon Glass int speed; /* pointer to speed control */ 45ba457562SSimon Glass ulong max_speed; /* Maximum bus speed in MHz */ 46ba457562SSimon Glass ulong cur_speed; /* Current bus speed */ 47ba457562SSimon Glass struct spi_trans trans; /* current transaction in progress */ 48ba457562SSimon Glass }; 491853030eSSimon Glass 50ba457562SSimon Glass static u8 ich_readb(struct ich_spi_priv *priv, int reg) 511853030eSSimon Glass { 52ba457562SSimon Glass u8 value = readb(priv->base + reg); 531853030eSSimon Glass 54ba457562SSimon Glass debug("read %2.2x from %4.4x\n", value, reg); 551853030eSSimon Glass 561853030eSSimon Glass return value; 571853030eSSimon Glass } 581853030eSSimon Glass 59ba457562SSimon Glass static u16 ich_readw(struct ich_spi_priv *priv, int reg) 601853030eSSimon Glass { 61ba457562SSimon Glass u16 value = readw(priv->base + reg); 621853030eSSimon Glass 63ba457562SSimon Glass debug("read %4.4x from %4.4x\n", value, reg); 641853030eSSimon Glass 651853030eSSimon Glass return value; 661853030eSSimon Glass } 671853030eSSimon Glass 68ba457562SSimon Glass static u32 ich_readl(struct ich_spi_priv *priv, int reg) 691853030eSSimon Glass { 70ba457562SSimon Glass u32 value = readl(priv->base + reg); 711853030eSSimon Glass 72ba457562SSimon Glass debug("read %8.8x from %4.4x\n", value, reg); 731853030eSSimon Glass 741853030eSSimon Glass return value; 751853030eSSimon Glass } 761853030eSSimon Glass 77ba457562SSimon Glass static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) 781853030eSSimon Glass { 79ba457562SSimon Glass writeb(value, priv->base + reg); 80ba457562SSimon Glass debug("wrote %2.2x to %4.4x\n", value, reg); 811853030eSSimon Glass } 821853030eSSimon Glass 83ba457562SSimon Glass static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) 841853030eSSimon Glass { 85ba457562SSimon Glass writew(value, priv->base + reg); 86ba457562SSimon Glass debug("wrote %4.4x to %4.4x\n", value, reg); 871853030eSSimon Glass } 881853030eSSimon Glass 89ba457562SSimon Glass static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) 901853030eSSimon Glass { 91ba457562SSimon Glass writel(value, priv->base + reg); 92ba457562SSimon Glass debug("wrote %8.8x to %4.4x\n", value, reg); 931853030eSSimon Glass } 941853030eSSimon Glass 95ba457562SSimon Glass static void write_reg(struct ich_spi_priv *priv, const void *value, 96ba457562SSimon Glass int dest_reg, uint32_t size) 971853030eSSimon Glass { 98ba457562SSimon Glass memcpy_toio(priv->base + dest_reg, value, size); 991853030eSSimon Glass } 1001853030eSSimon Glass 101ba457562SSimon Glass static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, 102ba457562SSimon Glass uint32_t size) 1031853030eSSimon Glass { 104ba457562SSimon Glass memcpy_fromio(value, priv->base + src_reg, size); 1051853030eSSimon Glass } 1061853030eSSimon Glass 107ba457562SSimon Glass static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) 1081853030eSSimon Glass { 1091853030eSSimon Glass const uint32_t bbar_mask = 0x00ffff00; 1101853030eSSimon Glass uint32_t ichspi_bbar; 1111853030eSSimon Glass 1121853030eSSimon Glass minaddr &= bbar_mask; 113ba457562SSimon Glass ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; 1141853030eSSimon Glass ichspi_bbar |= minaddr; 115ba457562SSimon Glass ich_writel(ctlr, ichspi_bbar, ctlr->bbar); 1161853030eSSimon Glass } 1171853030eSSimon Glass 1181853030eSSimon Glass /* 1191853030eSSimon Glass * Check if this device ID matches one of supported Intel PCH devices. 1201853030eSSimon Glass * 1211853030eSSimon Glass * Return the ICH version if there is a match, or zero otherwise. 1221853030eSSimon Glass */ 1231853030eSSimon Glass static int get_ich_version(uint16_t device_id) 1241853030eSSimon Glass { 1257e774039SBin Meng if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || 126728b393fSBin Meng device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || 127728b393fSBin Meng device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) 1281853030eSSimon Glass return 7; 1291853030eSSimon Glass 1301853030eSSimon Glass if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 1311853030eSSimon Glass device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || 1321853030eSSimon Glass (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 1335093badbSSimon Glass device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || 13487108cf2SSimon Glass device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || 13587108cf2SSimon Glass device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC) 1361853030eSSimon Glass return 9; 1371853030eSSimon Glass 1381853030eSSimon Glass return 0; 1391853030eSSimon Glass } 1401853030eSSimon Glass 1411853030eSSimon Glass /* @return 1 if the SPI flash supports the 33MHz speed */ 1421853030eSSimon Glass static int ich9_can_do_33mhz(pci_dev_t dev) 1431853030eSSimon Glass { 1441853030eSSimon Glass u32 fdod, speed; 1451853030eSSimon Glass 1461853030eSSimon Glass /* Observe SPI Descriptor Component Section 0 */ 1471853030eSSimon Glass pci_write_config_dword(dev, 0xb0, 0x1000); 1481853030eSSimon Glass 1491853030eSSimon Glass /* Extract the Write/Erase SPI Frequency from descriptor */ 1501853030eSSimon Glass pci_read_config_dword(dev, 0xb4, &fdod); 1511853030eSSimon Glass 1521853030eSSimon Glass /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 1531853030eSSimon Glass speed = (fdod >> 21) & 7; 1541853030eSSimon Glass 1551853030eSSimon Glass return speed == 1; 1561853030eSSimon Glass } 1571853030eSSimon Glass 158ba457562SSimon Glass static int ich_find_spi_controller(struct ich_spi_platdata *ich) 1591853030eSSimon Glass { 1601853030eSSimon Glass int last_bus = pci_last_busno(); 1611853030eSSimon Glass int bus; 1621853030eSSimon Glass 1631853030eSSimon Glass if (last_bus == -1) { 1641853030eSSimon Glass debug("No PCI busses?\n"); 1655093badbSSimon Glass return -ENODEV; 1661853030eSSimon Glass } 1671853030eSSimon Glass 1681853030eSSimon Glass for (bus = 0; bus <= last_bus; bus++) { 1691853030eSSimon Glass uint16_t vendor_id, device_id; 1701853030eSSimon Glass uint32_t ids; 1711853030eSSimon Glass pci_dev_t dev; 1721853030eSSimon Glass 1731853030eSSimon Glass dev = PCI_BDF(bus, 31, 0); 1741853030eSSimon Glass pci_read_config_dword(dev, 0, &ids); 1751853030eSSimon Glass vendor_id = ids; 1761853030eSSimon Glass device_id = ids >> 16; 1771853030eSSimon Glass 1781853030eSSimon Glass if (vendor_id == PCI_VENDOR_ID_INTEL) { 1795093badbSSimon Glass ich->dev = dev; 1805093badbSSimon Glass ich->ich_version = get_ich_version(device_id); 1815093badbSSimon Glass if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) 1825093badbSSimon Glass ich->use_sbase = true; 1835093badbSSimon Glass return ich->ich_version == 0 ? -ENODEV : 0; 1841853030eSSimon Glass } 1851853030eSSimon Glass } 1861853030eSSimon Glass 1871853030eSSimon Glass debug("ICH SPI: No ICH found.\n"); 1885093badbSSimon Glass return -ENODEV; 1891853030eSSimon Glass } 1901853030eSSimon Glass 191ba457562SSimon Glass static int ich_init_controller(struct ich_spi_platdata *plat, 192ba457562SSimon Glass struct ich_spi_priv *ctlr) 1931853030eSSimon Glass { 1941853030eSSimon Glass uint8_t *rcrb; /* Root Complex Register Block */ 1951853030eSSimon Glass uint32_t rcba; /* Root Complex Base Address */ 1965093badbSSimon Glass uint32_t sbase_addr; 1975093badbSSimon Glass uint8_t *sbase; 1981853030eSSimon Glass 199ba457562SSimon Glass pci_read_config_dword(plat->dev, 0xf0, &rcba); 2001853030eSSimon Glass /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ 2011853030eSSimon Glass rcrb = (uint8_t *)(rcba & 0xffffc000); 2025093badbSSimon Glass 2035093badbSSimon Glass /* SBASE is similar */ 204ba457562SSimon Glass pci_read_config_dword(plat->dev, 0x54, &sbase_addr); 2055093badbSSimon Glass sbase = (uint8_t *)(sbase_addr & 0xfffffe00); 2065093badbSSimon Glass 207ba457562SSimon Glass if (plat->ich_version == 7) { 2081853030eSSimon Glass struct ich7_spi_regs *ich7_spi; 2091853030eSSimon Glass 2101853030eSSimon Glass ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); 211ba457562SSimon Glass ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; 212ba457562SSimon Glass ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); 2131853030eSSimon Glass ctlr->menubytes = sizeof(ich7_spi->opmenu); 214ba457562SSimon Glass ctlr->optype = offsetof(struct ich7_spi_regs, optype); 215ba457562SSimon Glass ctlr->addr = offsetof(struct ich7_spi_regs, spia); 216ba457562SSimon Glass ctlr->data = offsetof(struct ich7_spi_regs, spid); 2171853030eSSimon Glass ctlr->databytes = sizeof(ich7_spi->spid); 218ba457562SSimon Glass ctlr->status = offsetof(struct ich7_spi_regs, spis); 219ba457562SSimon Glass ctlr->control = offsetof(struct ich7_spi_regs, spic); 220ba457562SSimon Glass ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); 221ba457562SSimon Glass ctlr->preop = offsetof(struct ich7_spi_regs, preop); 2221853030eSSimon Glass ctlr->base = ich7_spi; 223ba457562SSimon Glass } else if (plat->ich_version == 9) { 2241853030eSSimon Glass struct ich9_spi_regs *ich9_spi; 2251853030eSSimon Glass 226ba457562SSimon Glass if (plat->use_sbase) 2275093badbSSimon Glass ich9_spi = (struct ich9_spi_regs *)sbase; 2285093badbSSimon Glass else 2291853030eSSimon Glass ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); 230ba457562SSimon Glass ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 231ba457562SSimon Glass ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); 2321853030eSSimon Glass ctlr->menubytes = sizeof(ich9_spi->opmenu); 233ba457562SSimon Glass ctlr->optype = offsetof(struct ich9_spi_regs, optype); 234ba457562SSimon Glass ctlr->addr = offsetof(struct ich9_spi_regs, faddr); 235ba457562SSimon Glass ctlr->data = offsetof(struct ich9_spi_regs, fdata); 2361853030eSSimon Glass ctlr->databytes = sizeof(ich9_spi->fdata); 237ba457562SSimon Glass ctlr->status = offsetof(struct ich9_spi_regs, ssfs); 238ba457562SSimon Glass ctlr->control = offsetof(struct ich9_spi_regs, ssfc); 239ba457562SSimon Glass ctlr->speed = ctlr->control + 2; 240ba457562SSimon Glass ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); 241ba457562SSimon Glass ctlr->preop = offsetof(struct ich9_spi_regs, preop); 2421853030eSSimon Glass ctlr->pr = &ich9_spi->pr[0]; 2431853030eSSimon Glass ctlr->base = ich9_spi; 2441853030eSSimon Glass } else { 245ba457562SSimon Glass debug("ICH SPI: Unrecognised ICH version %d\n", 246ba457562SSimon Glass plat->ich_version); 247ba457562SSimon Glass return -EINVAL; 2481853030eSSimon Glass } 2491853030eSSimon Glass 2501853030eSSimon Glass /* Work out the maximum speed we can support */ 2511853030eSSimon Glass ctlr->max_speed = 20000000; 252ba457562SSimon Glass if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev)) 2531853030eSSimon Glass ctlr->max_speed = 33000000; 2545093badbSSimon Glass debug("ICH SPI: Version %d detected at %p, speed %ld\n", 255ba457562SSimon Glass plat->ich_version, ctlr->base, ctlr->max_speed); 2561853030eSSimon Glass 2571853030eSSimon Glass ich_set_bbar(ctlr, 0); 2581853030eSSimon Glass 2591853030eSSimon Glass return 0; 2601853030eSSimon Glass } 2611853030eSSimon Glass 2621853030eSSimon Glass static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 2631853030eSSimon Glass { 2641853030eSSimon Glass trans->out += bytes; 2651853030eSSimon Glass trans->bytesout -= bytes; 2661853030eSSimon Glass } 2671853030eSSimon Glass 2681853030eSSimon Glass static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 2691853030eSSimon Glass { 2701853030eSSimon Glass trans->in += bytes; 2711853030eSSimon Glass trans->bytesin -= bytes; 2721853030eSSimon Glass } 2731853030eSSimon Glass 2741853030eSSimon Glass static void spi_setup_type(struct spi_trans *trans, int data_bytes) 2751853030eSSimon Glass { 2761853030eSSimon Glass trans->type = 0xFF; 2771853030eSSimon Glass 2781853030eSSimon Glass /* Try to guess spi type from read/write sizes. */ 2791853030eSSimon Glass if (trans->bytesin == 0) { 2801853030eSSimon Glass if (trans->bytesout + data_bytes > 4) 2811853030eSSimon Glass /* 2821853030eSSimon Glass * If bytesin = 0 and bytesout > 4, we presume this is 2831853030eSSimon Glass * a write data operation, which is accompanied by an 2841853030eSSimon Glass * address. 2851853030eSSimon Glass */ 2861853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 2871853030eSSimon Glass else 2881853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 2891853030eSSimon Glass return; 2901853030eSSimon Glass } 2911853030eSSimon Glass 2921853030eSSimon Glass if (trans->bytesout == 1) { /* and bytesin is > 0 */ 2931853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 2941853030eSSimon Glass return; 2951853030eSSimon Glass } 2961853030eSSimon Glass 2971853030eSSimon Glass if (trans->bytesout == 4) /* and bytesin is > 0 */ 2981853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 2991853030eSSimon Glass 3001853030eSSimon Glass /* Fast read command is called with 5 bytes instead of 4 */ 3011853030eSSimon Glass if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 3021853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 3031853030eSSimon Glass --trans->bytesout; 3041853030eSSimon Glass } 3051853030eSSimon Glass } 3061853030eSSimon Glass 307ba457562SSimon Glass static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) 3081853030eSSimon Glass { 3091853030eSSimon Glass uint16_t optypes; 310ba457562SSimon Glass uint8_t opmenu[ctlr->menubytes]; 3111853030eSSimon Glass 3121853030eSSimon Glass trans->opcode = trans->out[0]; 3131853030eSSimon Glass spi_use_out(trans, 1); 314ba457562SSimon Glass if (!ctlr->ichspi_lock) { 3151853030eSSimon Glass /* The lock is off, so just use index 0. */ 316ba457562SSimon Glass ich_writeb(ctlr, trans->opcode, ctlr->opmenu); 317ba457562SSimon Glass optypes = ich_readw(ctlr, ctlr->optype); 3181853030eSSimon Glass optypes = (optypes & 0xfffc) | (trans->type & 0x3); 319ba457562SSimon Glass ich_writew(ctlr, optypes, ctlr->optype); 3201853030eSSimon Glass return 0; 3211853030eSSimon Glass } else { 3221853030eSSimon Glass /* The lock is on. See if what we need is on the menu. */ 3231853030eSSimon Glass uint8_t optype; 3241853030eSSimon Glass uint16_t opcode_index; 3251853030eSSimon Glass 3261853030eSSimon Glass /* Write Enable is handled as atomic prefix */ 3271853030eSSimon Glass if (trans->opcode == SPI_OPCODE_WREN) 3281853030eSSimon Glass return 0; 3291853030eSSimon Glass 330ba457562SSimon Glass read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); 331ba457562SSimon Glass for (opcode_index = 0; opcode_index < ctlr->menubytes; 3321853030eSSimon Glass opcode_index++) { 3331853030eSSimon Glass if (opmenu[opcode_index] == trans->opcode) 3341853030eSSimon Glass break; 3351853030eSSimon Glass } 3361853030eSSimon Glass 337ba457562SSimon Glass if (opcode_index == ctlr->menubytes) { 3381853030eSSimon Glass printf("ICH SPI: Opcode %x not found\n", 3391853030eSSimon Glass trans->opcode); 340ba457562SSimon Glass return -EINVAL; 3411853030eSSimon Glass } 3421853030eSSimon Glass 343ba457562SSimon Glass optypes = ich_readw(ctlr, ctlr->optype); 3441853030eSSimon Glass optype = (optypes >> (opcode_index * 2)) & 0x3; 3451853030eSSimon Glass if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 3461853030eSSimon Glass optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 3471853030eSSimon Glass trans->bytesout >= 3) { 3481853030eSSimon Glass /* We guessed wrong earlier. Fix it up. */ 3491853030eSSimon Glass trans->type = optype; 3501853030eSSimon Glass } 3511853030eSSimon Glass if (optype != trans->type) { 3521853030eSSimon Glass printf("ICH SPI: Transaction doesn't fit type %d\n", 3531853030eSSimon Glass optype); 354ba457562SSimon Glass return -ENOSPC; 3551853030eSSimon Glass } 3561853030eSSimon Glass return opcode_index; 3571853030eSSimon Glass } 3581853030eSSimon Glass } 3591853030eSSimon Glass 3601853030eSSimon Glass static int spi_setup_offset(struct spi_trans *trans) 3611853030eSSimon Glass { 3621853030eSSimon Glass /* Separate the SPI address and data. */ 3631853030eSSimon Glass switch (trans->type) { 3641853030eSSimon Glass case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 3651853030eSSimon Glass case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 3661853030eSSimon Glass return 0; 3671853030eSSimon Glass case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 3681853030eSSimon Glass case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 3691853030eSSimon Glass trans->offset = ((uint32_t)trans->out[0] << 16) | 3701853030eSSimon Glass ((uint32_t)trans->out[1] << 8) | 3711853030eSSimon Glass ((uint32_t)trans->out[2] << 0); 3721853030eSSimon Glass spi_use_out(trans, 3); 3731853030eSSimon Glass return 1; 3741853030eSSimon Glass default: 3751853030eSSimon Glass printf("Unrecognized SPI transaction type %#x\n", trans->type); 376ba457562SSimon Glass return -EPROTO; 3771853030eSSimon Glass } 3781853030eSSimon Glass } 3791853030eSSimon Glass 3801853030eSSimon Glass /* 3811853030eSSimon Glass * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 382472d5460SYork Sun * below is true) or 0. In case the wait was for the bit(s) to set - write 3831853030eSSimon Glass * those bits back, which would cause resetting them. 3841853030eSSimon Glass * 3851853030eSSimon Glass * Return the last read status value on success or -1 on failure. 3861853030eSSimon Glass */ 387ba457562SSimon Glass static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, 388ba457562SSimon Glass int wait_til_set) 3891853030eSSimon Glass { 3901853030eSSimon Glass int timeout = 600000; /* This will result in 6s */ 3911853030eSSimon Glass u16 status = 0; 3921853030eSSimon Glass 3931853030eSSimon Glass while (timeout--) { 394ba457562SSimon Glass status = ich_readw(ctlr, ctlr->status); 3951853030eSSimon Glass if (wait_til_set ^ ((status & bitmask) == 0)) { 396ba457562SSimon Glass if (wait_til_set) { 397ba457562SSimon Glass ich_writew(ctlr, status & bitmask, 398ba457562SSimon Glass ctlr->status); 399ba457562SSimon Glass } 4001853030eSSimon Glass return status; 4011853030eSSimon Glass } 4021853030eSSimon Glass udelay(10); 4031853030eSSimon Glass } 4041853030eSSimon Glass 4051853030eSSimon Glass printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 4061853030eSSimon Glass status, bitmask); 407ba457562SSimon Glass return -ETIMEDOUT; 4081853030eSSimon Glass } 4091853030eSSimon Glass 410ba457562SSimon Glass static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, 411ba457562SSimon Glass const void *dout, void *din, unsigned long flags) 4121853030eSSimon Glass { 413ba457562SSimon Glass struct udevice *bus = dev_get_parent(dev); 414*e1e332c8SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus); 415ba457562SSimon Glass struct ich_spi_priv *ctlr = dev_get_priv(bus); 4161853030eSSimon Glass uint16_t control; 4171853030eSSimon Glass int16_t opcode_index; 4181853030eSSimon Glass int with_address; 4191853030eSSimon Glass int status; 4201853030eSSimon Glass int bytes = bitlen / 8; 421ba457562SSimon Glass struct spi_trans *trans = &ctlr->trans; 4221853030eSSimon Glass unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 4231853030eSSimon Glass int using_cmd = 0; 424ba457562SSimon Glass int ret; 4251853030eSSimon Glass 4265d4a757cSSimon Glass /* We don't support writing partial bytes */ 4271853030eSSimon Glass if (bitlen % 8) { 4281853030eSSimon Glass debug("ICH SPI: Accessing partial bytes not supported\n"); 429ba457562SSimon Glass return -EPROTONOSUPPORT; 4301853030eSSimon Glass } 4311853030eSSimon Glass 4321853030eSSimon Glass /* An empty end transaction can be ignored */ 4331853030eSSimon Glass if (type == SPI_XFER_END && !dout && !din) 4341853030eSSimon Glass return 0; 4351853030eSSimon Glass 4361853030eSSimon Glass if (type & SPI_XFER_BEGIN) 4371853030eSSimon Glass memset(trans, '\0', sizeof(*trans)); 4381853030eSSimon Glass 4391853030eSSimon Glass /* Dp we need to come back later to finish it? */ 4401853030eSSimon Glass if (dout && type == SPI_XFER_BEGIN) { 4411853030eSSimon Glass if (bytes > ICH_MAX_CMD_LEN) { 4421853030eSSimon Glass debug("ICH SPI: Command length limit exceeded\n"); 443ba457562SSimon Glass return -ENOSPC; 4441853030eSSimon Glass } 4451853030eSSimon Glass memcpy(trans->cmd, dout, bytes); 4461853030eSSimon Glass trans->cmd_len = bytes; 4471853030eSSimon Glass debug("ICH SPI: Saved %d bytes\n", bytes); 4481853030eSSimon Glass return 0; 4491853030eSSimon Glass } 4501853030eSSimon Glass 4511853030eSSimon Glass /* 4521853030eSSimon Glass * We process a 'middle' spi_xfer() call, which has no 4531853030eSSimon Glass * SPI_XFER_BEGIN/END, as an independent transaction as if it had 4541853030eSSimon Glass * an end. We therefore repeat the command. This is because ICH 4551853030eSSimon Glass * seems to have no support for this, or because interest (in digging 4561853030eSSimon Glass * out the details and creating a special case in the code) is low. 4571853030eSSimon Glass */ 4581853030eSSimon Glass if (trans->cmd_len) { 4591853030eSSimon Glass trans->out = trans->cmd; 4601853030eSSimon Glass trans->bytesout = trans->cmd_len; 4611853030eSSimon Glass using_cmd = 1; 4621853030eSSimon Glass debug("ICH SPI: Using %d bytes\n", trans->cmd_len); 4631853030eSSimon Glass } else { 4641853030eSSimon Glass trans->out = dout; 4651853030eSSimon Glass trans->bytesout = dout ? bytes : 0; 4661853030eSSimon Glass } 4671853030eSSimon Glass 4681853030eSSimon Glass trans->in = din; 4691853030eSSimon Glass trans->bytesin = din ? bytes : 0; 4701853030eSSimon Glass 4711853030eSSimon Glass /* There has to always at least be an opcode. */ 4721853030eSSimon Glass if (!trans->bytesout) { 4731853030eSSimon Glass debug("ICH SPI: No opcode for transfer\n"); 474ba457562SSimon Glass return -EPROTO; 4751853030eSSimon Glass } 4761853030eSSimon Glass 477ba457562SSimon Glass ret = ich_status_poll(ctlr, SPIS_SCIP, 0); 478ba457562SSimon Glass if (ret < 0) 479ba457562SSimon Glass return ret; 4801853030eSSimon Glass 481*e1e332c8SSimon Glass if (plat->ich_version == 7) 482ba457562SSimon Glass ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 483*e1e332c8SSimon Glass else 484*e1e332c8SSimon Glass ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 4851853030eSSimon Glass 4861853030eSSimon Glass spi_setup_type(trans, using_cmd ? bytes : 0); 487ba457562SSimon Glass opcode_index = spi_setup_opcode(ctlr, trans); 4881853030eSSimon Glass if (opcode_index < 0) 489ba457562SSimon Glass return -EINVAL; 4901853030eSSimon Glass with_address = spi_setup_offset(trans); 4911853030eSSimon Glass if (with_address < 0) 492ba457562SSimon Glass return -EINVAL; 4931853030eSSimon Glass 4941853030eSSimon Glass if (trans->opcode == SPI_OPCODE_WREN) { 4951853030eSSimon Glass /* 4961853030eSSimon Glass * Treat Write Enable as Atomic Pre-Op if possible 4971853030eSSimon Glass * in order to prevent the Management Engine from 4981853030eSSimon Glass * issuing a transaction between WREN and DATA. 4991853030eSSimon Glass */ 500ba457562SSimon Glass if (!ctlr->ichspi_lock) 501ba457562SSimon Glass ich_writew(ctlr, trans->opcode, ctlr->preop); 5021853030eSSimon Glass return 0; 5031853030eSSimon Glass } 5041853030eSSimon Glass 505ba457562SSimon Glass if (ctlr->speed && ctlr->max_speed >= 33000000) { 5061853030eSSimon Glass int byte; 5071853030eSSimon Glass 508ba457562SSimon Glass byte = ich_readb(ctlr, ctlr->speed); 509ba457562SSimon Glass if (ctlr->cur_speed >= 33000000) 5101853030eSSimon Glass byte |= SSFC_SCF_33MHZ; 5111853030eSSimon Glass else 5121853030eSSimon Glass byte &= ~SSFC_SCF_33MHZ; 513ba457562SSimon Glass ich_writeb(ctlr, byte, ctlr->speed); 5141853030eSSimon Glass } 5151853030eSSimon Glass 5161853030eSSimon Glass /* See if we have used up the command data */ 5171853030eSSimon Glass if (using_cmd && dout && bytes) { 5181853030eSSimon Glass trans->out = dout; 5191853030eSSimon Glass trans->bytesout = bytes; 5201853030eSSimon Glass debug("ICH SPI: Moving to data, %d bytes\n", bytes); 5211853030eSSimon Glass } 5221853030eSSimon Glass 5231853030eSSimon Glass /* Preset control fields */ 524ba457562SSimon Glass control = ich_readw(ctlr, ctlr->control); 5251853030eSSimon Glass control &= ~SSFC_RESERVED; 5261853030eSSimon Glass control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 5271853030eSSimon Glass 5281853030eSSimon Glass /* Issue atomic preop cycle if needed */ 529ba457562SSimon Glass if (ich_readw(ctlr, ctlr->preop)) 5301853030eSSimon Glass control |= SPIC_ACS; 5311853030eSSimon Glass 5321853030eSSimon Glass if (!trans->bytesout && !trans->bytesin) { 5331853030eSSimon Glass /* SPI addresses are 24 bit only */ 534ba457562SSimon Glass if (with_address) { 535ba457562SSimon Glass ich_writel(ctlr, trans->offset & 0x00FFFFFF, 536ba457562SSimon Glass ctlr->addr); 537ba457562SSimon Glass } 5381853030eSSimon Glass /* 5391853030eSSimon Glass * This is a 'no data' command (like Write Enable), its 5401853030eSSimon Glass * bitesout size was 1, decremented to zero while executing 5411853030eSSimon Glass * spi_setup_opcode() above. Tell the chip to send the 5421853030eSSimon Glass * command. 5431853030eSSimon Glass */ 544ba457562SSimon Glass ich_writew(ctlr, control, ctlr->control); 5451853030eSSimon Glass 5461853030eSSimon Glass /* wait for the result */ 547ba457562SSimon Glass status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 548ba457562SSimon Glass if (status < 0) 549ba457562SSimon Glass return status; 5501853030eSSimon Glass 5511853030eSSimon Glass if (status & SPIS_FCERR) { 5521853030eSSimon Glass debug("ICH SPI: Command transaction error\n"); 553ba457562SSimon Glass return -EIO; 5541853030eSSimon Glass } 5551853030eSSimon Glass 5561853030eSSimon Glass return 0; 5571853030eSSimon Glass } 5581853030eSSimon Glass 5591853030eSSimon Glass /* 5601853030eSSimon Glass * Check if this is a write command atempting to transfer more bytes 5611853030eSSimon Glass * than the controller can handle. Iterations for writes are not 5621853030eSSimon Glass * supported here because each SPI write command needs to be preceded 5631853030eSSimon Glass * and followed by other SPI commands, and this sequence is controlled 5641853030eSSimon Glass * by the SPI chip driver. 5651853030eSSimon Glass */ 566ba457562SSimon Glass if (trans->bytesout > ctlr->databytes) { 5671853030eSSimon Glass debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 568ba457562SSimon Glass return -EPROTO; 5691853030eSSimon Glass } 5701853030eSSimon Glass 5711853030eSSimon Glass /* 5721853030eSSimon Glass * Read or write up to databytes bytes at a time until everything has 5731853030eSSimon Glass * been sent. 5741853030eSSimon Glass */ 5751853030eSSimon Glass while (trans->bytesout || trans->bytesin) { 5761853030eSSimon Glass uint32_t data_length; 5771853030eSSimon Glass 5781853030eSSimon Glass /* SPI addresses are 24 bit only */ 579ba457562SSimon Glass ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); 5801853030eSSimon Glass 5811853030eSSimon Glass if (trans->bytesout) 582ba457562SSimon Glass data_length = min(trans->bytesout, ctlr->databytes); 5831853030eSSimon Glass else 584ba457562SSimon Glass data_length = min(trans->bytesin, ctlr->databytes); 5851853030eSSimon Glass 5861853030eSSimon Glass /* Program data into FDATA0 to N */ 5871853030eSSimon Glass if (trans->bytesout) { 588ba457562SSimon Glass write_reg(ctlr, trans->out, ctlr->data, data_length); 5891853030eSSimon Glass spi_use_out(trans, data_length); 5901853030eSSimon Glass if (with_address) 5911853030eSSimon Glass trans->offset += data_length; 5921853030eSSimon Glass } 5931853030eSSimon Glass 5941853030eSSimon Glass /* Add proper control fields' values */ 595ba457562SSimon Glass control &= ~((ctlr->databytes - 1) << 8); 5961853030eSSimon Glass control |= SPIC_DS; 5971853030eSSimon Glass control |= (data_length - 1) << 8; 5981853030eSSimon Glass 5991853030eSSimon Glass /* write it */ 600ba457562SSimon Glass ich_writew(ctlr, control, ctlr->control); 6011853030eSSimon Glass 6021853030eSSimon Glass /* Wait for Cycle Done Status or Flash Cycle Error. */ 603ba457562SSimon Glass status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 604ba457562SSimon Glass if (status < 0) 605ba457562SSimon Glass return status; 6061853030eSSimon Glass 6071853030eSSimon Glass if (status & SPIS_FCERR) { 6085d4a757cSSimon Glass debug("ICH SPI: Data transaction error %x\n", status); 609ba457562SSimon Glass return -EIO; 6101853030eSSimon Glass } 6111853030eSSimon Glass 6121853030eSSimon Glass if (trans->bytesin) { 613ba457562SSimon Glass read_reg(ctlr, ctlr->data, trans->in, data_length); 6141853030eSSimon Glass spi_use_in(trans, data_length); 6151853030eSSimon Glass if (with_address) 6161853030eSSimon Glass trans->offset += data_length; 6171853030eSSimon Glass } 6181853030eSSimon Glass } 6191853030eSSimon Glass 6201853030eSSimon Glass /* Clear atomic preop now that xfer is done */ 621ba457562SSimon Glass ich_writew(ctlr, 0, ctlr->preop); 6221853030eSSimon Glass 6231853030eSSimon Glass return 0; 6241853030eSSimon Glass } 6251853030eSSimon Glass 6261853030eSSimon Glass /* 6271853030eSSimon Glass * This uses the SPI controller from the Intel Cougar Point and Panther Point 6281853030eSSimon Glass * PCH to write-protect portions of the SPI flash until reboot. The changes 6291853030eSSimon Glass * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 6301853030eSSimon Glass * done elsewhere. 6311853030eSSimon Glass */ 632ba457562SSimon Glass int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, 633ba457562SSimon Glass uint32_t length, int hint) 6341853030eSSimon Glass { 635ba457562SSimon Glass struct udevice *bus = dev->parent; 636ba457562SSimon Glass struct ich_spi_priv *ctlr = dev_get_priv(bus); 6371853030eSSimon Glass uint32_t tmplong; 6381853030eSSimon Glass uint32_t upper_limit; 6391853030eSSimon Glass 640ba457562SSimon Glass if (!ctlr->pr) { 6411853030eSSimon Glass printf("%s: operation not supported on this chipset\n", 6421853030eSSimon Glass __func__); 643ba457562SSimon Glass return -ENOSYS; 6441853030eSSimon Glass } 6451853030eSSimon Glass 6461853030eSSimon Glass if (length == 0 || 6471853030eSSimon Glass lower_limit > (0xFFFFFFFFUL - length) + 1 || 6481853030eSSimon Glass hint < 0 || hint > 4) { 6491853030eSSimon Glass printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 6501853030eSSimon Glass lower_limit, length, hint); 651ba457562SSimon Glass return -EPERM; 6521853030eSSimon Glass } 6531853030eSSimon Glass 6541853030eSSimon Glass upper_limit = lower_limit + length - 1; 6551853030eSSimon Glass 6561853030eSSimon Glass /* 6571853030eSSimon Glass * Determine bits to write, as follows: 6581853030eSSimon Glass * 31 Write-protection enable (includes erase operation) 6591853030eSSimon Glass * 30:29 reserved 6601853030eSSimon Glass * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 6611853030eSSimon Glass * 15 Read-protection enable 6621853030eSSimon Glass * 14:13 reserved 6631853030eSSimon Glass * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 6641853030eSSimon Glass */ 6651853030eSSimon Glass tmplong = 0x80000000 | 6661853030eSSimon Glass ((upper_limit & 0x01fff000) << 4) | 6671853030eSSimon Glass ((lower_limit & 0x01fff000) >> 12); 6681853030eSSimon Glass 6691853030eSSimon Glass printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 670ba457562SSimon Glass &ctlr->pr[hint]); 671ba457562SSimon Glass ctlr->pr[hint] = tmplong; 6721853030eSSimon Glass 6731853030eSSimon Glass return 0; 6741853030eSSimon Glass } 675ba457562SSimon Glass 676ba457562SSimon Glass static int ich_spi_probe(struct udevice *bus) 677ba457562SSimon Glass { 678ba457562SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus); 679ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus); 680ba457562SSimon Glass uint8_t bios_cntl; 681ba457562SSimon Glass int ret; 682ba457562SSimon Glass 683ba457562SSimon Glass ret = ich_init_controller(plat, priv); 684ba457562SSimon Glass if (ret) 685ba457562SSimon Glass return ret; 686ba457562SSimon Glass /* 687ba457562SSimon Glass * Disable the BIOS write protect so write commands are allowed. On 688ba457562SSimon Glass * v9, deassert SMM BIOS Write Protect Disable. 689ba457562SSimon Glass */ 690ba457562SSimon Glass if (plat->use_sbase) { 691ba457562SSimon Glass struct ich9_spi_regs *ich9_spi; 692ba457562SSimon Glass 693ba457562SSimon Glass ich9_spi = priv->base; 694ba457562SSimon Glass bios_cntl = ich_readb(priv, ich9_spi->bcr); 695ba457562SSimon Glass bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */ 696ba457562SSimon Glass bios_cntl |= 1; /* Write Protect Disable (WPD) */ 697ba457562SSimon Glass ich_writeb(priv, bios_cntl, ich9_spi->bcr); 698ba457562SSimon Glass } else { 699ba457562SSimon Glass pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); 700ba457562SSimon Glass if (plat->ich_version == 9) 701ba457562SSimon Glass bios_cntl &= ~(1 << 5); 702ba457562SSimon Glass pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); 703ba457562SSimon Glass } 704ba457562SSimon Glass 705ba457562SSimon Glass priv->cur_speed = priv->max_speed; 706ba457562SSimon Glass 707ba457562SSimon Glass return 0; 708ba457562SSimon Glass } 709ba457562SSimon Glass 710ba457562SSimon Glass static int ich_spi_ofdata_to_platdata(struct udevice *bus) 711ba457562SSimon Glass { 712ba457562SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus); 713ba457562SSimon Glass int ret; 714ba457562SSimon Glass 715ba457562SSimon Glass ret = ich_find_spi_controller(plat); 716ba457562SSimon Glass if (ret) 717ba457562SSimon Glass return ret; 718ba457562SSimon Glass 719ba457562SSimon Glass return 0; 720ba457562SSimon Glass } 721ba457562SSimon Glass 722ba457562SSimon Glass static int ich_spi_set_speed(struct udevice *bus, uint speed) 723ba457562SSimon Glass { 724ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus); 725ba457562SSimon Glass 726ba457562SSimon Glass priv->cur_speed = speed; 727ba457562SSimon Glass 728ba457562SSimon Glass return 0; 729ba457562SSimon Glass } 730ba457562SSimon Glass 731ba457562SSimon Glass static int ich_spi_set_mode(struct udevice *bus, uint mode) 732ba457562SSimon Glass { 733ba457562SSimon Glass debug("%s: mode=%d\n", __func__, mode); 734ba457562SSimon Glass 735ba457562SSimon Glass return 0; 736ba457562SSimon Glass } 737ba457562SSimon Glass 738ba457562SSimon Glass static int ich_spi_child_pre_probe(struct udevice *dev) 739ba457562SSimon Glass { 740ba457562SSimon Glass struct udevice *bus = dev_get_parent(dev); 741ba457562SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus); 742ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus); 743ba457562SSimon Glass struct spi_slave *slave = dev_get_parentdata(dev); 744ba457562SSimon Glass 745ba457562SSimon Glass /* 746ba457562SSimon Glass * Yes this controller can only write a small number of bytes at 747ba457562SSimon Glass * once! The limit is typically 64 bytes. 748ba457562SSimon Glass */ 749ba457562SSimon Glass slave->max_write_size = priv->databytes; 750ba457562SSimon Glass /* 751ba457562SSimon Glass * ICH 7 SPI controller only supports array read command 752ba457562SSimon Glass * and byte program command for SST flash 753ba457562SSimon Glass */ 754ba457562SSimon Glass if (plat->ich_version == 7) { 755ba457562SSimon Glass slave->op_mode_rx = SPI_OPM_RX_AS; 756ba457562SSimon Glass slave->op_mode_tx = SPI_OPM_TX_BP; 757ba457562SSimon Glass } 758ba457562SSimon Glass 759ba457562SSimon Glass return 0; 760ba457562SSimon Glass } 761ba457562SSimon Glass 762ba457562SSimon Glass static const struct dm_spi_ops ich_spi_ops = { 763ba457562SSimon Glass .xfer = ich_spi_xfer, 764ba457562SSimon Glass .set_speed = ich_spi_set_speed, 765ba457562SSimon Glass .set_mode = ich_spi_set_mode, 766ba457562SSimon Glass /* 767ba457562SSimon Glass * cs_info is not needed, since we require all chip selects to be 768ba457562SSimon Glass * in the device tree explicitly 769ba457562SSimon Glass */ 770ba457562SSimon Glass }; 771ba457562SSimon Glass 772ba457562SSimon Glass static const struct udevice_id ich_spi_ids[] = { 773ba457562SSimon Glass { .compatible = "intel,ich-spi" }, 774ba457562SSimon Glass { } 775ba457562SSimon Glass }; 776ba457562SSimon Glass 777ba457562SSimon Glass U_BOOT_DRIVER(ich_spi) = { 778ba457562SSimon Glass .name = "ich_spi", 779ba457562SSimon Glass .id = UCLASS_SPI, 780ba457562SSimon Glass .of_match = ich_spi_ids, 781ba457562SSimon Glass .ops = &ich_spi_ops, 782ba457562SSimon Glass .ofdata_to_platdata = ich_spi_ofdata_to_platdata, 783ba457562SSimon Glass .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), 784ba457562SSimon Glass .priv_auto_alloc_size = sizeof(struct ich_spi_priv), 785ba457562SSimon Glass .child_pre_probe = ich_spi_child_pre_probe, 786ba457562SSimon Glass .probe = ich_spi_probe, 787ba457562SSimon Glass }; 788