11853030eSSimon Glass /* 21853030eSSimon Glass * Copyright (c) 2011-12 The Chromium OS Authors. 31853030eSSimon Glass * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 51853030eSSimon Glass * 61853030eSSimon Glass * This file is derived from the flashrom project. 71853030eSSimon Glass */ 89eb4339bSBin Meng 91853030eSSimon Glass #include <common.h> 10ba457562SSimon Glass #include <dm.h> 115093badbSSimon Glass #include <errno.h> 121853030eSSimon Glass #include <malloc.h> 13f2b85ab5SSimon Glass #include <pch.h> 141853030eSSimon Glass #include <pci.h> 151853030eSSimon Glass #include <pci_ids.h> 16f2b85ab5SSimon Glass #include <spi.h> 171853030eSSimon Glass #include <asm/io.h> 181853030eSSimon Glass 191853030eSSimon Glass #include "ich.h" 201853030eSSimon Glass 211f9eb59dSBin Meng DECLARE_GLOBAL_DATA_PTR; 221f9eb59dSBin Meng 23fffe25dbSSimon Glass #ifdef DEBUG_TRACE 24fffe25dbSSimon Glass #define debug_trace(fmt, args...) debug(fmt, ##args) 25fffe25dbSSimon Glass #else 26fffe25dbSSimon Glass #define debug_trace(x, args...) 27fffe25dbSSimon Glass #endif 28fffe25dbSSimon Glass 29ba457562SSimon Glass static u8 ich_readb(struct ich_spi_priv *priv, int reg) 301853030eSSimon Glass { 31ba457562SSimon Glass u8 value = readb(priv->base + reg); 321853030eSSimon Glass 33fffe25dbSSimon Glass debug_trace("read %2.2x from %4.4x\n", value, reg); 341853030eSSimon Glass 351853030eSSimon Glass return value; 361853030eSSimon Glass } 371853030eSSimon Glass 38ba457562SSimon Glass static u16 ich_readw(struct ich_spi_priv *priv, int reg) 391853030eSSimon Glass { 40ba457562SSimon Glass u16 value = readw(priv->base + reg); 411853030eSSimon Glass 42fffe25dbSSimon Glass debug_trace("read %4.4x from %4.4x\n", value, reg); 431853030eSSimon Glass 441853030eSSimon Glass return value; 451853030eSSimon Glass } 461853030eSSimon Glass 47ba457562SSimon Glass static u32 ich_readl(struct ich_spi_priv *priv, int reg) 481853030eSSimon Glass { 49ba457562SSimon Glass u32 value = readl(priv->base + reg); 501853030eSSimon Glass 51fffe25dbSSimon Glass debug_trace("read %8.8x from %4.4x\n", value, reg); 521853030eSSimon Glass 531853030eSSimon Glass return value; 541853030eSSimon Glass } 551853030eSSimon Glass 56ba457562SSimon Glass static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) 571853030eSSimon Glass { 58ba457562SSimon Glass writeb(value, priv->base + reg); 59fffe25dbSSimon Glass debug_trace("wrote %2.2x to %4.4x\n", value, reg); 601853030eSSimon Glass } 611853030eSSimon Glass 62ba457562SSimon Glass static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) 631853030eSSimon Glass { 64ba457562SSimon Glass writew(value, priv->base + reg); 65fffe25dbSSimon Glass debug_trace("wrote %4.4x to %4.4x\n", value, reg); 661853030eSSimon Glass } 671853030eSSimon Glass 68ba457562SSimon Glass static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) 691853030eSSimon Glass { 70ba457562SSimon Glass writel(value, priv->base + reg); 71fffe25dbSSimon Glass debug_trace("wrote %8.8x to %4.4x\n", value, reg); 721853030eSSimon Glass } 731853030eSSimon Glass 74ba457562SSimon Glass static void write_reg(struct ich_spi_priv *priv, const void *value, 75ba457562SSimon Glass int dest_reg, uint32_t size) 761853030eSSimon Glass { 77ba457562SSimon Glass memcpy_toio(priv->base + dest_reg, value, size); 781853030eSSimon Glass } 791853030eSSimon Glass 80ba457562SSimon Glass static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, 81ba457562SSimon Glass uint32_t size) 821853030eSSimon Glass { 83ba457562SSimon Glass memcpy_fromio(value, priv->base + src_reg, size); 841853030eSSimon Glass } 851853030eSSimon Glass 86ba457562SSimon Glass static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) 871853030eSSimon Glass { 881853030eSSimon Glass const uint32_t bbar_mask = 0x00ffff00; 891853030eSSimon Glass uint32_t ichspi_bbar; 901853030eSSimon Glass 911853030eSSimon Glass minaddr &= bbar_mask; 92ba457562SSimon Glass ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; 931853030eSSimon Glass ichspi_bbar |= minaddr; 94ba457562SSimon Glass ich_writel(ctlr, ichspi_bbar, ctlr->bbar); 951853030eSSimon Glass } 961853030eSSimon Glass 971853030eSSimon Glass /* @return 1 if the SPI flash supports the 33MHz speed */ 98f2b85ab5SSimon Glass static int ich9_can_do_33mhz(struct udevice *dev) 991853030eSSimon Glass { 1001853030eSSimon Glass u32 fdod, speed; 1011853030eSSimon Glass 1021853030eSSimon Glass /* Observe SPI Descriptor Component Section 0 */ 103f2b85ab5SSimon Glass dm_pci_write_config32(dev->parent, 0xb0, 0x1000); 1041853030eSSimon Glass 1051853030eSSimon Glass /* Extract the Write/Erase SPI Frequency from descriptor */ 106f2b85ab5SSimon Glass dm_pci_read_config32(dev->parent, 0xb4, &fdod); 1071853030eSSimon Glass 1081853030eSSimon Glass /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ 1091853030eSSimon Glass speed = (fdod >> 21) & 7; 1101853030eSSimon Glass 1111853030eSSimon Glass return speed == 1; 1121853030eSSimon Glass } 1131853030eSSimon Glass 114f2b85ab5SSimon Glass static int ich_init_controller(struct udevice *dev, 115f2b85ab5SSimon Glass struct ich_spi_platdata *plat, 116ba457562SSimon Glass struct ich_spi_priv *ctlr) 1171853030eSSimon Glass { 118f2b85ab5SSimon Glass ulong sbase_addr; 119f2b85ab5SSimon Glass void *sbase; 1205093badbSSimon Glass 1215093badbSSimon Glass /* SBASE is similar */ 1223e389d8bSBin Meng pch_get_spi_base(dev->parent, &sbase_addr); 123f2b85ab5SSimon Glass sbase = (void *)sbase_addr; 124f2b85ab5SSimon Glass debug("%s: sbase=%p\n", __func__, sbase); 1255093badbSSimon Glass 1266e670b5cSBin Meng if (plat->ich_version == ICHV_7) { 127f2b85ab5SSimon Glass struct ich7_spi_regs *ich7_spi = sbase; 1281853030eSSimon Glass 129f2b85ab5SSimon Glass ich7_spi = (struct ich7_spi_regs *)sbase; 130ba457562SSimon Glass ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; 131ba457562SSimon Glass ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); 1321853030eSSimon Glass ctlr->menubytes = sizeof(ich7_spi->opmenu); 133ba457562SSimon Glass ctlr->optype = offsetof(struct ich7_spi_regs, optype); 134ba457562SSimon Glass ctlr->addr = offsetof(struct ich7_spi_regs, spia); 135ba457562SSimon Glass ctlr->data = offsetof(struct ich7_spi_regs, spid); 1361853030eSSimon Glass ctlr->databytes = sizeof(ich7_spi->spid); 137ba457562SSimon Glass ctlr->status = offsetof(struct ich7_spi_regs, spis); 138ba457562SSimon Glass ctlr->control = offsetof(struct ich7_spi_regs, spic); 139ba457562SSimon Glass ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); 140ba457562SSimon Glass ctlr->preop = offsetof(struct ich7_spi_regs, preop); 1411853030eSSimon Glass ctlr->base = ich7_spi; 1426e670b5cSBin Meng } else if (plat->ich_version == ICHV_9) { 143f2b85ab5SSimon Glass struct ich9_spi_regs *ich9_spi = sbase; 1441853030eSSimon Glass 145ba457562SSimon Glass ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; 146ba457562SSimon Glass ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); 1471853030eSSimon Glass ctlr->menubytes = sizeof(ich9_spi->opmenu); 148ba457562SSimon Glass ctlr->optype = offsetof(struct ich9_spi_regs, optype); 149ba457562SSimon Glass ctlr->addr = offsetof(struct ich9_spi_regs, faddr); 150ba457562SSimon Glass ctlr->data = offsetof(struct ich9_spi_regs, fdata); 1511853030eSSimon Glass ctlr->databytes = sizeof(ich9_spi->fdata); 152ba457562SSimon Glass ctlr->status = offsetof(struct ich9_spi_regs, ssfs); 153ba457562SSimon Glass ctlr->control = offsetof(struct ich9_spi_regs, ssfc); 154ba457562SSimon Glass ctlr->speed = ctlr->control + 2; 155ba457562SSimon Glass ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); 156ba457562SSimon Glass ctlr->preop = offsetof(struct ich9_spi_regs, preop); 15750787928SSimon Glass ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); 1581853030eSSimon Glass ctlr->pr = &ich9_spi->pr[0]; 1591853030eSSimon Glass ctlr->base = ich9_spi; 1601853030eSSimon Glass } else { 161ba457562SSimon Glass debug("ICH SPI: Unrecognised ICH version %d\n", 162ba457562SSimon Glass plat->ich_version); 163ba457562SSimon Glass return -EINVAL; 1641853030eSSimon Glass } 1651853030eSSimon Glass 1661853030eSSimon Glass /* Work out the maximum speed we can support */ 1671853030eSSimon Glass ctlr->max_speed = 20000000; 1686e670b5cSBin Meng if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) 1691853030eSSimon Glass ctlr->max_speed = 33000000; 170f2b85ab5SSimon Glass debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", 171ba457562SSimon Glass plat->ich_version, ctlr->base, ctlr->max_speed); 1721853030eSSimon Glass 1731853030eSSimon Glass ich_set_bbar(ctlr, 0); 1741853030eSSimon Glass 1751853030eSSimon Glass return 0; 1761853030eSSimon Glass } 1771853030eSSimon Glass 1781853030eSSimon Glass static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) 1791853030eSSimon Glass { 1801853030eSSimon Glass trans->out += bytes; 1811853030eSSimon Glass trans->bytesout -= bytes; 1821853030eSSimon Glass } 1831853030eSSimon Glass 1841853030eSSimon Glass static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) 1851853030eSSimon Glass { 1861853030eSSimon Glass trans->in += bytes; 1871853030eSSimon Glass trans->bytesin -= bytes; 1881853030eSSimon Glass } 1891853030eSSimon Glass 1901853030eSSimon Glass static void spi_setup_type(struct spi_trans *trans, int data_bytes) 1911853030eSSimon Glass { 1921853030eSSimon Glass trans->type = 0xFF; 1931853030eSSimon Glass 1949eb4339bSBin Meng /* Try to guess spi type from read/write sizes */ 1951853030eSSimon Glass if (trans->bytesin == 0) { 1961853030eSSimon Glass if (trans->bytesout + data_bytes > 4) 1971853030eSSimon Glass /* 1981853030eSSimon Glass * If bytesin = 0 and bytesout > 4, we presume this is 1991853030eSSimon Glass * a write data operation, which is accompanied by an 2001853030eSSimon Glass * address. 2011853030eSSimon Glass */ 2021853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; 2031853030eSSimon Glass else 2041853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; 2051853030eSSimon Glass return; 2061853030eSSimon Glass } 2071853030eSSimon Glass 2081853030eSSimon Glass if (trans->bytesout == 1) { /* and bytesin is > 0 */ 2091853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; 2101853030eSSimon Glass return; 2111853030eSSimon Glass } 2121853030eSSimon Glass 2131853030eSSimon Glass if (trans->bytesout == 4) /* and bytesin is > 0 */ 2141853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 2151853030eSSimon Glass 2161853030eSSimon Glass /* Fast read command is called with 5 bytes instead of 4 */ 2171853030eSSimon Glass if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { 2181853030eSSimon Glass trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; 2191853030eSSimon Glass --trans->bytesout; 2201853030eSSimon Glass } 2211853030eSSimon Glass } 2221853030eSSimon Glass 223ba457562SSimon Glass static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) 2241853030eSSimon Glass { 2251853030eSSimon Glass uint16_t optypes; 226ba457562SSimon Glass uint8_t opmenu[ctlr->menubytes]; 2271853030eSSimon Glass 2281853030eSSimon Glass trans->opcode = trans->out[0]; 2291853030eSSimon Glass spi_use_out(trans, 1); 230ba457562SSimon Glass if (!ctlr->ichspi_lock) { 2311853030eSSimon Glass /* The lock is off, so just use index 0. */ 232ba457562SSimon Glass ich_writeb(ctlr, trans->opcode, ctlr->opmenu); 233ba457562SSimon Glass optypes = ich_readw(ctlr, ctlr->optype); 2341853030eSSimon Glass optypes = (optypes & 0xfffc) | (trans->type & 0x3); 235ba457562SSimon Glass ich_writew(ctlr, optypes, ctlr->optype); 2361853030eSSimon Glass return 0; 2371853030eSSimon Glass } else { 2381853030eSSimon Glass /* The lock is on. See if what we need is on the menu. */ 2391853030eSSimon Glass uint8_t optype; 2401853030eSSimon Glass uint16_t opcode_index; 2411853030eSSimon Glass 2421853030eSSimon Glass /* Write Enable is handled as atomic prefix */ 2431853030eSSimon Glass if (trans->opcode == SPI_OPCODE_WREN) 2441853030eSSimon Glass return 0; 2451853030eSSimon Glass 246ba457562SSimon Glass read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); 247ba457562SSimon Glass for (opcode_index = 0; opcode_index < ctlr->menubytes; 2481853030eSSimon Glass opcode_index++) { 2491853030eSSimon Glass if (opmenu[opcode_index] == trans->opcode) 2501853030eSSimon Glass break; 2511853030eSSimon Glass } 2521853030eSSimon Glass 253ba457562SSimon Glass if (opcode_index == ctlr->menubytes) { 2541853030eSSimon Glass printf("ICH SPI: Opcode %x not found\n", 2551853030eSSimon Glass trans->opcode); 256ba457562SSimon Glass return -EINVAL; 2571853030eSSimon Glass } 2581853030eSSimon Glass 259ba457562SSimon Glass optypes = ich_readw(ctlr, ctlr->optype); 2601853030eSSimon Glass optype = (optypes >> (opcode_index * 2)) & 0x3; 2611853030eSSimon Glass if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && 2621853030eSSimon Glass optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && 2631853030eSSimon Glass trans->bytesout >= 3) { 2641853030eSSimon Glass /* We guessed wrong earlier. Fix it up. */ 2651853030eSSimon Glass trans->type = optype; 2661853030eSSimon Glass } 2671853030eSSimon Glass if (optype != trans->type) { 2681853030eSSimon Glass printf("ICH SPI: Transaction doesn't fit type %d\n", 2691853030eSSimon Glass optype); 270ba457562SSimon Glass return -ENOSPC; 2711853030eSSimon Glass } 2721853030eSSimon Glass return opcode_index; 2731853030eSSimon Glass } 2741853030eSSimon Glass } 2751853030eSSimon Glass 2761853030eSSimon Glass static int spi_setup_offset(struct spi_trans *trans) 2771853030eSSimon Glass { 2789eb4339bSBin Meng /* Separate the SPI address and data */ 2791853030eSSimon Glass switch (trans->type) { 2801853030eSSimon Glass case SPI_OPCODE_TYPE_READ_NO_ADDRESS: 2811853030eSSimon Glass case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: 2821853030eSSimon Glass return 0; 2831853030eSSimon Glass case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: 2841853030eSSimon Glass case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: 2851853030eSSimon Glass trans->offset = ((uint32_t)trans->out[0] << 16) | 2861853030eSSimon Glass ((uint32_t)trans->out[1] << 8) | 2871853030eSSimon Glass ((uint32_t)trans->out[2] << 0); 2881853030eSSimon Glass spi_use_out(trans, 3); 2891853030eSSimon Glass return 1; 2901853030eSSimon Glass default: 2911853030eSSimon Glass printf("Unrecognized SPI transaction type %#x\n", trans->type); 292ba457562SSimon Glass return -EPROTO; 2931853030eSSimon Glass } 2941853030eSSimon Glass } 2951853030eSSimon Glass 2961853030eSSimon Glass /* 2971853030eSSimon Glass * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set 298472d5460SYork Sun * below is true) or 0. In case the wait was for the bit(s) to set - write 2991853030eSSimon Glass * those bits back, which would cause resetting them. 3001853030eSSimon Glass * 3011853030eSSimon Glass * Return the last read status value on success or -1 on failure. 3021853030eSSimon Glass */ 303ba457562SSimon Glass static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, 304ba457562SSimon Glass int wait_til_set) 3051853030eSSimon Glass { 3061853030eSSimon Glass int timeout = 600000; /* This will result in 6s */ 3071853030eSSimon Glass u16 status = 0; 3081853030eSSimon Glass 3091853030eSSimon Glass while (timeout--) { 310ba457562SSimon Glass status = ich_readw(ctlr, ctlr->status); 3111853030eSSimon Glass if (wait_til_set ^ ((status & bitmask) == 0)) { 312ba457562SSimon Glass if (wait_til_set) { 313ba457562SSimon Glass ich_writew(ctlr, status & bitmask, 314ba457562SSimon Glass ctlr->status); 315ba457562SSimon Glass } 3161853030eSSimon Glass return status; 3171853030eSSimon Glass } 3181853030eSSimon Glass udelay(10); 3191853030eSSimon Glass } 3201853030eSSimon Glass 3211853030eSSimon Glass printf("ICH SPI: SCIP timeout, read %x, expected %x\n", 3221853030eSSimon Glass status, bitmask); 323ba457562SSimon Glass return -ETIMEDOUT; 3241853030eSSimon Glass } 3251853030eSSimon Glass 326ba457562SSimon Glass static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, 327ba457562SSimon Glass const void *dout, void *din, unsigned long flags) 3281853030eSSimon Glass { 329ba457562SSimon Glass struct udevice *bus = dev_get_parent(dev); 330e1e332c8SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus); 331ba457562SSimon Glass struct ich_spi_priv *ctlr = dev_get_priv(bus); 3321853030eSSimon Glass uint16_t control; 3331853030eSSimon Glass int16_t opcode_index; 3341853030eSSimon Glass int with_address; 3351853030eSSimon Glass int status; 3361853030eSSimon Glass int bytes = bitlen / 8; 337ba457562SSimon Glass struct spi_trans *trans = &ctlr->trans; 3381853030eSSimon Glass unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); 3391853030eSSimon Glass int using_cmd = 0; 340ba457562SSimon Glass int ret; 3411853030eSSimon Glass 3425d4a757cSSimon Glass /* We don't support writing partial bytes */ 3431853030eSSimon Glass if (bitlen % 8) { 3441853030eSSimon Glass debug("ICH SPI: Accessing partial bytes not supported\n"); 345ba457562SSimon Glass return -EPROTONOSUPPORT; 3461853030eSSimon Glass } 3471853030eSSimon Glass 3481853030eSSimon Glass /* An empty end transaction can be ignored */ 3491853030eSSimon Glass if (type == SPI_XFER_END && !dout && !din) 3501853030eSSimon Glass return 0; 3511853030eSSimon Glass 3521853030eSSimon Glass if (type & SPI_XFER_BEGIN) 3531853030eSSimon Glass memset(trans, '\0', sizeof(*trans)); 3541853030eSSimon Glass 3551853030eSSimon Glass /* Dp we need to come back later to finish it? */ 3561853030eSSimon Glass if (dout && type == SPI_XFER_BEGIN) { 3571853030eSSimon Glass if (bytes > ICH_MAX_CMD_LEN) { 3581853030eSSimon Glass debug("ICH SPI: Command length limit exceeded\n"); 359ba457562SSimon Glass return -ENOSPC; 3601853030eSSimon Glass } 3611853030eSSimon Glass memcpy(trans->cmd, dout, bytes); 3621853030eSSimon Glass trans->cmd_len = bytes; 363fffe25dbSSimon Glass debug_trace("ICH SPI: Saved %d bytes\n", bytes); 3641853030eSSimon Glass return 0; 3651853030eSSimon Glass } 3661853030eSSimon Glass 3671853030eSSimon Glass /* 3681853030eSSimon Glass * We process a 'middle' spi_xfer() call, which has no 3691853030eSSimon Glass * SPI_XFER_BEGIN/END, as an independent transaction as if it had 3701853030eSSimon Glass * an end. We therefore repeat the command. This is because ICH 3711853030eSSimon Glass * seems to have no support for this, or because interest (in digging 3721853030eSSimon Glass * out the details and creating a special case in the code) is low. 3731853030eSSimon Glass */ 3741853030eSSimon Glass if (trans->cmd_len) { 3751853030eSSimon Glass trans->out = trans->cmd; 3761853030eSSimon Glass trans->bytesout = trans->cmd_len; 3771853030eSSimon Glass using_cmd = 1; 378fffe25dbSSimon Glass debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); 3791853030eSSimon Glass } else { 3801853030eSSimon Glass trans->out = dout; 3811853030eSSimon Glass trans->bytesout = dout ? bytes : 0; 3821853030eSSimon Glass } 3831853030eSSimon Glass 3841853030eSSimon Glass trans->in = din; 3851853030eSSimon Glass trans->bytesin = din ? bytes : 0; 3861853030eSSimon Glass 3879eb4339bSBin Meng /* There has to always at least be an opcode */ 3881853030eSSimon Glass if (!trans->bytesout) { 3891853030eSSimon Glass debug("ICH SPI: No opcode for transfer\n"); 390ba457562SSimon Glass return -EPROTO; 3911853030eSSimon Glass } 3921853030eSSimon Glass 393ba457562SSimon Glass ret = ich_status_poll(ctlr, SPIS_SCIP, 0); 394ba457562SSimon Glass if (ret < 0) 395ba457562SSimon Glass return ret; 3961853030eSSimon Glass 3976e670b5cSBin Meng if (plat->ich_version == ICHV_7) 398ba457562SSimon Glass ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 399e1e332c8SSimon Glass else 400e1e332c8SSimon Glass ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); 4011853030eSSimon Glass 4021853030eSSimon Glass spi_setup_type(trans, using_cmd ? bytes : 0); 403ba457562SSimon Glass opcode_index = spi_setup_opcode(ctlr, trans); 4041853030eSSimon Glass if (opcode_index < 0) 405ba457562SSimon Glass return -EINVAL; 4061853030eSSimon Glass with_address = spi_setup_offset(trans); 4071853030eSSimon Glass if (with_address < 0) 408ba457562SSimon Glass return -EINVAL; 4091853030eSSimon Glass 4101853030eSSimon Glass if (trans->opcode == SPI_OPCODE_WREN) { 4111853030eSSimon Glass /* 4121853030eSSimon Glass * Treat Write Enable as Atomic Pre-Op if possible 4131853030eSSimon Glass * in order to prevent the Management Engine from 4141853030eSSimon Glass * issuing a transaction between WREN and DATA. 4151853030eSSimon Glass */ 416ba457562SSimon Glass if (!ctlr->ichspi_lock) 417ba457562SSimon Glass ich_writew(ctlr, trans->opcode, ctlr->preop); 4181853030eSSimon Glass return 0; 4191853030eSSimon Glass } 4201853030eSSimon Glass 421ba457562SSimon Glass if (ctlr->speed && ctlr->max_speed >= 33000000) { 4221853030eSSimon Glass int byte; 4231853030eSSimon Glass 424ba457562SSimon Glass byte = ich_readb(ctlr, ctlr->speed); 425ba457562SSimon Glass if (ctlr->cur_speed >= 33000000) 4261853030eSSimon Glass byte |= SSFC_SCF_33MHZ; 4271853030eSSimon Glass else 4281853030eSSimon Glass byte &= ~SSFC_SCF_33MHZ; 429ba457562SSimon Glass ich_writeb(ctlr, byte, ctlr->speed); 4301853030eSSimon Glass } 4311853030eSSimon Glass 4321853030eSSimon Glass /* See if we have used up the command data */ 4331853030eSSimon Glass if (using_cmd && dout && bytes) { 4341853030eSSimon Glass trans->out = dout; 4351853030eSSimon Glass trans->bytesout = bytes; 436fffe25dbSSimon Glass debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); 4371853030eSSimon Glass } 4381853030eSSimon Glass 4391853030eSSimon Glass /* Preset control fields */ 440ba457562SSimon Glass control = ich_readw(ctlr, ctlr->control); 4411853030eSSimon Glass control &= ~SSFC_RESERVED; 4421853030eSSimon Glass control = SPIC_SCGO | ((opcode_index & 0x07) << 4); 4431853030eSSimon Glass 4441853030eSSimon Glass /* Issue atomic preop cycle if needed */ 445ba457562SSimon Glass if (ich_readw(ctlr, ctlr->preop)) 4461853030eSSimon Glass control |= SPIC_ACS; 4471853030eSSimon Glass 4481853030eSSimon Glass if (!trans->bytesout && !trans->bytesin) { 4491853030eSSimon Glass /* SPI addresses are 24 bit only */ 450ba457562SSimon Glass if (with_address) { 451ba457562SSimon Glass ich_writel(ctlr, trans->offset & 0x00FFFFFF, 452ba457562SSimon Glass ctlr->addr); 453ba457562SSimon Glass } 4541853030eSSimon Glass /* 4551853030eSSimon Glass * This is a 'no data' command (like Write Enable), its 4561853030eSSimon Glass * bitesout size was 1, decremented to zero while executing 4571853030eSSimon Glass * spi_setup_opcode() above. Tell the chip to send the 4581853030eSSimon Glass * command. 4591853030eSSimon Glass */ 460ba457562SSimon Glass ich_writew(ctlr, control, ctlr->control); 4611853030eSSimon Glass 4621853030eSSimon Glass /* wait for the result */ 463ba457562SSimon Glass status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 464ba457562SSimon Glass if (status < 0) 465ba457562SSimon Glass return status; 4661853030eSSimon Glass 4671853030eSSimon Glass if (status & SPIS_FCERR) { 4681853030eSSimon Glass debug("ICH SPI: Command transaction error\n"); 469ba457562SSimon Glass return -EIO; 4701853030eSSimon Glass } 4711853030eSSimon Glass 4721853030eSSimon Glass return 0; 4731853030eSSimon Glass } 4741853030eSSimon Glass 4751853030eSSimon Glass /* 4761853030eSSimon Glass * Check if this is a write command atempting to transfer more bytes 4771853030eSSimon Glass * than the controller can handle. Iterations for writes are not 4781853030eSSimon Glass * supported here because each SPI write command needs to be preceded 4791853030eSSimon Glass * and followed by other SPI commands, and this sequence is controlled 4801853030eSSimon Glass * by the SPI chip driver. 4811853030eSSimon Glass */ 482ba457562SSimon Glass if (trans->bytesout > ctlr->databytes) { 4831853030eSSimon Glass debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); 484ba457562SSimon Glass return -EPROTO; 4851853030eSSimon Glass } 4861853030eSSimon Glass 4871853030eSSimon Glass /* 4881853030eSSimon Glass * Read or write up to databytes bytes at a time until everything has 4891853030eSSimon Glass * been sent. 4901853030eSSimon Glass */ 4911853030eSSimon Glass while (trans->bytesout || trans->bytesin) { 4921853030eSSimon Glass uint32_t data_length; 4931853030eSSimon Glass 4941853030eSSimon Glass /* SPI addresses are 24 bit only */ 495ba457562SSimon Glass ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); 4961853030eSSimon Glass 4971853030eSSimon Glass if (trans->bytesout) 498ba457562SSimon Glass data_length = min(trans->bytesout, ctlr->databytes); 4991853030eSSimon Glass else 500ba457562SSimon Glass data_length = min(trans->bytesin, ctlr->databytes); 5011853030eSSimon Glass 5021853030eSSimon Glass /* Program data into FDATA0 to N */ 5031853030eSSimon Glass if (trans->bytesout) { 504ba457562SSimon Glass write_reg(ctlr, trans->out, ctlr->data, data_length); 5051853030eSSimon Glass spi_use_out(trans, data_length); 5061853030eSSimon Glass if (with_address) 5071853030eSSimon Glass trans->offset += data_length; 5081853030eSSimon Glass } 5091853030eSSimon Glass 5101853030eSSimon Glass /* Add proper control fields' values */ 511ba457562SSimon Glass control &= ~((ctlr->databytes - 1) << 8); 5121853030eSSimon Glass control |= SPIC_DS; 5131853030eSSimon Glass control |= (data_length - 1) << 8; 5141853030eSSimon Glass 5151853030eSSimon Glass /* write it */ 516ba457562SSimon Glass ich_writew(ctlr, control, ctlr->control); 5171853030eSSimon Glass 5189eb4339bSBin Meng /* Wait for Cycle Done Status or Flash Cycle Error */ 519ba457562SSimon Glass status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); 520ba457562SSimon Glass if (status < 0) 521ba457562SSimon Glass return status; 5221853030eSSimon Glass 5231853030eSSimon Glass if (status & SPIS_FCERR) { 5245d4a757cSSimon Glass debug("ICH SPI: Data transaction error %x\n", status); 525ba457562SSimon Glass return -EIO; 5261853030eSSimon Glass } 5271853030eSSimon Glass 5281853030eSSimon Glass if (trans->bytesin) { 529ba457562SSimon Glass read_reg(ctlr, ctlr->data, trans->in, data_length); 5301853030eSSimon Glass spi_use_in(trans, data_length); 5311853030eSSimon Glass if (with_address) 5321853030eSSimon Glass trans->offset += data_length; 5331853030eSSimon Glass } 5341853030eSSimon Glass } 5351853030eSSimon Glass 5361853030eSSimon Glass /* Clear atomic preop now that xfer is done */ 537ba457562SSimon Glass ich_writew(ctlr, 0, ctlr->preop); 5381853030eSSimon Glass 5391853030eSSimon Glass return 0; 5401853030eSSimon Glass } 5411853030eSSimon Glass 5421853030eSSimon Glass /* 5431853030eSSimon Glass * This uses the SPI controller from the Intel Cougar Point and Panther Point 5441853030eSSimon Glass * PCH to write-protect portions of the SPI flash until reboot. The changes 5451853030eSSimon Glass * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's 5461853030eSSimon Glass * done elsewhere. 5471853030eSSimon Glass */ 548ba457562SSimon Glass int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, 549ba457562SSimon Glass uint32_t length, int hint) 5501853030eSSimon Glass { 551ba457562SSimon Glass struct udevice *bus = dev->parent; 552ba457562SSimon Glass struct ich_spi_priv *ctlr = dev_get_priv(bus); 5531853030eSSimon Glass uint32_t tmplong; 5541853030eSSimon Glass uint32_t upper_limit; 5551853030eSSimon Glass 556ba457562SSimon Glass if (!ctlr->pr) { 5571853030eSSimon Glass printf("%s: operation not supported on this chipset\n", 5581853030eSSimon Glass __func__); 559ba457562SSimon Glass return -ENOSYS; 5601853030eSSimon Glass } 5611853030eSSimon Glass 5621853030eSSimon Glass if (length == 0 || 5631853030eSSimon Glass lower_limit > (0xFFFFFFFFUL - length) + 1 || 5641853030eSSimon Glass hint < 0 || hint > 4) { 5651853030eSSimon Glass printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, 5661853030eSSimon Glass lower_limit, length, hint); 567ba457562SSimon Glass return -EPERM; 5681853030eSSimon Glass } 5691853030eSSimon Glass 5701853030eSSimon Glass upper_limit = lower_limit + length - 1; 5711853030eSSimon Glass 5721853030eSSimon Glass /* 5731853030eSSimon Glass * Determine bits to write, as follows: 5741853030eSSimon Glass * 31 Write-protection enable (includes erase operation) 5751853030eSSimon Glass * 30:29 reserved 5761853030eSSimon Glass * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) 5771853030eSSimon Glass * 15 Read-protection enable 5781853030eSSimon Glass * 14:13 reserved 5791853030eSSimon Glass * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) 5801853030eSSimon Glass */ 5811853030eSSimon Glass tmplong = 0x80000000 | 5821853030eSSimon Glass ((upper_limit & 0x01fff000) << 4) | 5831853030eSSimon Glass ((lower_limit & 0x01fff000) >> 12); 5841853030eSSimon Glass 5851853030eSSimon Glass printf("%s: writing 0x%08x to %p\n", __func__, tmplong, 586ba457562SSimon Glass &ctlr->pr[hint]); 587ba457562SSimon Glass ctlr->pr[hint] = tmplong; 5881853030eSSimon Glass 5891853030eSSimon Glass return 0; 5901853030eSSimon Glass } 591ba457562SSimon Glass 592f2b85ab5SSimon Glass static int ich_spi_probe(struct udevice *dev) 593ba457562SSimon Glass { 594f2b85ab5SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(dev); 595f2b85ab5SSimon Glass struct ich_spi_priv *priv = dev_get_priv(dev); 596ba457562SSimon Glass uint8_t bios_cntl; 597ba457562SSimon Glass int ret; 598ba457562SSimon Glass 599f2b85ab5SSimon Glass ret = ich_init_controller(dev, plat, priv); 600ba457562SSimon Glass if (ret) 601ba457562SSimon Glass return ret; 602f2b85ab5SSimon Glass /* Disable the BIOS write protect so write commands are allowed */ 603f2b85ab5SSimon Glass ret = pch_set_spi_protect(dev->parent, false); 604f2b85ab5SSimon Glass if (ret == -ENOSYS) { 60550787928SSimon Glass bios_cntl = ich_readb(priv, priv->bcr); 60669fd4c38SJagan Teki bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ 607ba457562SSimon Glass bios_cntl |= 1; /* Write Protect Disable (WPD) */ 60850787928SSimon Glass ich_writeb(priv, bios_cntl, priv->bcr); 609f2b85ab5SSimon Glass } else if (ret) { 610f2b85ab5SSimon Glass debug("%s: Failed to disable write-protect: err=%d\n", 611f2b85ab5SSimon Glass __func__, ret); 612f2b85ab5SSimon Glass return ret; 613ba457562SSimon Glass } 614ba457562SSimon Glass 615ba457562SSimon Glass priv->cur_speed = priv->max_speed; 616ba457562SSimon Glass 617ba457562SSimon Glass return 0; 618ba457562SSimon Glass } 619ba457562SSimon Glass 620ba457562SSimon Glass static int ich_spi_set_speed(struct udevice *bus, uint speed) 621ba457562SSimon Glass { 622ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus); 623ba457562SSimon Glass 624ba457562SSimon Glass priv->cur_speed = speed; 625ba457562SSimon Glass 626ba457562SSimon Glass return 0; 627ba457562SSimon Glass } 628ba457562SSimon Glass 629ba457562SSimon Glass static int ich_spi_set_mode(struct udevice *bus, uint mode) 630ba457562SSimon Glass { 631ba457562SSimon Glass debug("%s: mode=%d\n", __func__, mode); 632ba457562SSimon Glass 633ba457562SSimon Glass return 0; 634ba457562SSimon Glass } 635ba457562SSimon Glass 636ba457562SSimon Glass static int ich_spi_child_pre_probe(struct udevice *dev) 637ba457562SSimon Glass { 638ba457562SSimon Glass struct udevice *bus = dev_get_parent(dev); 639ba457562SSimon Glass struct ich_spi_platdata *plat = dev_get_platdata(bus); 640ba457562SSimon Glass struct ich_spi_priv *priv = dev_get_priv(bus); 641bcbe3d15SSimon Glass struct spi_slave *slave = dev_get_parent_priv(dev); 642ba457562SSimon Glass 643ba457562SSimon Glass /* 644ba457562SSimon Glass * Yes this controller can only write a small number of bytes at 645ba457562SSimon Glass * once! The limit is typically 64 bytes. 646ba457562SSimon Glass */ 647ba457562SSimon Glass slave->max_write_size = priv->databytes; 648ba457562SSimon Glass /* 649ba457562SSimon Glass * ICH 7 SPI controller only supports array read command 650ba457562SSimon Glass * and byte program command for SST flash 651ba457562SSimon Glass */ 65208fe9c29SJagan Teki if (plat->ich_version == ICHV_7) 65308fe9c29SJagan Teki slave->mode = SPI_RX_SLOW | SPI_TX_BYTE; 654ba457562SSimon Glass 655ba457562SSimon Glass return 0; 656ba457562SSimon Glass } 657ba457562SSimon Glass 6581f9eb59dSBin Meng static int ich_spi_ofdata_to_platdata(struct udevice *dev) 6591f9eb59dSBin Meng { 6601f9eb59dSBin Meng struct ich_spi_platdata *plat = dev_get_platdata(dev); 661*e160f7d4SSimon Glass int node = dev_of_offset(dev); 6621f9eb59dSBin Meng int ret; 6631f9eb59dSBin Meng 664*e160f7d4SSimon Glass ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); 6651f9eb59dSBin Meng if (ret == 0) { 6666e670b5cSBin Meng plat->ich_version = ICHV_7; 6671f9eb59dSBin Meng } else { 668*e160f7d4SSimon Glass ret = fdt_node_check_compatible(gd->fdt_blob, node, 6691f9eb59dSBin Meng "intel,ich9-spi"); 6701f9eb59dSBin Meng if (ret == 0) 6716e670b5cSBin Meng plat->ich_version = ICHV_9; 6721f9eb59dSBin Meng } 6731f9eb59dSBin Meng 6741f9eb59dSBin Meng return ret; 6751f9eb59dSBin Meng } 6761f9eb59dSBin Meng 677ba457562SSimon Glass static const struct dm_spi_ops ich_spi_ops = { 678ba457562SSimon Glass .xfer = ich_spi_xfer, 679ba457562SSimon Glass .set_speed = ich_spi_set_speed, 680ba457562SSimon Glass .set_mode = ich_spi_set_mode, 681ba457562SSimon Glass /* 682ba457562SSimon Glass * cs_info is not needed, since we require all chip selects to be 683ba457562SSimon Glass * in the device tree explicitly 684ba457562SSimon Glass */ 685ba457562SSimon Glass }; 686ba457562SSimon Glass 687ba457562SSimon Glass static const struct udevice_id ich_spi_ids[] = { 6881f9eb59dSBin Meng { .compatible = "intel,ich7-spi" }, 6891f9eb59dSBin Meng { .compatible = "intel,ich9-spi" }, 690ba457562SSimon Glass { } 691ba457562SSimon Glass }; 692ba457562SSimon Glass 693ba457562SSimon Glass U_BOOT_DRIVER(ich_spi) = { 694ba457562SSimon Glass .name = "ich_spi", 695ba457562SSimon Glass .id = UCLASS_SPI, 696ba457562SSimon Glass .of_match = ich_spi_ids, 697ba457562SSimon Glass .ops = &ich_spi_ops, 6981f9eb59dSBin Meng .ofdata_to_platdata = ich_spi_ofdata_to_platdata, 699ba457562SSimon Glass .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), 700ba457562SSimon Glass .priv_auto_alloc_size = sizeof(struct ich_spi_priv), 701ba457562SSimon Glass .child_pre_probe = ich_spi_child_pre_probe, 702ba457562SSimon Glass .probe = ich_spi_probe, 703ba457562SSimon Glass }; 704