1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * Register definitions for Freescale QSPI 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _FSL_QSPI_H_ 10 #define _FSL_QSPI_H_ 11 12 struct fsl_qspi_regs { 13 u32 mcr; 14 u32 rsvd0[1]; 15 u32 ipcr; 16 u32 flshcr; 17 u32 buf0cr; 18 u32 buf1cr; 19 u32 buf2cr; 20 u32 buf3cr; 21 u32 bfgencr; 22 u32 soccr; 23 u32 rsvd1[2]; 24 u32 buf0ind; 25 u32 buf1ind; 26 u32 buf2ind; 27 u32 rsvd2[49]; 28 u32 sfar; 29 u32 rsvd3[1]; 30 u32 smpr; 31 u32 rbsr; 32 u32 rbct; 33 u32 rsvd4[15]; 34 u32 tbsr; 35 u32 tbdr; 36 u32 rsvd5[1]; 37 u32 sr; 38 u32 fr; 39 u32 rser; 40 u32 spndst; 41 u32 sptrclr; 42 u32 rsvd6[4]; 43 u32 sfa1ad; 44 u32 sfa2ad; 45 u32 sfb1ad; 46 u32 sfb2ad; 47 u32 rsvd7[28]; 48 u32 rbdr[32]; 49 u32 rsvd8[32]; 50 u32 lutkey; 51 u32 lckcr; 52 u32 rsvd9[2]; 53 u32 lut[64]; 54 }; 55 56 #define QSPI_IPCR_SEQID_SHIFT 24 57 #define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT) 58 59 #define QSPI_MCR_END_CFD_SHIFT 2 60 #define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT) 61 #define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT) 62 #define QSPI_MCR_DDR_EN_SHIFT 7 63 #define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT) 64 #define QSPI_MCR_CLR_RXF_SHIFT 10 65 #define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT) 66 #define QSPI_MCR_CLR_TXF_SHIFT 11 67 #define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT) 68 #define QSPI_MCR_MDIS_SHIFT 14 69 #define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT) 70 #define QSPI_MCR_RESERVED_SHIFT 16 71 #define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT) 72 73 #define QSPI_SMPR_HSENA_SHIFT 0 74 #define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT) 75 #define QSPI_SMPR_FSPHS_SHIFT 5 76 #define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT) 77 #define QSPI_SMPR_FSDLY_SHIFT 6 78 #define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT) 79 #define QSPI_SMPR_DDRSMP_SHIFT 16 80 #define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT) 81 82 #define QSPI_BFGENCR_SEQID_SHIFT 12 83 #define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT) 84 #define QSPI_BFGENCR_PAR_EN_SHIFT 16 85 #define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT) 86 87 #define QSPI_RBSR_RDBFL_SHIFT 8 88 #define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT) 89 90 #define QSPI_RBCT_RXBRD_SHIFT 8 91 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT) 92 93 #define QSPI_SR_BUSY_SHIFT 0 94 #define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT) 95 96 #define QSPI_LCKCR_LOCK 0x1 97 #define QSPI_LCKCR_UNLOCK 0x2 98 99 #define LUT_KEY_VALUE 0x5af05af0 100 101 #define OPRND0_SHIFT 0 102 #define OPRND0(x) ((x) << OPRND0_SHIFT) 103 #define PAD0_SHIFT 8 104 #define PAD0(x) ((x) << PAD0_SHIFT) 105 #define INSTR0_SHIFT 10 106 #define INSTR0(x) ((x) << INSTR0_SHIFT) 107 #define OPRND1_SHIFT 16 108 #define OPRND1(x) ((x) << OPRND1_SHIFT) 109 #define PAD1_SHIFT 24 110 #define PAD1(x) ((x) << PAD1_SHIFT) 111 #define INSTR1_SHIFT 26 112 #define INSTR1(x) ((x) << INSTR1_SHIFT) 113 114 #define LUT_CMD 1 115 #define LUT_ADDR 2 116 #define LUT_DUMMY 3 117 #define LUT_READ 7 118 #define LUT_WRITE 8 119 120 #define LUT_PAD1 0 121 #define LUT_PAD2 1 122 #define LUT_PAD4 2 123 124 #define ADDR24BIT 0x18 125 #define ADDR32BIT 0x20 126 127 #endif /* _FSL_QSPI_H_ */ 128