1 /* 2 * Copyright 2013-2015 Freescale Semiconductor, Inc. 3 * 4 * Freescale Quad Serial Peripheral Interface (QSPI) driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <spi.h> 12 #include <asm/io.h> 13 #include <linux/sizes.h> 14 #include <dm.h> 15 #include <errno.h> 16 #include <watchdog.h> 17 #include <wait_bit.h> 18 #include "fsl_qspi.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define RX_BUFFER_SIZE 0x80 23 #ifdef CONFIG_MX6SX 24 #define TX_BUFFER_SIZE 0x200 25 #else 26 #define TX_BUFFER_SIZE 0x40 27 #endif 28 29 #define OFFSET_BITS_MASK GENMASK(23, 0) 30 31 #define FLASH_STATUS_WEL 0x02 32 33 /* SEQID */ 34 #define SEQID_WREN 1 35 #define SEQID_FAST_READ 2 36 #define SEQID_RDSR 3 37 #define SEQID_SE 4 38 #define SEQID_CHIP_ERASE 5 39 #define SEQID_PP 6 40 #define SEQID_RDID 7 41 #define SEQID_BE_4K 8 42 #ifdef CONFIG_SPI_FLASH_BAR 43 #define SEQID_BRRD 9 44 #define SEQID_BRWR 10 45 #define SEQID_RDEAR 11 46 #define SEQID_WREAR 12 47 #endif 48 #define SEQID_WRAR 13 49 #define SEQID_RDAR 14 50 51 /* QSPI CMD */ 52 #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ 53 #define QSPI_CMD_RDSR 0x05 /* Read status register */ 54 #define QSPI_CMD_WREN 0x06 /* Write enable */ 55 #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ 56 #define QSPI_CMD_BE_4K 0x20 /* 4K erase */ 57 #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 58 #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ 59 #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ 60 61 /* Used for Micron, winbond and Macronix flashes */ 62 #define QSPI_CMD_WREAR 0xc5 /* EAR register write */ 63 #define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */ 64 65 /* Used for Spansion flashes only. */ 66 #define QSPI_CMD_BRRD 0x16 /* Bank register read */ 67 #define QSPI_CMD_BRWR 0x17 /* Bank register write */ 68 69 /* Used for Spansion S25FS-S family flash only. */ 70 #define QSPI_CMD_RDAR 0x65 /* Read any device register */ 71 #define QSPI_CMD_WRAR 0x71 /* Write any device register */ 72 73 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ 74 #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ 75 #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ 76 #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 77 78 /* fsl_qspi_platdata flags */ 79 #define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) 80 81 /* default SCK frequency, unit: HZ */ 82 #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 83 84 /* QSPI max chipselect signals number */ 85 #define FSL_QSPI_MAX_CHIPSELECT_NUM 4 86 87 #ifdef CONFIG_DM_SPI 88 /** 89 * struct fsl_qspi_platdata - platform data for Freescale QSPI 90 * 91 * @flags: Flags for QSPI QSPI_FLAG_... 92 * @speed_hz: Default SCK frequency 93 * @reg_base: Base address of QSPI registers 94 * @amba_base: Base address of QSPI memory mapping 95 * @amba_total_size: size of QSPI memory mapping 96 * @flash_num: Number of active slave devices 97 * @num_chipselect: Number of QSPI chipselect signals 98 */ 99 struct fsl_qspi_platdata { 100 u32 flags; 101 u32 speed_hz; 102 fdt_addr_t reg_base; 103 fdt_addr_t amba_base; 104 fdt_size_t amba_total_size; 105 u32 flash_num; 106 u32 num_chipselect; 107 }; 108 #endif 109 110 /** 111 * struct fsl_qspi_priv - private data for Freescale QSPI 112 * 113 * @flags: Flags for QSPI QSPI_FLAG_... 114 * @bus_clk: QSPI input clk frequency 115 * @speed_hz: Default SCK frequency 116 * @cur_seqid: current LUT table sequence id 117 * @sf_addr: flash access offset 118 * @amba_base: Base address of QSPI memory mapping of every CS 119 * @amba_total_size: size of QSPI memory mapping 120 * @cur_amba_base: Base address of QSPI memory mapping of current CS 121 * @flash_num: Number of active slave devices 122 * @num_chipselect: Number of QSPI chipselect signals 123 * @regs: Point to QSPI register structure for I/O access 124 */ 125 struct fsl_qspi_priv { 126 u32 flags; 127 u32 bus_clk; 128 u32 speed_hz; 129 u32 cur_seqid; 130 u32 sf_addr; 131 u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM]; 132 u32 amba_total_size; 133 u32 cur_amba_base; 134 u32 flash_num; 135 u32 num_chipselect; 136 struct fsl_qspi_regs *regs; 137 }; 138 139 #ifndef CONFIG_DM_SPI 140 struct fsl_qspi { 141 struct spi_slave slave; 142 struct fsl_qspi_priv priv; 143 }; 144 #endif 145 146 static u32 qspi_read32(u32 flags, u32 *addr) 147 { 148 return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? 149 in_be32(addr) : in_le32(addr); 150 } 151 152 static void qspi_write32(u32 flags, u32 *addr, u32 val) 153 { 154 flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? 155 out_be32(addr, val) : out_le32(addr, val); 156 } 157 158 /* QSPI support swapping the flash read/write data 159 * in hardware for LS102xA, but not for VF610 */ 160 static inline u32 qspi_endian_xchg(u32 data) 161 { 162 #ifdef CONFIG_VF610 163 return swab32(data); 164 #else 165 return data; 166 #endif 167 } 168 169 static void qspi_set_lut(struct fsl_qspi_priv *priv) 170 { 171 struct fsl_qspi_regs *regs = priv->regs; 172 u32 lut_base; 173 174 /* Unlock the LUT */ 175 qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); 176 qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_UNLOCK); 177 178 /* Write Enable */ 179 lut_base = SEQID_WREN * 4; 180 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | 181 PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); 182 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); 183 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 184 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 185 186 /* Fast Read */ 187 lut_base = SEQID_FAST_READ * 4; 188 #ifdef CONFIG_SPI_FLASH_BAR 189 qspi_write32(priv->flags, ®s->lut[lut_base], 190 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | 191 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 192 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 193 #else 194 if (FSL_QSPI_FLASH_SIZE <= SZ_16M) 195 qspi_write32(priv->flags, ®s->lut[lut_base], 196 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | 197 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 198 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 199 else 200 qspi_write32(priv->flags, ®s->lut[lut_base], 201 OPRND0(QSPI_CMD_FAST_READ_4B) | 202 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | 203 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | 204 INSTR1(LUT_ADDR)); 205 #endif 206 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 207 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | 208 OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | 209 INSTR1(LUT_READ)); 210 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 211 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 212 213 /* Read Status */ 214 lut_base = SEQID_RDSR * 4; 215 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | 216 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | 217 PAD1(LUT_PAD1) | INSTR1(LUT_READ)); 218 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); 219 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 220 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 221 222 /* Erase a sector */ 223 lut_base = SEQID_SE * 4; 224 #ifdef CONFIG_SPI_FLASH_BAR 225 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | 226 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 227 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 228 #else 229 if (FSL_QSPI_FLASH_SIZE <= SZ_16M) 230 qspi_write32(priv->flags, ®s->lut[lut_base], 231 OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | 232 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 233 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 234 else 235 qspi_write32(priv->flags, ®s->lut[lut_base], 236 OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | 237 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | 238 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 239 #endif 240 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); 241 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 242 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 243 244 /* Erase the whole chip */ 245 lut_base = SEQID_CHIP_ERASE * 4; 246 qspi_write32(priv->flags, ®s->lut[lut_base], 247 OPRND0(QSPI_CMD_CHIP_ERASE) | 248 PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); 249 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); 250 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 251 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 252 253 /* Page Program */ 254 lut_base = SEQID_PP * 4; 255 #ifdef CONFIG_SPI_FLASH_BAR 256 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | 257 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 258 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 259 #else 260 if (FSL_QSPI_FLASH_SIZE <= SZ_16M) 261 qspi_write32(priv->flags, ®s->lut[lut_base], 262 OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | 263 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 264 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 265 else 266 qspi_write32(priv->flags, ®s->lut[lut_base], 267 OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | 268 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | 269 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 270 #endif 271 #ifdef CONFIG_MX6SX 272 /* 273 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. 274 * So, Use IDATSZ in IPCR to determine the size and here set 0. 275 */ 276 qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) | 277 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); 278 #else 279 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 280 OPRND0(TX_BUFFER_SIZE) | 281 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); 282 #endif 283 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 284 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 285 286 /* READ ID */ 287 lut_base = SEQID_RDID * 4; 288 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) | 289 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | 290 PAD1(LUT_PAD1) | INSTR1(LUT_READ)); 291 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); 292 qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); 293 qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); 294 295 /* SUB SECTOR 4K ERASE */ 296 lut_base = SEQID_BE_4K * 4; 297 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | 298 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 299 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 300 301 #ifdef CONFIG_SPI_FLASH_BAR 302 /* 303 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to 304 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during 305 * initialization. 306 */ 307 lut_base = SEQID_BRRD * 4; 308 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | 309 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | 310 PAD1(LUT_PAD1) | INSTR1(LUT_READ)); 311 312 lut_base = SEQID_BRWR * 4; 313 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | 314 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | 315 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); 316 317 lut_base = SEQID_RDEAR * 4; 318 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | 319 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | 320 PAD1(LUT_PAD1) | INSTR1(LUT_READ)); 321 322 lut_base = SEQID_WREAR * 4; 323 qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | 324 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | 325 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); 326 #endif 327 328 /* 329 * Read any device register. 330 * Used for Spansion S25FS-S family flash only. 331 */ 332 lut_base = SEQID_RDAR * 4; 333 qspi_write32(priv->flags, ®s->lut[lut_base], 334 OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) | 335 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 336 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 337 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 338 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | 339 OPRND1(1) | PAD1(LUT_PAD1) | 340 INSTR1(LUT_READ)); 341 342 /* 343 * Write any device register. 344 * Used for Spansion S25FS-S family flash only. 345 */ 346 lut_base = SEQID_WRAR * 4; 347 qspi_write32(priv->flags, ®s->lut[lut_base], 348 OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) | 349 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | 350 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); 351 qspi_write32(priv->flags, ®s->lut[lut_base + 1], 352 OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); 353 354 /* Lock the LUT */ 355 qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); 356 qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK); 357 } 358 359 #if defined(CONFIG_SYS_FSL_QSPI_AHB) 360 /* 361 * If we have changed the content of the flash by writing or erasing, 362 * we need to invalidate the AHB buffer. If we do not do so, we may read out 363 * the wrong data. The spec tells us reset the AHB domain and Serial Flash 364 * domain at the same time. 365 */ 366 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv) 367 { 368 struct fsl_qspi_regs *regs = priv->regs; 369 u32 reg; 370 371 reg = qspi_read32(priv->flags, ®s->mcr); 372 reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK; 373 qspi_write32(priv->flags, ®s->mcr, reg); 374 375 /* 376 * The minimum delay : 1 AHB + 2 SFCK clocks. 377 * Delay 1 us is enough. 378 */ 379 udelay(1); 380 381 reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK); 382 qspi_write32(priv->flags, ®s->mcr, reg); 383 } 384 385 /* Read out the data from the AHB buffer. */ 386 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) 387 { 388 struct fsl_qspi_regs *regs = priv->regs; 389 u32 mcr_reg; 390 void *rx_addr = NULL; 391 392 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 393 394 qspi_write32(priv->flags, ®s->mcr, 395 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 396 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 397 398 rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); 399 /* Read out the data directly from the AHB buffer. */ 400 memcpy(rxbuf, rx_addr, len); 401 402 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 403 } 404 405 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) 406 { 407 u32 reg, reg2; 408 struct fsl_qspi_regs *regs = priv->regs; 409 410 reg = qspi_read32(priv->flags, ®s->mcr); 411 /* Disable the module */ 412 qspi_write32(priv->flags, ®s->mcr, reg | QSPI_MCR_MDIS_MASK); 413 414 /* Set the Sampling Register for DDR */ 415 reg2 = qspi_read32(priv->flags, ®s->smpr); 416 reg2 &= ~QSPI_SMPR_DDRSMP_MASK; 417 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); 418 qspi_write32(priv->flags, ®s->smpr, reg2); 419 420 /* Enable the module again (enable the DDR too) */ 421 reg |= QSPI_MCR_DDR_EN_MASK; 422 /* Enable bit 29 for imx6sx */ 423 reg |= BIT(29); 424 425 qspi_write32(priv->flags, ®s->mcr, reg); 426 } 427 428 /* 429 * There are two different ways to read out the data from the flash: 430 * the "IP Command Read" and the "AHB Command Read". 431 * 432 * The IC guy suggests we use the "AHB Command Read" which is faster 433 * then the "IP Command Read". (What's more is that there is a bug in 434 * the "IP Command Read" in the Vybrid.) 435 * 436 * After we set up the registers for the "AHB Command Read", we can use 437 * the memcpy to read the data directly. A "missed" access to the buffer 438 * causes the controller to clear the buffer, and use the sequence pointed 439 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash. 440 */ 441 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) 442 { 443 struct fsl_qspi_regs *regs = priv->regs; 444 445 /* AHB configuration for access buffer 0/1/2 .*/ 446 qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); 447 qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); 448 qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); 449 qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | 450 (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); 451 452 /* We only use the buffer3 */ 453 qspi_write32(priv->flags, ®s->buf0ind, 0); 454 qspi_write32(priv->flags, ®s->buf1ind, 0); 455 qspi_write32(priv->flags, ®s->buf2ind, 0); 456 457 /* 458 * Set the default lut sequence for AHB Read. 459 * Parallel mode is disabled. 460 */ 461 qspi_write32(priv->flags, ®s->bfgencr, 462 SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); 463 464 /*Enable DDR Mode*/ 465 qspi_enable_ddr_mode(priv); 466 } 467 #endif 468 469 #ifdef CONFIG_SPI_FLASH_BAR 470 /* Bank register read/write, EAR register read/write */ 471 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) 472 { 473 struct fsl_qspi_regs *regs = priv->regs; 474 u32 reg, mcr_reg, data, seqid; 475 476 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 477 qspi_write32(priv->flags, ®s->mcr, 478 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 479 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 480 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 481 482 qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); 483 484 if (priv->cur_seqid == QSPI_CMD_BRRD) 485 seqid = SEQID_BRRD; 486 else 487 seqid = SEQID_RDEAR; 488 489 qspi_write32(priv->flags, ®s->ipcr, 490 (seqid << QSPI_IPCR_SEQID_SHIFT) | len); 491 492 /* Wait previous command complete */ 493 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 494 ; 495 496 while (1) { 497 WATCHDOG_RESET(); 498 499 reg = qspi_read32(priv->flags, ®s->rbsr); 500 if (reg & QSPI_RBSR_RDBFL_MASK) { 501 data = qspi_read32(priv->flags, ®s->rbdr[0]); 502 data = qspi_endian_xchg(data); 503 memcpy(rxbuf, &data, len); 504 qspi_write32(priv->flags, ®s->mcr, 505 qspi_read32(priv->flags, ®s->mcr) | 506 QSPI_MCR_CLR_RXF_MASK); 507 break; 508 } 509 } 510 511 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 512 } 513 #endif 514 515 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) 516 { 517 struct fsl_qspi_regs *regs = priv->regs; 518 u32 mcr_reg, rbsr_reg, data, size; 519 int i; 520 521 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 522 qspi_write32(priv->flags, ®s->mcr, 523 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 524 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 525 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 526 527 qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); 528 529 qspi_write32(priv->flags, ®s->ipcr, 530 (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); 531 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 532 ; 533 534 i = 0; 535 while ((RX_BUFFER_SIZE >= len) && (len > 0)) { 536 WATCHDOG_RESET(); 537 538 rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); 539 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { 540 data = qspi_read32(priv->flags, ®s->rbdr[i]); 541 data = qspi_endian_xchg(data); 542 size = (len < 4) ? len : 4; 543 memcpy(rxbuf, &data, size); 544 len -= size; 545 rxbuf++; 546 i++; 547 } 548 } 549 550 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 551 } 552 553 /* If not use AHB read, read data from ip interface */ 554 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) 555 { 556 struct fsl_qspi_regs *regs = priv->regs; 557 u32 mcr_reg, data; 558 int i, size; 559 u32 to_or_from; 560 u32 seqid; 561 562 if (priv->cur_seqid == QSPI_CMD_RDAR) 563 seqid = SEQID_RDAR; 564 else 565 seqid = SEQID_FAST_READ; 566 567 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 568 qspi_write32(priv->flags, ®s->mcr, 569 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 570 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 571 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 572 573 to_or_from = priv->sf_addr + priv->cur_amba_base; 574 575 while (len > 0) { 576 WATCHDOG_RESET(); 577 578 qspi_write32(priv->flags, ®s->sfar, to_or_from); 579 580 size = (len > RX_BUFFER_SIZE) ? 581 RX_BUFFER_SIZE : len; 582 583 qspi_write32(priv->flags, ®s->ipcr, 584 (seqid << QSPI_IPCR_SEQID_SHIFT) | 585 size); 586 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 587 ; 588 589 to_or_from += size; 590 len -= size; 591 592 i = 0; 593 while ((RX_BUFFER_SIZE >= size) && (size > 0)) { 594 data = qspi_read32(priv->flags, ®s->rbdr[i]); 595 data = qspi_endian_xchg(data); 596 if (size < 4) 597 memcpy(rxbuf, &data, size); 598 else 599 memcpy(rxbuf, &data, 4); 600 rxbuf++; 601 size -= 4; 602 i++; 603 } 604 qspi_write32(priv->flags, ®s->mcr, 605 qspi_read32(priv->flags, ®s->mcr) | 606 QSPI_MCR_CLR_RXF_MASK); 607 } 608 609 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 610 } 611 612 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) 613 { 614 struct fsl_qspi_regs *regs = priv->regs; 615 u32 mcr_reg, data, reg, status_reg, seqid; 616 int i, size, tx_size; 617 u32 to_or_from = 0; 618 619 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 620 qspi_write32(priv->flags, ®s->mcr, 621 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 622 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 623 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 624 625 status_reg = 0; 626 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { 627 WATCHDOG_RESET(); 628 629 qspi_write32(priv->flags, ®s->ipcr, 630 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); 631 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 632 ; 633 634 qspi_write32(priv->flags, ®s->ipcr, 635 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); 636 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 637 ; 638 639 reg = qspi_read32(priv->flags, ®s->rbsr); 640 if (reg & QSPI_RBSR_RDBFL_MASK) { 641 status_reg = qspi_read32(priv->flags, ®s->rbdr[0]); 642 status_reg = qspi_endian_xchg(status_reg); 643 } 644 qspi_write32(priv->flags, ®s->mcr, 645 qspi_read32(priv->flags, ®s->mcr) | 646 QSPI_MCR_CLR_RXF_MASK); 647 } 648 649 /* Default is page programming */ 650 seqid = SEQID_PP; 651 if (priv->cur_seqid == QSPI_CMD_WRAR) 652 seqid = SEQID_WRAR; 653 #ifdef CONFIG_SPI_FLASH_BAR 654 if (priv->cur_seqid == QSPI_CMD_BRWR) 655 seqid = SEQID_BRWR; 656 else if (priv->cur_seqid == QSPI_CMD_WREAR) 657 seqid = SEQID_WREAR; 658 #endif 659 660 to_or_from = priv->sf_addr + priv->cur_amba_base; 661 662 qspi_write32(priv->flags, ®s->sfar, to_or_from); 663 664 tx_size = (len > TX_BUFFER_SIZE) ? 665 TX_BUFFER_SIZE : len; 666 667 size = tx_size / 16; 668 /* 669 * There must be atleast 128bit data 670 * available in TX FIFO for any pop operation 671 */ 672 if (tx_size % 16) 673 size++; 674 for (i = 0; i < size * 4; i++) { 675 memcpy(&data, txbuf, 4); 676 data = qspi_endian_xchg(data); 677 qspi_write32(priv->flags, ®s->tbdr, data); 678 txbuf += 4; 679 } 680 681 qspi_write32(priv->flags, ®s->ipcr, 682 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); 683 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 684 ; 685 686 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 687 } 688 689 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) 690 { 691 struct fsl_qspi_regs *regs = priv->regs; 692 u32 mcr_reg, reg, data; 693 694 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 695 qspi_write32(priv->flags, ®s->mcr, 696 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 697 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 698 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 699 700 qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); 701 702 qspi_write32(priv->flags, ®s->ipcr, 703 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); 704 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 705 ; 706 707 while (1) { 708 WATCHDOG_RESET(); 709 710 reg = qspi_read32(priv->flags, ®s->rbsr); 711 if (reg & QSPI_RBSR_RDBFL_MASK) { 712 data = qspi_read32(priv->flags, ®s->rbdr[0]); 713 data = qspi_endian_xchg(data); 714 memcpy(rxbuf, &data, len); 715 qspi_write32(priv->flags, ®s->mcr, 716 qspi_read32(priv->flags, ®s->mcr) | 717 QSPI_MCR_CLR_RXF_MASK); 718 break; 719 } 720 } 721 722 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 723 } 724 725 static void qspi_op_erase(struct fsl_qspi_priv *priv) 726 { 727 struct fsl_qspi_regs *regs = priv->regs; 728 u32 mcr_reg; 729 u32 to_or_from = 0; 730 731 mcr_reg = qspi_read32(priv->flags, ®s->mcr); 732 qspi_write32(priv->flags, ®s->mcr, 733 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | 734 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); 735 qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); 736 737 to_or_from = priv->sf_addr + priv->cur_amba_base; 738 qspi_write32(priv->flags, ®s->sfar, to_or_from); 739 740 qspi_write32(priv->flags, ®s->ipcr, 741 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); 742 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 743 ; 744 745 if (priv->cur_seqid == QSPI_CMD_SE) { 746 qspi_write32(priv->flags, ®s->ipcr, 747 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); 748 } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { 749 qspi_write32(priv->flags, ®s->ipcr, 750 (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); 751 } 752 while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) 753 ; 754 755 qspi_write32(priv->flags, ®s->mcr, mcr_reg); 756 } 757 758 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, 759 const void *dout, void *din, unsigned long flags) 760 { 761 u32 bytes = DIV_ROUND_UP(bitlen, 8); 762 static u32 wr_sfaddr; 763 u32 txbuf; 764 765 WATCHDOG_RESET(); 766 767 if (dout) { 768 if (flags & SPI_XFER_BEGIN) { 769 priv->cur_seqid = *(u8 *)dout; 770 memcpy(&txbuf, dout, 4); 771 } 772 773 if (flags == SPI_XFER_END) { 774 priv->sf_addr = wr_sfaddr; 775 qspi_op_write(priv, (u8 *)dout, bytes); 776 return 0; 777 } 778 779 if (priv->cur_seqid == QSPI_CMD_FAST_READ || 780 priv->cur_seqid == QSPI_CMD_RDAR) { 781 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; 782 } else if ((priv->cur_seqid == QSPI_CMD_SE) || 783 (priv->cur_seqid == QSPI_CMD_BE_4K)) { 784 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; 785 qspi_op_erase(priv); 786 } else if (priv->cur_seqid == QSPI_CMD_PP || 787 priv->cur_seqid == QSPI_CMD_WRAR) { 788 wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; 789 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) || 790 (priv->cur_seqid == QSPI_CMD_WREAR)) { 791 #ifdef CONFIG_SPI_FLASH_BAR 792 wr_sfaddr = 0; 793 #endif 794 } 795 } 796 797 if (din) { 798 if (priv->cur_seqid == QSPI_CMD_FAST_READ) { 799 #ifdef CONFIG_SYS_FSL_QSPI_AHB 800 qspi_ahb_read(priv, din, bytes); 801 #else 802 qspi_op_read(priv, din, bytes); 803 #endif 804 } else if (priv->cur_seqid == QSPI_CMD_RDAR) { 805 qspi_op_read(priv, din, bytes); 806 } else if (priv->cur_seqid == QSPI_CMD_RDID) 807 qspi_op_rdid(priv, din, bytes); 808 else if (priv->cur_seqid == QSPI_CMD_RDSR) 809 qspi_op_rdsr(priv, din, bytes); 810 #ifdef CONFIG_SPI_FLASH_BAR 811 else if ((priv->cur_seqid == QSPI_CMD_BRRD) || 812 (priv->cur_seqid == QSPI_CMD_RDEAR)) { 813 priv->sf_addr = 0; 814 qspi_op_rdbank(priv, din, bytes); 815 } 816 #endif 817 } 818 819 #ifdef CONFIG_SYS_FSL_QSPI_AHB 820 if ((priv->cur_seqid == QSPI_CMD_SE) || 821 (priv->cur_seqid == QSPI_CMD_PP) || 822 (priv->cur_seqid == QSPI_CMD_BE_4K) || 823 (priv->cur_seqid == QSPI_CMD_WREAR) || 824 (priv->cur_seqid == QSPI_CMD_BRWR)) 825 qspi_ahb_invalid(priv); 826 #endif 827 828 return 0; 829 } 830 831 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable) 832 { 833 u32 mcr_val; 834 835 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); 836 if (disable) 837 mcr_val |= QSPI_MCR_MDIS_MASK; 838 else 839 mcr_val &= ~QSPI_MCR_MDIS_MASK; 840 qspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 841 } 842 843 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) 844 { 845 u32 smpr_val; 846 847 smpr_val = qspi_read32(priv->flags, &priv->regs->smpr); 848 smpr_val &= ~clear_bits; 849 smpr_val |= set_bits; 850 qspi_write32(priv->flags, &priv->regs->smpr, smpr_val); 851 } 852 #ifndef CONFIG_DM_SPI 853 static unsigned long spi_bases[] = { 854 QSPI0_BASE_ADDR, 855 #ifdef CONFIG_MX6SX 856 QSPI1_BASE_ADDR, 857 #endif 858 }; 859 860 static unsigned long amba_bases[] = { 861 QSPI0_AMBA_BASE, 862 #ifdef CONFIG_MX6SX 863 QSPI1_AMBA_BASE, 864 #endif 865 }; 866 867 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) 868 { 869 return container_of(slave, struct fsl_qspi, slave); 870 } 871 872 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 873 unsigned int max_hz, unsigned int mode) 874 { 875 u32 mcr_val; 876 struct fsl_qspi *qspi; 877 struct fsl_qspi_regs *regs; 878 u32 total_size; 879 880 if (bus >= ARRAY_SIZE(spi_bases)) 881 return NULL; 882 883 if (cs >= FSL_QSPI_FLASH_NUM) 884 return NULL; 885 886 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); 887 if (!qspi) 888 return NULL; 889 890 #ifdef CONFIG_SYS_FSL_QSPI_BE 891 qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; 892 #endif 893 894 regs = (struct fsl_qspi_regs *)spi_bases[bus]; 895 qspi->priv.regs = regs; 896 /* 897 * According cs, use different amba_base to choose the 898 * corresponding flash devices. 899 * 900 * If not, only one flash device is used even if passing 901 * different cs using `sf probe` 902 */ 903 qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; 904 905 qspi->slave.max_write_size = TX_BUFFER_SIZE; 906 907 mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); 908 qspi_write32(qspi->priv.flags, ®s->mcr, 909 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | 910 (mcr_val & QSPI_MCR_END_CFD_MASK)); 911 912 qspi_cfg_smpr(&qspi->priv, 913 ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | 914 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); 915 916 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; 917 /* 918 * Any read access to non-implemented addresses will provide 919 * undefined results. 920 * 921 * In case single die flash devices, TOP_ADDR_MEMA2 and 922 * TOP_ADDR_MEMB2 should be initialized/programmed to 923 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, 924 * setting the size of these devices to 0. This would ensure 925 * that the complete memory map is assigned to only one flash device. 926 */ 927 qspi_write32(qspi->priv.flags, ®s->sfa1ad, 928 FSL_QSPI_FLASH_SIZE | amba_bases[bus]); 929 qspi_write32(qspi->priv.flags, ®s->sfa2ad, 930 FSL_QSPI_FLASH_SIZE | amba_bases[bus]); 931 qspi_write32(qspi->priv.flags, ®s->sfb1ad, 932 total_size | amba_bases[bus]); 933 qspi_write32(qspi->priv.flags, ®s->sfb2ad, 934 total_size | amba_bases[bus]); 935 936 qspi_set_lut(&qspi->priv); 937 938 #ifdef CONFIG_SYS_FSL_QSPI_AHB 939 qspi_init_ahb_read(&qspi->priv); 940 #endif 941 942 qspi_module_disable(&qspi->priv, 0); 943 944 return &qspi->slave; 945 } 946 947 void spi_free_slave(struct spi_slave *slave) 948 { 949 struct fsl_qspi *qspi = to_qspi_spi(slave); 950 951 free(qspi); 952 } 953 954 int spi_claim_bus(struct spi_slave *slave) 955 { 956 return 0; 957 } 958 959 void spi_release_bus(struct spi_slave *slave) 960 { 961 /* Nothing to do */ 962 } 963 964 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 965 const void *dout, void *din, unsigned long flags) 966 { 967 struct fsl_qspi *qspi = to_qspi_spi(slave); 968 969 return qspi_xfer(&qspi->priv, bitlen, dout, din, flags); 970 } 971 972 void spi_init(void) 973 { 974 /* Nothing to do */ 975 } 976 #else 977 static int fsl_qspi_child_pre_probe(struct udevice *dev) 978 { 979 struct spi_slave *slave = dev_get_parent_priv(dev); 980 981 slave->max_write_size = TX_BUFFER_SIZE; 982 983 return 0; 984 } 985 986 static int fsl_qspi_probe(struct udevice *bus) 987 { 988 u32 mcr_val; 989 u32 amba_size_per_chip; 990 struct fsl_qspi_platdata *plat = dev_get_platdata(bus); 991 struct fsl_qspi_priv *priv = dev_get_priv(bus); 992 struct dm_spi_bus *dm_spi_bus; 993 int i, ret; 994 995 dm_spi_bus = bus->uclass_priv; 996 997 dm_spi_bus->max_hz = plat->speed_hz; 998 999 priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; 1000 priv->flags = plat->flags; 1001 1002 priv->speed_hz = plat->speed_hz; 1003 /* 1004 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1. 1005 * AMBA memory zone should be located on the 0~4GB space 1006 * even on a 64bits cpu. 1007 */ 1008 priv->amba_base[0] = (u32)plat->amba_base; 1009 priv->amba_total_size = (u32)plat->amba_total_size; 1010 priv->flash_num = plat->flash_num; 1011 priv->num_chipselect = plat->num_chipselect; 1012 1013 /* make sure controller is not busy anywhere */ 1014 ret = wait_for_bit(__func__, &priv->regs->sr, 1015 QSPI_SR_BUSY_MASK | 1016 QSPI_SR_AHB_ACC_MASK | 1017 QSPI_SR_IP_ACC_MASK, 1018 false, 100, false); 1019 1020 if (ret) { 1021 debug("ERROR : The controller is busy\n"); 1022 return ret; 1023 } 1024 1025 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); 1026 qspi_write32(priv->flags, &priv->regs->mcr, 1027 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | 1028 (mcr_val & QSPI_MCR_END_CFD_MASK)); 1029 1030 qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | 1031 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); 1032 1033 /* 1034 * Assign AMBA memory zone for every chipselect 1035 * QuadSPI has two channels, every channel has two chipselects. 1036 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided 1037 * into two parts and assign to every channel. This indicate that every 1038 * channel only has one valid chipselect. 1039 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided 1040 * into four parts and assign to every chipselect. 1041 * Every channel will has two valid chipselects. 1042 */ 1043 amba_size_per_chip = priv->amba_total_size >> 1044 (priv->num_chipselect >> 1); 1045 for (i = 1 ; i < priv->num_chipselect ; i++) 1046 priv->amba_base[i] = 1047 amba_size_per_chip + priv->amba_base[i - 1]; 1048 1049 /* 1050 * Any read access to non-implemented addresses will provide 1051 * undefined results. 1052 * 1053 * In case single die flash devices, TOP_ADDR_MEMA2 and 1054 * TOP_ADDR_MEMB2 should be initialized/programmed to 1055 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, 1056 * setting the size of these devices to 0. This would ensure 1057 * that the complete memory map is assigned to only one flash device. 1058 */ 1059 qspi_write32(priv->flags, &priv->regs->sfa1ad, 1060 priv->amba_base[0] + amba_size_per_chip); 1061 switch (priv->num_chipselect) { 1062 case 1: 1063 break; 1064 case 2: 1065 qspi_write32(priv->flags, &priv->regs->sfa2ad, 1066 priv->amba_base[1]); 1067 qspi_write32(priv->flags, &priv->regs->sfb1ad, 1068 priv->amba_base[1] + amba_size_per_chip); 1069 qspi_write32(priv->flags, &priv->regs->sfb2ad, 1070 priv->amba_base[1] + amba_size_per_chip); 1071 break; 1072 case 4: 1073 qspi_write32(priv->flags, &priv->regs->sfa2ad, 1074 priv->amba_base[2]); 1075 qspi_write32(priv->flags, &priv->regs->sfb1ad, 1076 priv->amba_base[3]); 1077 qspi_write32(priv->flags, &priv->regs->sfb2ad, 1078 priv->amba_base[3] + amba_size_per_chip); 1079 break; 1080 default: 1081 debug("Error: Unsupported chipselect number %u!\n", 1082 priv->num_chipselect); 1083 qspi_module_disable(priv, 1); 1084 return -EINVAL; 1085 } 1086 1087 qspi_set_lut(priv); 1088 1089 #ifdef CONFIG_SYS_FSL_QSPI_AHB 1090 qspi_init_ahb_read(priv); 1091 #endif 1092 1093 qspi_module_disable(priv, 0); 1094 1095 return 0; 1096 } 1097 1098 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) 1099 { 1100 struct fdt_resource res_regs, res_mem; 1101 struct fsl_qspi_platdata *plat = bus->platdata; 1102 const void *blob = gd->fdt_blob; 1103 int node = dev_of_offset(bus); 1104 int ret, flash_num = 0, subnode; 1105 1106 if (fdtdec_get_bool(blob, node, "big-endian")) 1107 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; 1108 1109 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 1110 "QuadSPI", &res_regs); 1111 if (ret) { 1112 debug("Error: can't get regs base addresses(ret = %d)!\n", ret); 1113 return -ENOMEM; 1114 } 1115 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 1116 "QuadSPI-memory", &res_mem); 1117 if (ret) { 1118 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret); 1119 return -ENOMEM; 1120 } 1121 1122 /* Count flash numbers */ 1123 fdt_for_each_subnode(subnode, blob, node) 1124 ++flash_num; 1125 1126 if (flash_num == 0) { 1127 debug("Error: Missing flashes!\n"); 1128 return -ENODEV; 1129 } 1130 1131 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 1132 FSL_QSPI_DEFAULT_SCK_FREQ); 1133 plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", 1134 FSL_QSPI_MAX_CHIPSELECT_NUM); 1135 1136 plat->reg_base = res_regs.start; 1137 plat->amba_base = res_mem.start; 1138 plat->amba_total_size = res_mem.end - res_mem.start + 1; 1139 plat->flash_num = flash_num; 1140 1141 debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n", 1142 __func__, 1143 (u64)plat->reg_base, 1144 (u64)plat->amba_base, 1145 (u64)plat->amba_total_size, 1146 plat->speed_hz, 1147 plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" 1148 ); 1149 1150 return 0; 1151 } 1152 1153 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, 1154 const void *dout, void *din, unsigned long flags) 1155 { 1156 struct fsl_qspi_priv *priv; 1157 struct udevice *bus; 1158 1159 bus = dev->parent; 1160 priv = dev_get_priv(bus); 1161 1162 return qspi_xfer(priv, bitlen, dout, din, flags); 1163 } 1164 1165 static int fsl_qspi_claim_bus(struct udevice *dev) 1166 { 1167 struct fsl_qspi_priv *priv; 1168 struct udevice *bus; 1169 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 1170 int ret; 1171 1172 bus = dev->parent; 1173 priv = dev_get_priv(bus); 1174 1175 /* make sure controller is not busy anywhere */ 1176 ret = wait_for_bit(__func__, &priv->regs->sr, 1177 QSPI_SR_BUSY_MASK | 1178 QSPI_SR_AHB_ACC_MASK | 1179 QSPI_SR_IP_ACC_MASK, 1180 false, 100, false); 1181 1182 if (ret) { 1183 debug("ERROR : The controller is busy\n"); 1184 return ret; 1185 } 1186 1187 priv->cur_amba_base = priv->amba_base[slave_plat->cs]; 1188 1189 qspi_module_disable(priv, 0); 1190 1191 return 0; 1192 } 1193 1194 static int fsl_qspi_release_bus(struct udevice *dev) 1195 { 1196 struct fsl_qspi_priv *priv; 1197 struct udevice *bus; 1198 1199 bus = dev->parent; 1200 priv = dev_get_priv(bus); 1201 1202 qspi_module_disable(priv, 1); 1203 1204 return 0; 1205 } 1206 1207 static int fsl_qspi_set_speed(struct udevice *bus, uint speed) 1208 { 1209 /* Nothing to do */ 1210 return 0; 1211 } 1212 1213 static int fsl_qspi_set_mode(struct udevice *bus, uint mode) 1214 { 1215 /* Nothing to do */ 1216 return 0; 1217 } 1218 1219 static const struct dm_spi_ops fsl_qspi_ops = { 1220 .claim_bus = fsl_qspi_claim_bus, 1221 .release_bus = fsl_qspi_release_bus, 1222 .xfer = fsl_qspi_xfer, 1223 .set_speed = fsl_qspi_set_speed, 1224 .set_mode = fsl_qspi_set_mode, 1225 }; 1226 1227 static const struct udevice_id fsl_qspi_ids[] = { 1228 { .compatible = "fsl,vf610-qspi" }, 1229 { .compatible = "fsl,imx6sx-qspi" }, 1230 { } 1231 }; 1232 1233 U_BOOT_DRIVER(fsl_qspi) = { 1234 .name = "fsl_qspi", 1235 .id = UCLASS_SPI, 1236 .of_match = fsl_qspi_ids, 1237 .ops = &fsl_qspi_ops, 1238 .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata, 1239 .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata), 1240 .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv), 1241 .probe = fsl_qspi_probe, 1242 .child_pre_probe = fsl_qspi_child_pre_probe, 1243 }; 1244 #endif 1245