1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * Chao Fu (B44548@freescale.com) 8 * Haikun Wang (B53464@freescale.com) 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #include <dm.h> 13 #include <errno.h> 14 #include <common.h> 15 #include <spi.h> 16 #include <malloc.h> 17 #include <asm/io.h> 18 #include <fdtdec.h> 19 #ifndef CONFIG_M68K 20 #include <asm/arch/clock.h> 21 #endif 22 #include <fsl_dspi.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* fsl_dspi_platdata flags */ 27 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) 28 29 /* idle data value */ 30 #define DSPI_IDLE_VAL 0x0 31 32 /* max chipselect signals number */ 33 #define FSL_DSPI_MAX_CHIPSELECT 6 34 35 /* default SCK frequency, unit: HZ */ 36 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000 37 38 /* tx/rx data wait timeout value, unit: us */ 39 #define DSPI_TXRX_WAIT_TIMEOUT 1000000 40 41 /* CTAR register pre-configure value */ 42 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \ 43 DSPI_CTAR_PCSSCK_1CLK | \ 44 DSPI_CTAR_PASC(0) | \ 45 DSPI_CTAR_PDT(0) | \ 46 DSPI_CTAR_CSSCK(0) | \ 47 DSPI_CTAR_ASC(0) | \ 48 DSPI_CTAR_DT(0)) 49 50 /* CTAR register pre-configure mask */ 51 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \ 52 DSPI_CTAR_PCSSCK(3) | \ 53 DSPI_CTAR_PASC(3) | \ 54 DSPI_CTAR_PDT(3) | \ 55 DSPI_CTAR_CSSCK(15) | \ 56 DSPI_CTAR_ASC(15) | \ 57 DSPI_CTAR_DT(15)) 58 59 /** 60 * struct fsl_dspi_platdata - platform data for Freescale DSPI 61 * 62 * @flags: Flags for DSPI DSPI_FLAG_... 63 * @speed_hz: Default SCK frequency 64 * @num_chipselect: Number of DSPI chipselect signals 65 * @regs_addr: Base address of DSPI registers 66 */ 67 struct fsl_dspi_platdata { 68 uint flags; 69 uint speed_hz; 70 uint num_chipselect; 71 fdt_addr_t regs_addr; 72 }; 73 74 /** 75 * struct fsl_dspi_priv - private data for Freescale DSPI 76 * 77 * @flags: Flags for DSPI DSPI_FLAG_... 78 * @mode: SPI mode to use for slave device (see SPI mode flags) 79 * @mcr_val: MCR register configure value 80 * @bus_clk: DSPI input clk frequency 81 * @speed_hz: Default SCK frequency 82 * @charbit: How many bits in every transfer 83 * @num_chipselect: Number of DSPI chipselect signals 84 * @ctar_val: CTAR register configure value of per chipselect slave device 85 * @regs: Point to DSPI register structure for I/O access 86 */ 87 struct fsl_dspi_priv { 88 uint flags; 89 uint mode; 90 uint mcr_val; 91 uint bus_clk; 92 uint speed_hz; 93 uint charbit; 94 uint num_chipselect; 95 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT]; 96 struct dspi *regs; 97 }; 98 99 #ifndef CONFIG_DM_SPI 100 struct fsl_dspi { 101 struct spi_slave slave; 102 struct fsl_dspi_priv priv; 103 }; 104 #endif 105 106 __weak void cpu_dspi_port_conf(void) 107 { 108 } 109 110 __weak int cpu_dspi_claim_bus(uint bus, uint cs) 111 { 112 return 0; 113 } 114 115 __weak void cpu_dspi_release_bus(uint bus, uint cs) 116 { 117 } 118 119 static uint dspi_read32(uint flags, uint *addr) 120 { 121 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? 122 in_be32(addr) : in_le32(addr); 123 } 124 125 static void dspi_write32(uint flags, uint *addr, uint val) 126 { 127 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? 128 out_be32(addr, val) : out_le32(addr, val); 129 } 130 131 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt) 132 { 133 uint mcr_val; 134 135 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); 136 137 if (halt) 138 mcr_val |= DSPI_MCR_HALT; 139 else 140 mcr_val &= ~DSPI_MCR_HALT; 141 142 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 143 } 144 145 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val) 146 { 147 /* halt DSPI module */ 148 dspi_halt(priv, 1); 149 150 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val); 151 152 /* resume module */ 153 dspi_halt(priv, 0); 154 155 priv->mcr_val = cfg_val; 156 } 157 158 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv, 159 uint cs, uint state) 160 { 161 uint mcr_val; 162 163 dspi_halt(priv, 1); 164 165 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); 166 if (state & SPI_CS_HIGH) 167 /* CSx inactive state is low */ 168 mcr_val &= ~DSPI_MCR_PCSIS(cs); 169 else 170 /* CSx inactive state is high */ 171 mcr_val |= DSPI_MCR_PCSIS(cs); 172 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 173 174 dspi_halt(priv, 0); 175 } 176 177 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv, 178 uint cs, uint mode) 179 { 180 uint bus_setup; 181 182 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); 183 184 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK; 185 bus_setup |= priv->ctar_val[cs]; 186 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE); 187 188 if (mode & SPI_CPOL) 189 bus_setup |= DSPI_CTAR_CPOL; 190 if (mode & SPI_CPHA) 191 bus_setup |= DSPI_CTAR_CPHA; 192 if (mode & SPI_LSB_FIRST) 193 bus_setup |= DSPI_CTAR_LSBFE; 194 195 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); 196 197 priv->charbit = 198 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) & 199 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8; 200 201 return 0; 202 } 203 204 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv) 205 { 206 uint mcr_val; 207 208 dspi_halt(priv, 1); 209 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); 210 /* flush RX and TX FIFO */ 211 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF); 212 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 213 dspi_halt(priv, 0); 214 } 215 216 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data) 217 { 218 int timeout = DSPI_TXRX_WAIT_TIMEOUT; 219 220 /* wait for empty entries in TXFIFO or timeout */ 221 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 && 222 timeout--) 223 udelay(1); 224 225 if (timeout >= 0) 226 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data)); 227 else 228 debug("dspi_tx: waiting timeout!\n"); 229 } 230 231 static u16 dspi_rx(struct fsl_dspi_priv *priv) 232 { 233 int timeout = DSPI_TXRX_WAIT_TIMEOUT; 234 235 /* wait for valid entries in RXFIFO or timeout */ 236 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 && 237 timeout--) 238 udelay(1); 239 240 if (timeout >= 0) 241 return (u16)DSPI_RFR_RXDATA( 242 dspi_read32(priv->flags, &priv->regs->rfr)); 243 else { 244 debug("dspi_rx: waiting timeout!\n"); 245 return (u16)(~0); 246 } 247 } 248 249 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen, 250 const void *dout, void *din, unsigned long flags) 251 { 252 u16 *spi_rd16 = NULL, *spi_wr16 = NULL; 253 u8 *spi_rd = NULL, *spi_wr = NULL; 254 static u32 ctrl; 255 uint len = bitlen >> 3; 256 257 if (priv->charbit == 16) { 258 bitlen >>= 1; 259 spi_wr16 = (u16 *)dout; 260 spi_rd16 = (u16 *)din; 261 } else { 262 spi_wr = (u8 *)dout; 263 spi_rd = (u8 *)din; 264 } 265 266 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) 267 ctrl |= DSPI_TFR_CONT; 268 269 ctrl = ctrl & DSPI_TFR_CONT; 270 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs); 271 272 if (len > 1) { 273 int tmp_len = len - 1; 274 while (tmp_len--) { 275 if (dout != NULL) { 276 if (priv->charbit == 16) 277 dspi_tx(priv, ctrl, *spi_wr16++); 278 else 279 dspi_tx(priv, ctrl, *spi_wr++); 280 dspi_rx(priv); 281 } 282 283 if (din != NULL) { 284 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); 285 if (priv->charbit == 16) 286 *spi_rd16++ = dspi_rx(priv); 287 else 288 *spi_rd++ = dspi_rx(priv); 289 } 290 } 291 292 len = 1; /* remaining byte */ 293 } 294 295 if ((flags & SPI_XFER_END) == SPI_XFER_END) 296 ctrl &= ~DSPI_TFR_CONT; 297 298 if (len) { 299 if (dout != NULL) { 300 if (priv->charbit == 16) 301 dspi_tx(priv, ctrl, *spi_wr16); 302 else 303 dspi_tx(priv, ctrl, *spi_wr); 304 dspi_rx(priv); 305 } 306 307 if (din != NULL) { 308 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); 309 if (priv->charbit == 16) 310 *spi_rd16 = dspi_rx(priv); 311 else 312 *spi_rd = dspi_rx(priv); 313 } 314 } else { 315 /* dummy read */ 316 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); 317 dspi_rx(priv); 318 } 319 320 return 0; 321 } 322 323 /** 324 * Calculate the divide value between input clk frequency and expected SCK frequency 325 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br) 326 * Dbr: use default value 0 327 * 328 * @pbr: return Baud Rate Prescaler value 329 * @br: return Baud Rate Scaler value 330 * @speed_hz: expected SCK frequency 331 * @clkrate: input clk frequency 332 */ 333 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br, 334 int speed_hz, uint clkrate) 335 { 336 /* Valid baud rate pre-scaler values */ 337 int pbr_tbl[4] = {2, 3, 5, 7}; 338 int brs[16] = {2, 4, 6, 8, 339 16, 32, 64, 128, 340 256, 512, 1024, 2048, 341 4096, 8192, 16384, 32768}; 342 int temp, i = 0, j = 0; 343 344 temp = clkrate / speed_hz; 345 346 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++) 347 for (j = 0; j < ARRAY_SIZE(brs); j++) { 348 if (pbr_tbl[i] * brs[j] >= temp) { 349 *pbr = i; 350 *br = j; 351 return 0; 352 } 353 } 354 355 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz); 356 debug("clkrate is %d, we use the max prescaler value.\n", clkrate); 357 358 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 359 *br = ARRAY_SIZE(brs) - 1; 360 return -EINVAL; 361 } 362 363 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed) 364 { 365 int ret; 366 uint bus_setup; 367 int best_i, best_j, bus_clk; 368 369 bus_clk = priv->bus_clk; 370 371 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n", 372 speed, bus_clk); 373 374 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); 375 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf)); 376 377 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk); 378 if (ret) { 379 speed = priv->speed_hz; 380 debug("DSPI set_speed use default SCK rate %u.\n", speed); 381 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk); 382 } 383 384 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); 385 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); 386 387 priv->speed_hz = speed; 388 389 return 0; 390 } 391 #ifndef CONFIG_DM_SPI 392 void spi_init(void) 393 { 394 /* Nothing to do */ 395 } 396 397 void spi_init_f(void) 398 { 399 /* Nothing to do */ 400 } 401 402 void spi_init_r(void) 403 { 404 /* Nothing to do */ 405 } 406 407 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 408 { 409 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) 410 return 1; 411 else 412 return 0; 413 } 414 415 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 416 unsigned int max_hz, unsigned int mode) 417 { 418 struct fsl_dspi *dspi; 419 uint mcr_cfg_val; 420 421 dspi = spi_alloc_slave(struct fsl_dspi, bus, cs); 422 if (!dspi) 423 return NULL; 424 425 cpu_dspi_port_conf(); 426 427 #ifdef CONFIG_SYS_FSL_DSPI_BE 428 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; 429 #endif 430 431 dspi->priv.regs = (struct dspi *)MMAP_DSPI; 432 433 #ifdef CONFIG_M68K 434 dspi->priv.bus_clk = gd->bus_clk; 435 #else 436 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK); 437 #endif 438 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ; 439 440 /* default: all CS signals inactive state is high */ 441 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | 442 DSPI_MCR_CRXF | DSPI_MCR_CTXF; 443 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val); 444 445 for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++) 446 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE; 447 448 #ifdef CONFIG_SYS_DSPI_CTAR0 449 if (FSL_DSPI_MAX_CHIPSELECT > 0) 450 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0; 451 #endif 452 #ifdef CONFIG_SYS_DSPI_CTAR1 453 if (FSL_DSPI_MAX_CHIPSELECT > 1) 454 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1; 455 #endif 456 #ifdef CONFIG_SYS_DSPI_CTAR2 457 if (FSL_DSPI_MAX_CHIPSELECT > 2) 458 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2; 459 #endif 460 #ifdef CONFIG_SYS_DSPI_CTAR3 461 if (FSL_DSPI_MAX_CHIPSELECT > 3) 462 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3; 463 #endif 464 #ifdef CONFIG_SYS_DSPI_CTAR4 465 if (FSL_DSPI_MAX_CHIPSELECT > 4) 466 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4; 467 #endif 468 #ifdef CONFIG_SYS_DSPI_CTAR5 469 if (FSL_DSPI_MAX_CHIPSELECT > 5) 470 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5; 471 #endif 472 #ifdef CONFIG_SYS_DSPI_CTAR6 473 if (FSL_DSPI_MAX_CHIPSELECT > 6) 474 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6; 475 #endif 476 #ifdef CONFIG_SYS_DSPI_CTAR7 477 if (FSL_DSPI_MAX_CHIPSELECT > 7) 478 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7; 479 #endif 480 481 fsl_dspi_cfg_speed(&dspi->priv, max_hz); 482 483 /* configure transfer mode */ 484 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode); 485 486 /* configure active state of CSX */ 487 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode); 488 489 return &dspi->slave; 490 } 491 492 void spi_free_slave(struct spi_slave *slave) 493 { 494 free(slave); 495 } 496 497 int spi_claim_bus(struct spi_slave *slave) 498 { 499 uint sr_val; 500 struct fsl_dspi *dspi = (struct fsl_dspi *)slave; 501 502 cpu_dspi_claim_bus(slave->bus, slave->cs); 503 504 fsl_dspi_clr_fifo(&dspi->priv); 505 506 /* check module TX and RX status */ 507 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr); 508 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) { 509 debug("DSPI RX/TX not ready!\n"); 510 return -EIO; 511 } 512 513 return 0; 514 } 515 516 void spi_release_bus(struct spi_slave *slave) 517 { 518 struct fsl_dspi *dspi = (struct fsl_dspi *)slave; 519 520 dspi_halt(&dspi->priv, 1); 521 cpu_dspi_release_bus(slave->bus.slave->cs); 522 } 523 524 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 525 void *din, unsigned long flags) 526 { 527 struct fsl_dspi *dspi = (struct fsl_dspi *)slave; 528 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags); 529 } 530 #else 531 static int fsl_dspi_child_pre_probe(struct udevice *dev) 532 { 533 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 534 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent); 535 536 if (slave_plat->cs >= priv->num_chipselect) { 537 debug("DSPI invalid chipselect number %d(max %d)!\n", 538 slave_plat->cs, priv->num_chipselect - 1); 539 return -EINVAL; 540 } 541 542 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE; 543 544 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n", 545 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 546 547 return 0; 548 } 549 550 static int fsl_dspi_probe(struct udevice *bus) 551 { 552 struct fsl_dspi_platdata *plat = dev_get_platdata(bus); 553 struct fsl_dspi_priv *priv = dev_get_priv(bus); 554 struct dm_spi_bus *dm_spi_bus; 555 uint mcr_cfg_val; 556 557 dm_spi_bus = bus->uclass_priv; 558 559 /* cpu speical pin muxing configure */ 560 cpu_dspi_port_conf(); 561 562 /* get input clk frequency */ 563 priv->regs = (struct dspi *)plat->regs_addr; 564 priv->flags = plat->flags; 565 #ifdef CONFIG_M68K 566 priv->bus_clk = gd->bus_clk; 567 #else 568 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK); 569 #endif 570 priv->num_chipselect = plat->num_chipselect; 571 priv->speed_hz = plat->speed_hz; 572 /* frame data length in bits, default 8bits */ 573 priv->charbit = 8; 574 575 dm_spi_bus->max_hz = plat->speed_hz; 576 577 /* default: all CS signals inactive state is high */ 578 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | 579 DSPI_MCR_CRXF | DSPI_MCR_CTXF; 580 fsl_dspi_init_mcr(priv, mcr_cfg_val); 581 582 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); 583 584 return 0; 585 } 586 587 static int fsl_dspi_claim_bus(struct udevice *dev) 588 { 589 uint sr_val; 590 struct fsl_dspi_priv *priv; 591 struct udevice *bus = dev->parent; 592 struct dm_spi_slave_platdata *slave_plat = 593 dev_get_parent_platdata(dev); 594 595 priv = dev_get_priv(bus); 596 597 /* processor special prepartion work */ 598 cpu_dspi_claim_bus(bus->seq, slave_plat->cs); 599 600 /* configure transfer mode */ 601 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode); 602 603 /* configure active state of CSX */ 604 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs, 605 priv->mode); 606 607 fsl_dspi_clr_fifo(priv); 608 609 /* check module TX and RX status */ 610 sr_val = dspi_read32(priv->flags, &priv->regs->sr); 611 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) { 612 debug("DSPI RX/TX not ready!\n"); 613 return -EIO; 614 } 615 616 return 0; 617 } 618 619 static int fsl_dspi_release_bus(struct udevice *dev) 620 { 621 struct udevice *bus = dev->parent; 622 struct fsl_dspi_priv *priv = dev_get_priv(bus); 623 struct dm_spi_slave_platdata *slave_plat = 624 dev_get_parent_platdata(dev); 625 626 /* halt module */ 627 dspi_halt(priv, 1); 628 629 /* processor special release work */ 630 cpu_dspi_release_bus(bus->seq, slave_plat->cs); 631 632 return 0; 633 } 634 635 /** 636 * This function doesn't do anything except help with debugging 637 */ 638 static int fsl_dspi_bind(struct udevice *bus) 639 { 640 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq); 641 return 0; 642 } 643 644 static int fsl_dspi_ofdata_to_platdata(struct udevice *bus) 645 { 646 fdt_addr_t addr; 647 struct fsl_dspi_platdata *plat = bus->platdata; 648 const void *blob = gd->fdt_blob; 649 int node = bus->of_offset; 650 651 if (fdtdec_get_bool(blob, node, "big-endian")) 652 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; 653 654 plat->num_chipselect = 655 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT); 656 657 addr = dev_get_addr(bus); 658 if (addr == FDT_ADDR_T_NONE) { 659 debug("DSPI: Can't get base address or size\n"); 660 return -ENOMEM; 661 } 662 plat->regs_addr = addr; 663 664 plat->speed_hz = fdtdec_get_int(blob, 665 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ); 666 667 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n", 668 &plat->regs_addr, plat->speed_hz, 669 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le", 670 plat->num_chipselect); 671 672 return 0; 673 } 674 675 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen, 676 const void *dout, void *din, unsigned long flags) 677 { 678 struct fsl_dspi_priv *priv; 679 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 680 struct udevice *bus; 681 682 bus = dev->parent; 683 priv = dev_get_priv(bus); 684 685 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags); 686 } 687 688 static int fsl_dspi_set_speed(struct udevice *bus, uint speed) 689 { 690 struct fsl_dspi_priv *priv = dev_get_priv(bus); 691 692 return fsl_dspi_cfg_speed(priv, speed); 693 } 694 695 static int fsl_dspi_set_mode(struct udevice *bus, uint mode) 696 { 697 struct fsl_dspi_priv *priv = dev_get_priv(bus); 698 699 debug("DSPI set_mode: mode 0x%x.\n", mode); 700 701 /* 702 * We store some chipselect special configure value in priv->ctar_val, 703 * and we can't get the correct chipselect number here, 704 * so just store mode value. 705 * Do really configuration when claim_bus. 706 */ 707 priv->mode = mode; 708 709 return 0; 710 } 711 712 static const struct dm_spi_ops fsl_dspi_ops = { 713 .claim_bus = fsl_dspi_claim_bus, 714 .release_bus = fsl_dspi_release_bus, 715 .xfer = fsl_dspi_xfer, 716 .set_speed = fsl_dspi_set_speed, 717 .set_mode = fsl_dspi_set_mode, 718 }; 719 720 static const struct udevice_id fsl_dspi_ids[] = { 721 { .compatible = "fsl,vf610-dspi" }, 722 { } 723 }; 724 725 U_BOOT_DRIVER(fsl_dspi) = { 726 .name = "fsl_dspi", 727 .id = UCLASS_SPI, 728 .of_match = fsl_dspi_ids, 729 .ops = &fsl_dspi_ops, 730 .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata, 731 .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata), 732 .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv), 733 .probe = fsl_dspi_probe, 734 .child_pre_probe = fsl_dspi_child_pre_probe, 735 .bind = fsl_dspi_bind, 736 }; 737 #endif 738