1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc. 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 8 * Chao Fu (B44548@freescale.com) 9 * Haikun Wang (B53464@freescale.com) 10 */ 11 12 #include <common.h> 13 #include <dm.h> 14 #include <errno.h> 15 #include <common.h> 16 #include <spi.h> 17 #include <malloc.h> 18 #include <asm/io.h> 19 #include <fdtdec.h> 20 #ifndef CONFIG_M68K 21 #include <asm/arch/clock.h> 22 #endif 23 #include <fsl_dspi.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* fsl_dspi_platdata flags */ 28 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) 29 30 /* idle data value */ 31 #define DSPI_IDLE_VAL 0x0 32 33 /* max chipselect signals number */ 34 #define FSL_DSPI_MAX_CHIPSELECT 6 35 36 /* default SCK frequency, unit: HZ */ 37 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000 38 39 /* tx/rx data wait timeout value, unit: us */ 40 #define DSPI_TXRX_WAIT_TIMEOUT 1000000 41 42 /* CTAR register pre-configure value */ 43 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \ 44 DSPI_CTAR_PCSSCK_1CLK | \ 45 DSPI_CTAR_PASC(0) | \ 46 DSPI_CTAR_PDT(0) | \ 47 DSPI_CTAR_CSSCK(0) | \ 48 DSPI_CTAR_ASC(0) | \ 49 DSPI_CTAR_DT(0)) 50 51 /* CTAR register pre-configure mask */ 52 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \ 53 DSPI_CTAR_PCSSCK(3) | \ 54 DSPI_CTAR_PASC(3) | \ 55 DSPI_CTAR_PDT(3) | \ 56 DSPI_CTAR_CSSCK(15) | \ 57 DSPI_CTAR_ASC(15) | \ 58 DSPI_CTAR_DT(15)) 59 60 /** 61 * struct fsl_dspi_platdata - platform data for Freescale DSPI 62 * 63 * @flags: Flags for DSPI DSPI_FLAG_... 64 * @speed_hz: Default SCK frequency 65 * @num_chipselect: Number of DSPI chipselect signals 66 * @regs_addr: Base address of DSPI registers 67 */ 68 struct fsl_dspi_platdata { 69 uint flags; 70 uint speed_hz; 71 uint num_chipselect; 72 fdt_addr_t regs_addr; 73 }; 74 75 /** 76 * struct fsl_dspi_priv - private data for Freescale DSPI 77 * 78 * @flags: Flags for DSPI DSPI_FLAG_... 79 * @mode: SPI mode to use for slave device (see SPI mode flags) 80 * @mcr_val: MCR register configure value 81 * @bus_clk: DSPI input clk frequency 82 * @speed_hz: Default SCK frequency 83 * @charbit: How many bits in every transfer 84 * @num_chipselect: Number of DSPI chipselect signals 85 * @ctar_val: CTAR register configure value of per chipselect slave device 86 * @regs: Point to DSPI register structure for I/O access 87 */ 88 struct fsl_dspi_priv { 89 uint flags; 90 uint mode; 91 uint mcr_val; 92 uint bus_clk; 93 uint speed_hz; 94 uint charbit; 95 uint num_chipselect; 96 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT]; 97 struct dspi *regs; 98 }; 99 100 #ifndef CONFIG_DM_SPI 101 struct fsl_dspi { 102 struct spi_slave slave; 103 struct fsl_dspi_priv priv; 104 }; 105 #endif 106 107 __weak void cpu_dspi_port_conf(void) 108 { 109 } 110 111 __weak int cpu_dspi_claim_bus(uint bus, uint cs) 112 { 113 return 0; 114 } 115 116 __weak void cpu_dspi_release_bus(uint bus, uint cs) 117 { 118 } 119 120 static uint dspi_read32(uint flags, uint *addr) 121 { 122 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? 123 in_be32(addr) : in_le32(addr); 124 } 125 126 static void dspi_write32(uint flags, uint *addr, uint val) 127 { 128 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? 129 out_be32(addr, val) : out_le32(addr, val); 130 } 131 132 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt) 133 { 134 uint mcr_val; 135 136 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); 137 138 if (halt) 139 mcr_val |= DSPI_MCR_HALT; 140 else 141 mcr_val &= ~DSPI_MCR_HALT; 142 143 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 144 } 145 146 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val) 147 { 148 /* halt DSPI module */ 149 dspi_halt(priv, 1); 150 151 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val); 152 153 /* resume module */ 154 dspi_halt(priv, 0); 155 156 priv->mcr_val = cfg_val; 157 } 158 159 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv, 160 uint cs, uint state) 161 { 162 uint mcr_val; 163 164 dspi_halt(priv, 1); 165 166 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); 167 if (state & SPI_CS_HIGH) 168 /* CSx inactive state is low */ 169 mcr_val &= ~DSPI_MCR_PCSIS(cs); 170 else 171 /* CSx inactive state is high */ 172 mcr_val |= DSPI_MCR_PCSIS(cs); 173 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 174 175 dspi_halt(priv, 0); 176 } 177 178 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv, 179 uint cs, uint mode) 180 { 181 uint bus_setup; 182 183 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); 184 185 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK; 186 bus_setup |= priv->ctar_val[cs]; 187 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE); 188 189 if (mode & SPI_CPOL) 190 bus_setup |= DSPI_CTAR_CPOL; 191 if (mode & SPI_CPHA) 192 bus_setup |= DSPI_CTAR_CPHA; 193 if (mode & SPI_LSB_FIRST) 194 bus_setup |= DSPI_CTAR_LSBFE; 195 196 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); 197 198 priv->charbit = 199 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) & 200 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8; 201 202 return 0; 203 } 204 205 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv) 206 { 207 uint mcr_val; 208 209 dspi_halt(priv, 1); 210 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); 211 /* flush RX and TX FIFO */ 212 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF); 213 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); 214 dspi_halt(priv, 0); 215 } 216 217 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data) 218 { 219 int timeout = DSPI_TXRX_WAIT_TIMEOUT; 220 221 /* wait for empty entries in TXFIFO or timeout */ 222 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 && 223 timeout--) 224 udelay(1); 225 226 if (timeout >= 0) 227 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data)); 228 else 229 debug("dspi_tx: waiting timeout!\n"); 230 } 231 232 static u16 dspi_rx(struct fsl_dspi_priv *priv) 233 { 234 int timeout = DSPI_TXRX_WAIT_TIMEOUT; 235 236 /* wait for valid entries in RXFIFO or timeout */ 237 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 && 238 timeout--) 239 udelay(1); 240 241 if (timeout >= 0) 242 return (u16)DSPI_RFR_RXDATA( 243 dspi_read32(priv->flags, &priv->regs->rfr)); 244 else { 245 debug("dspi_rx: waiting timeout!\n"); 246 return (u16)(~0); 247 } 248 } 249 250 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen, 251 const void *dout, void *din, unsigned long flags) 252 { 253 u16 *spi_rd16 = NULL, *spi_wr16 = NULL; 254 u8 *spi_rd = NULL, *spi_wr = NULL; 255 static u32 ctrl; 256 uint len = bitlen >> 3; 257 258 if (priv->charbit == 16) { 259 bitlen >>= 1; 260 spi_wr16 = (u16 *)dout; 261 spi_rd16 = (u16 *)din; 262 } else { 263 spi_wr = (u8 *)dout; 264 spi_rd = (u8 *)din; 265 } 266 267 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) 268 ctrl |= DSPI_TFR_CONT; 269 270 ctrl = ctrl & DSPI_TFR_CONT; 271 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs); 272 273 if (len > 1) { 274 int tmp_len = len - 1; 275 while (tmp_len--) { 276 if (dout != NULL) { 277 if (priv->charbit == 16) 278 dspi_tx(priv, ctrl, *spi_wr16++); 279 else 280 dspi_tx(priv, ctrl, *spi_wr++); 281 dspi_rx(priv); 282 } 283 284 if (din != NULL) { 285 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); 286 if (priv->charbit == 16) 287 *spi_rd16++ = dspi_rx(priv); 288 else 289 *spi_rd++ = dspi_rx(priv); 290 } 291 } 292 293 len = 1; /* remaining byte */ 294 } 295 296 if ((flags & SPI_XFER_END) == SPI_XFER_END) 297 ctrl &= ~DSPI_TFR_CONT; 298 299 if (len) { 300 if (dout != NULL) { 301 if (priv->charbit == 16) 302 dspi_tx(priv, ctrl, *spi_wr16); 303 else 304 dspi_tx(priv, ctrl, *spi_wr); 305 dspi_rx(priv); 306 } 307 308 if (din != NULL) { 309 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); 310 if (priv->charbit == 16) 311 *spi_rd16 = dspi_rx(priv); 312 else 313 *spi_rd = dspi_rx(priv); 314 } 315 } else { 316 /* dummy read */ 317 dspi_tx(priv, ctrl, DSPI_IDLE_VAL); 318 dspi_rx(priv); 319 } 320 321 return 0; 322 } 323 324 /** 325 * Calculate the divide value between input clk frequency and expected SCK frequency 326 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br) 327 * Dbr: use default value 0 328 * 329 * @pbr: return Baud Rate Prescaler value 330 * @br: return Baud Rate Scaler value 331 * @speed_hz: expected SCK frequency 332 * @clkrate: input clk frequency 333 */ 334 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br, 335 int speed_hz, uint clkrate) 336 { 337 /* Valid baud rate pre-scaler values */ 338 int pbr_tbl[4] = {2, 3, 5, 7}; 339 int brs[16] = {2, 4, 6, 8, 340 16, 32, 64, 128, 341 256, 512, 1024, 2048, 342 4096, 8192, 16384, 32768}; 343 int temp, i = 0, j = 0; 344 345 temp = clkrate / speed_hz; 346 347 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++) 348 for (j = 0; j < ARRAY_SIZE(brs); j++) { 349 if (pbr_tbl[i] * brs[j] >= temp) { 350 *pbr = i; 351 *br = j; 352 return 0; 353 } 354 } 355 356 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz); 357 debug("clkrate is %d, we use the max prescaler value.\n", clkrate); 358 359 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 360 *br = ARRAY_SIZE(brs) - 1; 361 return -EINVAL; 362 } 363 364 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed) 365 { 366 int ret; 367 uint bus_setup; 368 int best_i, best_j, bus_clk; 369 370 bus_clk = priv->bus_clk; 371 372 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n", 373 speed, bus_clk); 374 375 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); 376 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf)); 377 378 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk); 379 if (ret) { 380 speed = priv->speed_hz; 381 debug("DSPI set_speed use default SCK rate %u.\n", speed); 382 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk); 383 } 384 385 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); 386 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); 387 388 priv->speed_hz = speed; 389 390 return 0; 391 } 392 #ifndef CONFIG_DM_SPI 393 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 394 { 395 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) 396 return 1; 397 else 398 return 0; 399 } 400 401 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 402 unsigned int max_hz, unsigned int mode) 403 { 404 struct fsl_dspi *dspi; 405 uint mcr_cfg_val; 406 407 dspi = spi_alloc_slave(struct fsl_dspi, bus, cs); 408 if (!dspi) 409 return NULL; 410 411 cpu_dspi_port_conf(); 412 413 #ifdef CONFIG_SYS_FSL_DSPI_BE 414 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; 415 #endif 416 417 dspi->priv.regs = (struct dspi *)MMAP_DSPI; 418 419 #ifdef CONFIG_M68K 420 dspi->priv.bus_clk = gd->bus_clk; 421 #else 422 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK); 423 #endif 424 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ; 425 426 /* default: all CS signals inactive state is high */ 427 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | 428 DSPI_MCR_CRXF | DSPI_MCR_CTXF; 429 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val); 430 431 for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++) 432 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE; 433 434 #ifdef CONFIG_SYS_DSPI_CTAR0 435 if (FSL_DSPI_MAX_CHIPSELECT > 0) 436 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0; 437 #endif 438 #ifdef CONFIG_SYS_DSPI_CTAR1 439 if (FSL_DSPI_MAX_CHIPSELECT > 1) 440 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1; 441 #endif 442 #ifdef CONFIG_SYS_DSPI_CTAR2 443 if (FSL_DSPI_MAX_CHIPSELECT > 2) 444 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2; 445 #endif 446 #ifdef CONFIG_SYS_DSPI_CTAR3 447 if (FSL_DSPI_MAX_CHIPSELECT > 3) 448 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3; 449 #endif 450 #ifdef CONFIG_SYS_DSPI_CTAR4 451 if (FSL_DSPI_MAX_CHIPSELECT > 4) 452 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4; 453 #endif 454 #ifdef CONFIG_SYS_DSPI_CTAR5 455 if (FSL_DSPI_MAX_CHIPSELECT > 5) 456 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5; 457 #endif 458 #ifdef CONFIG_SYS_DSPI_CTAR6 459 if (FSL_DSPI_MAX_CHIPSELECT > 6) 460 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6; 461 #endif 462 #ifdef CONFIG_SYS_DSPI_CTAR7 463 if (FSL_DSPI_MAX_CHIPSELECT > 7) 464 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7; 465 #endif 466 467 fsl_dspi_cfg_speed(&dspi->priv, max_hz); 468 469 /* configure transfer mode */ 470 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode); 471 472 /* configure active state of CSX */ 473 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode); 474 475 return &dspi->slave; 476 } 477 478 void spi_free_slave(struct spi_slave *slave) 479 { 480 free(slave); 481 } 482 483 int spi_claim_bus(struct spi_slave *slave) 484 { 485 uint sr_val; 486 struct fsl_dspi *dspi = (struct fsl_dspi *)slave; 487 488 cpu_dspi_claim_bus(slave->bus, slave->cs); 489 490 fsl_dspi_clr_fifo(&dspi->priv); 491 492 /* check module TX and RX status */ 493 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr); 494 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) { 495 debug("DSPI RX/TX not ready!\n"); 496 return -EIO; 497 } 498 499 return 0; 500 } 501 502 void spi_release_bus(struct spi_slave *slave) 503 { 504 struct fsl_dspi *dspi = (struct fsl_dspi *)slave; 505 506 dspi_halt(&dspi->priv, 1); 507 cpu_dspi_release_bus(slave->bus.slave->cs); 508 } 509 510 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 511 void *din, unsigned long flags) 512 { 513 struct fsl_dspi *dspi = (struct fsl_dspi *)slave; 514 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags); 515 } 516 #else 517 static int fsl_dspi_child_pre_probe(struct udevice *dev) 518 { 519 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 520 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent); 521 522 if (slave_plat->cs >= priv->num_chipselect) { 523 debug("DSPI invalid chipselect number %d(max %d)!\n", 524 slave_plat->cs, priv->num_chipselect - 1); 525 return -EINVAL; 526 } 527 528 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE; 529 530 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n", 531 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 532 533 return 0; 534 } 535 536 static int fsl_dspi_probe(struct udevice *bus) 537 { 538 struct fsl_dspi_platdata *plat = dev_get_platdata(bus); 539 struct fsl_dspi_priv *priv = dev_get_priv(bus); 540 struct dm_spi_bus *dm_spi_bus; 541 uint mcr_cfg_val; 542 543 dm_spi_bus = bus->uclass_priv; 544 545 /* cpu speical pin muxing configure */ 546 cpu_dspi_port_conf(); 547 548 /* get input clk frequency */ 549 priv->regs = (struct dspi *)plat->regs_addr; 550 priv->flags = plat->flags; 551 #ifdef CONFIG_M68K 552 priv->bus_clk = gd->bus_clk; 553 #else 554 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK); 555 #endif 556 priv->num_chipselect = plat->num_chipselect; 557 priv->speed_hz = plat->speed_hz; 558 /* frame data length in bits, default 8bits */ 559 priv->charbit = 8; 560 561 dm_spi_bus->max_hz = plat->speed_hz; 562 563 /* default: all CS signals inactive state is high */ 564 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | 565 DSPI_MCR_CRXF | DSPI_MCR_CTXF; 566 fsl_dspi_init_mcr(priv, mcr_cfg_val); 567 568 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); 569 570 return 0; 571 } 572 573 static int fsl_dspi_claim_bus(struct udevice *dev) 574 { 575 uint sr_val; 576 struct fsl_dspi_priv *priv; 577 struct udevice *bus = dev->parent; 578 struct dm_spi_slave_platdata *slave_plat = 579 dev_get_parent_platdata(dev); 580 581 priv = dev_get_priv(bus); 582 583 /* processor special preparation work */ 584 cpu_dspi_claim_bus(bus->seq, slave_plat->cs); 585 586 /* configure transfer mode */ 587 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode); 588 589 /* configure active state of CSX */ 590 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs, 591 priv->mode); 592 593 fsl_dspi_clr_fifo(priv); 594 595 /* check module TX and RX status */ 596 sr_val = dspi_read32(priv->flags, &priv->regs->sr); 597 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) { 598 debug("DSPI RX/TX not ready!\n"); 599 return -EIO; 600 } 601 602 return 0; 603 } 604 605 static int fsl_dspi_release_bus(struct udevice *dev) 606 { 607 struct udevice *bus = dev->parent; 608 struct fsl_dspi_priv *priv = dev_get_priv(bus); 609 struct dm_spi_slave_platdata *slave_plat = 610 dev_get_parent_platdata(dev); 611 612 /* halt module */ 613 dspi_halt(priv, 1); 614 615 /* processor special release work */ 616 cpu_dspi_release_bus(bus->seq, slave_plat->cs); 617 618 return 0; 619 } 620 621 /** 622 * This function doesn't do anything except help with debugging 623 */ 624 static int fsl_dspi_bind(struct udevice *bus) 625 { 626 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq); 627 return 0; 628 } 629 630 static int fsl_dspi_ofdata_to_platdata(struct udevice *bus) 631 { 632 fdt_addr_t addr; 633 struct fsl_dspi_platdata *plat = bus->platdata; 634 const void *blob = gd->fdt_blob; 635 int node = dev_of_offset(bus); 636 637 if (fdtdec_get_bool(blob, node, "big-endian")) 638 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; 639 640 plat->num_chipselect = 641 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT); 642 643 addr = devfdt_get_addr(bus); 644 if (addr == FDT_ADDR_T_NONE) { 645 debug("DSPI: Can't get base address or size\n"); 646 return -ENOMEM; 647 } 648 plat->regs_addr = addr; 649 650 plat->speed_hz = fdtdec_get_int(blob, 651 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ); 652 653 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n", 654 &plat->regs_addr, plat->speed_hz, 655 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le", 656 plat->num_chipselect); 657 658 return 0; 659 } 660 661 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen, 662 const void *dout, void *din, unsigned long flags) 663 { 664 struct fsl_dspi_priv *priv; 665 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 666 struct udevice *bus; 667 668 bus = dev->parent; 669 priv = dev_get_priv(bus); 670 671 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags); 672 } 673 674 static int fsl_dspi_set_speed(struct udevice *bus, uint speed) 675 { 676 struct fsl_dspi_priv *priv = dev_get_priv(bus); 677 678 return fsl_dspi_cfg_speed(priv, speed); 679 } 680 681 static int fsl_dspi_set_mode(struct udevice *bus, uint mode) 682 { 683 struct fsl_dspi_priv *priv = dev_get_priv(bus); 684 685 debug("DSPI set_mode: mode 0x%x.\n", mode); 686 687 /* 688 * We store some chipselect special configure value in priv->ctar_val, 689 * and we can't get the correct chipselect number here, 690 * so just store mode value. 691 * Do really configuration when claim_bus. 692 */ 693 priv->mode = mode; 694 695 return 0; 696 } 697 698 static const struct dm_spi_ops fsl_dspi_ops = { 699 .claim_bus = fsl_dspi_claim_bus, 700 .release_bus = fsl_dspi_release_bus, 701 .xfer = fsl_dspi_xfer, 702 .set_speed = fsl_dspi_set_speed, 703 .set_mode = fsl_dspi_set_mode, 704 }; 705 706 static const struct udevice_id fsl_dspi_ids[] = { 707 { .compatible = "fsl,vf610-dspi" }, 708 { } 709 }; 710 711 U_BOOT_DRIVER(fsl_dspi) = { 712 .name = "fsl_dspi", 713 .id = UCLASS_SPI, 714 .of_match = fsl_dspi_ids, 715 .ops = &fsl_dspi_ops, 716 .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata, 717 .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata), 718 .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv), 719 .probe = fsl_dspi_probe, 720 .child_pre_probe = fsl_dspi_child_pre_probe, 721 .bind = fsl_dspi_bind, 722 }; 723 #endif 724