1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Padmavathi Venna <padma.v@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <malloc.h> 22 #include <spi.h> 23 #include <fdtdec.h> 24 #include <asm/arch/clk.h> 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/pinmux.h> 29 #include <asm/arch-exynos/spi.h> 30 #include <asm/io.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* Information about each SPI controller */ 35 struct spi_bus { 36 enum periph_id periph_id; 37 s32 frequency; /* Default clock frequency, -1 for none */ 38 struct exynos_spi *regs; 39 int inited; /* 1 if this bus is ready for use */ 40 int node; 41 }; 42 43 /* A list of spi buses that we know about */ 44 static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS]; 45 static unsigned int bus_count; 46 47 struct exynos_spi_slave { 48 struct spi_slave slave; 49 struct exynos_spi *regs; 50 unsigned int freq; /* Default frequency */ 51 unsigned int mode; 52 enum periph_id periph_id; /* Peripheral ID for this device */ 53 unsigned int fifo_size; 54 }; 55 56 static struct spi_bus *spi_get_bus(unsigned dev_index) 57 { 58 if (dev_index < bus_count) 59 return &spi_bus[dev_index]; 60 debug("%s: invalid bus %d", __func__, dev_index); 61 62 return NULL; 63 } 64 65 static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave) 66 { 67 return container_of(slave, struct exynos_spi_slave, slave); 68 } 69 70 /** 71 * Setup the driver private data 72 * 73 * @param bus ID of the bus that the slave is attached to 74 * @param cs ID of the chip select connected to the slave 75 * @param max_hz Required spi frequency 76 * @param mode Required spi mode (clk polarity, clk phase and 77 * master or slave) 78 * @return new device or NULL 79 */ 80 struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs, 81 unsigned int max_hz, unsigned int mode) 82 { 83 struct exynos_spi_slave *spi_slave; 84 struct spi_bus *bus; 85 86 if (!spi_cs_is_valid(busnum, cs)) { 87 debug("%s: Invalid bus/chip select %d, %d\n", __func__, 88 busnum, cs); 89 return NULL; 90 } 91 92 spi_slave = malloc(sizeof(*spi_slave)); 93 if (!spi_slave) { 94 debug("%s: Could not allocate spi_slave\n", __func__); 95 return NULL; 96 } 97 98 bus = &spi_bus[busnum]; 99 spi_slave->slave.bus = busnum; 100 spi_slave->slave.cs = cs; 101 spi_slave->regs = bus->regs; 102 spi_slave->mode = mode; 103 spi_slave->periph_id = bus->periph_id; 104 if (bus->periph_id == PERIPH_ID_SPI1 || 105 bus->periph_id == PERIPH_ID_SPI2) 106 spi_slave->fifo_size = 64; 107 else 108 spi_slave->fifo_size = 256; 109 110 spi_slave->freq = bus->frequency; 111 if (max_hz) 112 spi_slave->freq = min(max_hz, spi_slave->freq); 113 114 return &spi_slave->slave; 115 } 116 117 /** 118 * Free spi controller 119 * 120 * @param slave Pointer to spi_slave to which controller has to 121 * communicate with 122 */ 123 void spi_free_slave(struct spi_slave *slave) 124 { 125 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); 126 127 free(spi_slave); 128 } 129 130 /** 131 * Flush spi tx, rx fifos and reset the SPI controller 132 * 133 * @param slave Pointer to spi_slave to which controller has to 134 * communicate with 135 */ 136 static void spi_flush_fifo(struct spi_slave *slave) 137 { 138 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); 139 struct exynos_spi *regs = spi_slave->regs; 140 141 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); 142 clrbits_le32(®s->ch_cfg, SPI_CH_RST); 143 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); 144 } 145 146 /** 147 * Initialize the spi base registers, set the required clock frequency and 148 * initialize the gpios 149 * 150 * @param slave Pointer to spi_slave to which controller has to 151 * communicate with 152 * @return zero on success else a negative value 153 */ 154 int spi_claim_bus(struct spi_slave *slave) 155 { 156 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); 157 struct exynos_spi *regs = spi_slave->regs; 158 u32 reg = 0; 159 int ret; 160 161 ret = set_spi_clk(spi_slave->periph_id, 162 spi_slave->freq); 163 if (ret < 0) { 164 debug("%s: Failed to setup spi clock\n", __func__); 165 return ret; 166 } 167 168 exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE); 169 170 spi_flush_fifo(slave); 171 172 reg = readl(®s->ch_cfg); 173 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); 174 175 if (spi_slave->mode & SPI_CPHA) 176 reg |= SPI_CH_CPHA_B; 177 178 if (spi_slave->mode & SPI_CPOL) 179 reg |= SPI_CH_CPOL_L; 180 181 writel(reg, ®s->ch_cfg); 182 writel(SPI_FB_DELAY_180, ®s->fb_clk); 183 184 return 0; 185 } 186 187 /** 188 * Reset the spi H/W and flush the tx and rx fifos 189 * 190 * @param slave Pointer to spi_slave to which controller has to 191 * communicate with 192 */ 193 void spi_release_bus(struct spi_slave *slave) 194 { 195 spi_flush_fifo(slave); 196 } 197 198 static void spi_get_fifo_levels(struct exynos_spi *regs, 199 int *rx_lvl, int *tx_lvl) 200 { 201 uint32_t spi_sts = readl(®s->spi_sts); 202 203 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; 204 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; 205 } 206 207 /** 208 * If there's something to transfer, do a software reset and set a 209 * transaction size. 210 * 211 * @param regs SPI peripheral registers 212 * @param count Number of bytes to transfer 213 */ 214 static void spi_request_bytes(struct exynos_spi *regs, int count) 215 { 216 assert(count && count < (1 << 16)); 217 setbits_le32(®s->ch_cfg, SPI_CH_RST); 218 clrbits_le32(®s->ch_cfg, SPI_CH_RST); 219 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt); 220 } 221 222 static void spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, 223 void **dinp, void const **doutp) 224 { 225 struct exynos_spi *regs = spi_slave->regs; 226 uchar *rxp = *dinp; 227 const uchar *txp = *doutp; 228 int rx_lvl, tx_lvl; 229 uint out_bytes, in_bytes; 230 231 out_bytes = in_bytes = todo; 232 233 /* 234 * If there's something to send, do a software reset and set a 235 * transaction size. 236 */ 237 spi_request_bytes(regs, todo); 238 239 /* 240 * Bytes are transmitted/received in pairs. Wait to receive all the 241 * data because then transmission will be done as well. 242 */ 243 while (in_bytes) { 244 int temp; 245 246 /* Keep the fifos full/empty. */ 247 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); 248 if (tx_lvl < spi_slave->fifo_size && out_bytes) { 249 temp = txp ? *txp++ : 0xff; 250 writel(temp, ®s->tx_data); 251 out_bytes--; 252 } 253 if (rx_lvl > 0 && in_bytes) { 254 temp = readl(®s->rx_data); 255 if (rxp) 256 *rxp++ = temp; 257 in_bytes--; 258 } 259 } 260 *dinp = rxp; 261 *doutp = txp; 262 } 263 264 /** 265 * Transfer and receive data 266 * 267 * @param slave Pointer to spi_slave to which controller has to 268 * communicate with 269 * @param bitlen No of bits to tranfer or receive 270 * @param dout Pointer to transfer buffer 271 * @param din Pointer to receive buffer 272 * @param flags Flags for transfer begin and end 273 * @return zero on success else a negative value 274 */ 275 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 276 void *din, unsigned long flags) 277 { 278 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); 279 int upto, todo; 280 int bytelen; 281 282 /* spi core configured to do 8 bit transfers */ 283 if (bitlen % 8) { 284 debug("Non byte aligned SPI transfer.\n"); 285 return -1; 286 } 287 288 /* Start the transaction, if necessary. */ 289 if ((flags & SPI_XFER_BEGIN)) 290 spi_cs_activate(slave); 291 292 /* Exynos SPI limits each transfer to 65535 bytes */ 293 bytelen = bitlen / 8; 294 for (upto = 0; upto < bytelen; upto += todo) { 295 todo = min(bytelen - upto, (1 << 16) - 1); 296 spi_rx_tx(spi_slave, todo, &din, &dout); 297 } 298 299 /* Stop the transaction, if necessary. */ 300 if ((flags & SPI_XFER_END)) 301 spi_cs_deactivate(slave); 302 303 return 0; 304 } 305 306 /** 307 * Validates the bus and chip select numbers 308 * 309 * @param bus ID of the bus that the slave is attached to 310 * @param cs ID of the chip select connected to the slave 311 * @return one on success else zero 312 */ 313 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 314 { 315 return spi_get_bus(bus) && cs == 0; 316 } 317 318 /** 319 * Activate the CS by driving it LOW 320 * 321 * @param slave Pointer to spi_slave to which controller has to 322 * communicate with 323 */ 324 void spi_cs_activate(struct spi_slave *slave) 325 { 326 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); 327 328 clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); 329 debug("Activate CS, bus %d\n", spi_slave->slave.bus); 330 } 331 332 /** 333 * Deactivate the CS by driving it HIGH 334 * 335 * @param slave Pointer to spi_slave to which controller has to 336 * communicate with 337 */ 338 void spi_cs_deactivate(struct spi_slave *slave) 339 { 340 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave); 341 342 setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT); 343 debug("Deactivate CS, bus %d\n", spi_slave->slave.bus); 344 } 345 346 static inline struct exynos_spi *get_spi_base(int dev_index) 347 { 348 if (dev_index < 3) 349 return (struct exynos_spi *)samsung_get_base_spi() + dev_index; 350 else 351 return (struct exynos_spi *)samsung_get_base_spi_isp() + 352 (dev_index - 3); 353 } 354 355 /* 356 * Read the SPI config from the device tree node. 357 * 358 * @param blob FDT blob to read from 359 * @param node Node offset to read from 360 * @param bus SPI bus structure to fill with information 361 * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing 362 */ 363 static int spi_get_config(const void *blob, int node, struct spi_bus *bus) 364 { 365 bus->node = node; 366 bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg"); 367 bus->periph_id = pinmux_decode_periph_id(blob, node); 368 369 if (bus->periph_id == PERIPH_ID_NONE) { 370 debug("%s: Invalid peripheral ID %d\n", __func__, 371 bus->periph_id); 372 return -FDT_ERR_NOTFOUND; 373 } 374 375 /* Use 500KHz as a suitable default */ 376 bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 377 500000); 378 379 return 0; 380 } 381 382 /* 383 * Process a list of nodes, adding them to our list of SPI ports. 384 * 385 * @param blob fdt blob 386 * @param node_list list of nodes to process (any <=0 are ignored) 387 * @param count number of nodes to process 388 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C 389 * @return 0 if ok, -1 on error 390 */ 391 static int process_nodes(const void *blob, int node_list[], int count) 392 { 393 int i; 394 395 /* build the i2c_controllers[] for each controller */ 396 for (i = 0; i < count; i++) { 397 int node = node_list[i]; 398 struct spi_bus *bus; 399 400 if (node <= 0) 401 continue; 402 403 bus = &spi_bus[i]; 404 if (spi_get_config(blob, node, bus)) { 405 printf("exynos spi_init: failed to decode bus %d\n", 406 i); 407 return -1; 408 } 409 410 debug("spi: controller bus %d at %p, periph_id %d\n", 411 i, bus->regs, bus->periph_id); 412 bus->inited = 1; 413 bus_count++; 414 } 415 416 return 0; 417 } 418 419 /* Sadly there is no error return from this function */ 420 void spi_init(void) 421 { 422 int count; 423 424 #ifdef CONFIG_OF_CONTROL 425 int node_list[EXYNOS5_SPI_NUM_CONTROLLERS]; 426 const void *blob = gd->fdt_blob; 427 428 count = fdtdec_find_aliases_for_id(blob, "spi", 429 COMPAT_SAMSUNG_EXYNOS_SPI, node_list, 430 EXYNOS5_SPI_NUM_CONTROLLERS); 431 if (process_nodes(blob, node_list, count)) 432 return; 433 434 #else 435 struct spi_bus *bus; 436 437 for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) { 438 bus = &spi_bus[count]; 439 bus->regs = get_spi_base(count); 440 bus->periph_id = PERIPH_ID_SPI0 + count; 441 442 /* Although Exynos5 supports upto 50Mhz speed, 443 * we are setting it to 10Mhz for safe side 444 */ 445 bus->frequency = 10000000; 446 bus->inited = 1; 447 bus->node = 0; 448 bus_count = EXYNOS5_SPI_NUM_CONTROLLERS; 449 } 450 #endif 451 } 452