1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Padmavathi Venna <padma.v@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <malloc.h> 12 #include <spi.h> 13 #include <fdtdec.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/pinmux.h> 19 #include <asm/arch/spi.h> 20 #include <asm/io.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct exynos_spi_platdata { 25 enum periph_id periph_id; 26 s32 frequency; /* Default clock frequency, -1 for none */ 27 struct exynos_spi *regs; 28 uint deactivate_delay_us; /* Delay to wait after deactivate */ 29 }; 30 31 struct exynos_spi_priv { 32 struct exynos_spi *regs; 33 unsigned int freq; /* Default frequency */ 34 unsigned int mode; 35 enum periph_id periph_id; /* Peripheral ID for this device */ 36 unsigned int fifo_size; 37 int skip_preamble; 38 ulong last_transaction_us; /* Time of last transaction end */ 39 }; 40 41 /** 42 * Flush spi tx, rx fifos and reset the SPI controller 43 * 44 * @param regs Pointer to SPI registers 45 */ 46 static void spi_flush_fifo(struct exynos_spi *regs) 47 { 48 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); 49 clrbits_le32(®s->ch_cfg, SPI_CH_RST); 50 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); 51 } 52 53 static void spi_get_fifo_levels(struct exynos_spi *regs, 54 int *rx_lvl, int *tx_lvl) 55 { 56 uint32_t spi_sts = readl(®s->spi_sts); 57 58 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; 59 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; 60 } 61 62 /** 63 * If there's something to transfer, do a software reset and set a 64 * transaction size. 65 * 66 * @param regs SPI peripheral registers 67 * @param count Number of bytes to transfer 68 * @param step Number of bytes to transfer in each packet (1 or 4) 69 */ 70 static void spi_request_bytes(struct exynos_spi *regs, int count, int step) 71 { 72 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step); 73 74 /* For word address we need to swap bytes */ 75 if (step == 4) { 76 setbits_le32(®s->mode_cfg, 77 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); 78 count /= 4; 79 setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | 80 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | 81 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); 82 } else { 83 /* Select byte access and clear the swap configuration */ 84 clrbits_le32(®s->mode_cfg, 85 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); 86 writel(0, ®s->swap_cfg); 87 } 88 89 assert(count && count < (1 << 16)); 90 setbits_le32(®s->ch_cfg, SPI_CH_RST); 91 clrbits_le32(®s->ch_cfg, SPI_CH_RST); 92 93 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt); 94 } 95 96 static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, 97 void **dinp, void const **doutp, unsigned long flags) 98 { 99 struct exynos_spi *regs = priv->regs; 100 uchar *rxp = *dinp; 101 const uchar *txp = *doutp; 102 int rx_lvl, tx_lvl; 103 uint out_bytes, in_bytes; 104 int toread; 105 unsigned start = get_timer(0); 106 int stopping; 107 int step; 108 109 out_bytes = in_bytes = todo; 110 111 stopping = priv->skip_preamble && (flags & SPI_XFER_END) && 112 !(priv->mode & SPI_SLAVE); 113 114 /* 115 * Try to transfer words if we can. This helps read performance at 116 * SPI clock speeds above about 20MHz. 117 */ 118 step = 1; 119 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) && 120 !priv->skip_preamble) 121 step = 4; 122 123 /* 124 * If there's something to send, do a software reset and set a 125 * transaction size. 126 */ 127 spi_request_bytes(regs, todo, step); 128 129 /* 130 * Bytes are transmitted/received in pairs. Wait to receive all the 131 * data because then transmission will be done as well. 132 */ 133 toread = in_bytes; 134 135 while (in_bytes) { 136 int temp; 137 138 /* Keep the fifos full/empty. */ 139 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); 140 141 /* 142 * Don't completely fill the txfifo, since we don't want our 143 * rxfifo to overflow, and it may already contain data. 144 */ 145 while (tx_lvl < priv->fifo_size/2 && out_bytes) { 146 if (!txp) 147 temp = -1; 148 else if (step == 4) 149 temp = *(uint32_t *)txp; 150 else 151 temp = *txp; 152 writel(temp, ®s->tx_data); 153 out_bytes -= step; 154 if (txp) 155 txp += step; 156 tx_lvl += step; 157 } 158 if (rx_lvl >= step) { 159 while (rx_lvl >= step) { 160 temp = readl(®s->rx_data); 161 if (priv->skip_preamble) { 162 if (temp == SPI_PREAMBLE_END_BYTE) { 163 priv->skip_preamble = 0; 164 stopping = 0; 165 } 166 } else { 167 if (rxp || stopping) { 168 if (step == 4) 169 *(uint32_t *)rxp = temp; 170 else 171 *rxp = temp; 172 rxp += step; 173 } 174 in_bytes -= step; 175 } 176 toread -= step; 177 rx_lvl -= step; 178 } 179 } else if (!toread) { 180 /* 181 * We have run out of input data, but haven't read 182 * enough bytes after the preamble yet. Read some more, 183 * and make sure that we transmit dummy bytes too, to 184 * keep things going. 185 */ 186 assert(!out_bytes); 187 out_bytes = in_bytes; 188 toread = in_bytes; 189 txp = NULL; 190 spi_request_bytes(regs, toread, step); 191 } 192 if (priv->skip_preamble && get_timer(start) > 100) { 193 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ", 194 in_bytes, out_bytes); 195 return -ETIMEDOUT; 196 } 197 } 198 199 *dinp = rxp; 200 *doutp = txp; 201 202 return 0; 203 } 204 205 /** 206 * Activate the CS by driving it LOW 207 * 208 * @param slave Pointer to spi_slave to which controller has to 209 * communicate with 210 */ 211 static void spi_cs_activate(struct udevice *dev) 212 { 213 struct udevice *bus = dev->parent; 214 struct exynos_spi_platdata *pdata = dev_get_platdata(bus); 215 struct exynos_spi_priv *priv = dev_get_priv(bus); 216 217 /* If it's too soon to do another transaction, wait */ 218 if (pdata->deactivate_delay_us && 219 priv->last_transaction_us) { 220 ulong delay_us; /* The delay completed so far */ 221 delay_us = timer_get_us() - priv->last_transaction_us; 222 if (delay_us < pdata->deactivate_delay_us) 223 udelay(pdata->deactivate_delay_us - delay_us); 224 } 225 226 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); 227 debug("Activate CS, bus '%s'\n", bus->name); 228 priv->skip_preamble = priv->mode & SPI_PREAMBLE; 229 } 230 231 /** 232 * Deactivate the CS by driving it HIGH 233 * 234 * @param slave Pointer to spi_slave to which controller has to 235 * communicate with 236 */ 237 static void spi_cs_deactivate(struct udevice *dev) 238 { 239 struct udevice *bus = dev->parent; 240 struct exynos_spi_platdata *pdata = dev_get_platdata(bus); 241 struct exynos_spi_priv *priv = dev_get_priv(bus); 242 243 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); 244 245 /* Remember time of this transaction so we can honour the bus delay */ 246 if (pdata->deactivate_delay_us) 247 priv->last_transaction_us = timer_get_us(); 248 249 debug("Deactivate CS, bus '%s'\n", bus->name); 250 } 251 252 static int exynos_spi_ofdata_to_platdata(struct udevice *bus) 253 { 254 struct exynos_spi_platdata *plat = bus->platdata; 255 const void *blob = gd->fdt_blob; 256 int node = dev_of_offset(bus); 257 258 plat->regs = (struct exynos_spi *)devfdt_get_addr(bus); 259 plat->periph_id = pinmux_decode_periph_id(blob, node); 260 261 if (plat->periph_id == PERIPH_ID_NONE) { 262 debug("%s: Invalid peripheral ID %d\n", __func__, 263 plat->periph_id); 264 return -FDT_ERR_NOTFOUND; 265 } 266 267 /* Use 500KHz as a suitable default */ 268 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 269 500000); 270 plat->deactivate_delay_us = fdtdec_get_int(blob, node, 271 "spi-deactivate-delay", 0); 272 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", 273 __func__, plat->regs, plat->periph_id, plat->frequency, 274 plat->deactivate_delay_us); 275 276 return 0; 277 } 278 279 static int exynos_spi_probe(struct udevice *bus) 280 { 281 struct exynos_spi_platdata *plat = dev_get_platdata(bus); 282 struct exynos_spi_priv *priv = dev_get_priv(bus); 283 284 priv->regs = plat->regs; 285 if (plat->periph_id == PERIPH_ID_SPI1 || 286 plat->periph_id == PERIPH_ID_SPI2) 287 priv->fifo_size = 64; 288 else 289 priv->fifo_size = 256; 290 291 priv->skip_preamble = 0; 292 priv->last_transaction_us = timer_get_us(); 293 priv->freq = plat->frequency; 294 priv->periph_id = plat->periph_id; 295 296 return 0; 297 } 298 299 static int exynos_spi_claim_bus(struct udevice *dev) 300 { 301 struct udevice *bus = dev->parent; 302 struct exynos_spi_priv *priv = dev_get_priv(bus); 303 304 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE); 305 spi_flush_fifo(priv->regs); 306 307 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk); 308 309 return 0; 310 } 311 312 static int exynos_spi_release_bus(struct udevice *dev) 313 { 314 struct udevice *bus = dev->parent; 315 struct exynos_spi_priv *priv = dev_get_priv(bus); 316 317 spi_flush_fifo(priv->regs); 318 319 return 0; 320 } 321 322 static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen, 323 const void *dout, void *din, unsigned long flags) 324 { 325 struct udevice *bus = dev->parent; 326 struct exynos_spi_priv *priv = dev_get_priv(bus); 327 int upto, todo; 328 int bytelen; 329 int ret = 0; 330 331 /* spi core configured to do 8 bit transfers */ 332 if (bitlen % 8) { 333 debug("Non byte aligned SPI transfer.\n"); 334 return -1; 335 } 336 337 /* Start the transaction, if necessary. */ 338 if ((flags & SPI_XFER_BEGIN)) 339 spi_cs_activate(dev); 340 341 /* 342 * Exynos SPI limits each transfer to 65535 transfers. To keep 343 * things simple, allow a maximum of 65532 bytes. We could allow 344 * more in word mode, but the performance difference is small. 345 */ 346 bytelen = bitlen / 8; 347 for (upto = 0; !ret && upto < bytelen; upto += todo) { 348 todo = min(bytelen - upto, (1 << 16) - 4); 349 ret = spi_rx_tx(priv, todo, &din, &dout, flags); 350 if (ret) 351 break; 352 } 353 354 /* Stop the transaction, if necessary. */ 355 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) { 356 spi_cs_deactivate(dev); 357 if (priv->skip_preamble) { 358 assert(!priv->skip_preamble); 359 debug("Failed to complete premable transaction\n"); 360 ret = -1; 361 } 362 } 363 364 return ret; 365 } 366 367 static int exynos_spi_set_speed(struct udevice *bus, uint speed) 368 { 369 struct exynos_spi_platdata *plat = bus->platdata; 370 struct exynos_spi_priv *priv = dev_get_priv(bus); 371 int ret; 372 373 if (speed > plat->frequency) 374 speed = plat->frequency; 375 ret = set_spi_clk(priv->periph_id, speed); 376 if (ret) 377 return ret; 378 priv->freq = speed; 379 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); 380 381 return 0; 382 } 383 384 static int exynos_spi_set_mode(struct udevice *bus, uint mode) 385 { 386 struct exynos_spi_priv *priv = dev_get_priv(bus); 387 uint32_t reg; 388 389 reg = readl(&priv->regs->ch_cfg); 390 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); 391 392 if (mode & SPI_CPHA) 393 reg |= SPI_CH_CPHA_B; 394 395 if (mode & SPI_CPOL) 396 reg |= SPI_CH_CPOL_L; 397 398 writel(reg, &priv->regs->ch_cfg); 399 priv->mode = mode; 400 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 401 402 return 0; 403 } 404 405 static const struct dm_spi_ops exynos_spi_ops = { 406 .claim_bus = exynos_spi_claim_bus, 407 .release_bus = exynos_spi_release_bus, 408 .xfer = exynos_spi_xfer, 409 .set_speed = exynos_spi_set_speed, 410 .set_mode = exynos_spi_set_mode, 411 /* 412 * cs_info is not needed, since we require all chip selects to be 413 * in the device tree explicitly 414 */ 415 }; 416 417 static const struct udevice_id exynos_spi_ids[] = { 418 { .compatible = "samsung,exynos-spi" }, 419 { } 420 }; 421 422 U_BOOT_DRIVER(exynos_spi) = { 423 .name = "exynos_spi", 424 .id = UCLASS_SPI, 425 .of_match = exynos_spi_ids, 426 .ops = &exynos_spi_ops, 427 .ofdata_to_platdata = exynos_spi_ofdata_to_platdata, 428 .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata), 429 .priv_auto_alloc_size = sizeof(struct exynos_spi_priv), 430 .probe = exynos_spi_probe, 431 }; 432