xref: /openbmc/u-boot/drivers/spi/designware_spi.c (revision 3ba98ed8) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Designware master SPI core controller driver
4  *
5  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6  *
7  * Very loosely based on the Linux driver:
8  * drivers/spi/spi-dw.c, which is:
9  * Copyright (c) 2009, Intel Corporation.
10  */
11 
12 #include <common.h>
13 #include <asm-generic/gpio.h>
14 #include <clk.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <malloc.h>
18 #include <spi.h>
19 #include <fdtdec.h>
20 #include <reset.h>
21 #include <linux/compat.h>
22 #include <linux/iopoll.h>
23 #include <asm/io.h>
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 /* Register offsets */
28 #define DW_SPI_CTRL0			0x00
29 #define DW_SPI_CTRL1			0x04
30 #define DW_SPI_SSIENR			0x08
31 #define DW_SPI_MWCR			0x0c
32 #define DW_SPI_SER			0x10
33 #define DW_SPI_BAUDR			0x14
34 #define DW_SPI_TXFLTR			0x18
35 #define DW_SPI_RXFLTR			0x1c
36 #define DW_SPI_TXFLR			0x20
37 #define DW_SPI_RXFLR			0x24
38 #define DW_SPI_SR			0x28
39 #define DW_SPI_IMR			0x2c
40 #define DW_SPI_ISR			0x30
41 #define DW_SPI_RISR			0x34
42 #define DW_SPI_TXOICR			0x38
43 #define DW_SPI_RXOICR			0x3c
44 #define DW_SPI_RXUICR			0x40
45 #define DW_SPI_MSTICR			0x44
46 #define DW_SPI_ICR			0x48
47 #define DW_SPI_DMACR			0x4c
48 #define DW_SPI_DMATDLR			0x50
49 #define DW_SPI_DMARDLR			0x54
50 #define DW_SPI_IDR			0x58
51 #define DW_SPI_VERSION			0x5c
52 #define DW_SPI_DR			0x60
53 
54 /* Bit fields in CTRLR0 */
55 #define SPI_DFS_OFFSET			0
56 
57 #define SPI_FRF_OFFSET			4
58 #define SPI_FRF_SPI			0x0
59 #define SPI_FRF_SSP			0x1
60 #define SPI_FRF_MICROWIRE		0x2
61 #define SPI_FRF_RESV			0x3
62 
63 #define SPI_MODE_OFFSET			6
64 #define SPI_SCPH_OFFSET			6
65 #define SPI_SCOL_OFFSET			7
66 
67 #define SPI_TMOD_OFFSET			8
68 #define SPI_TMOD_MASK			(0x3 << SPI_TMOD_OFFSET)
69 #define	SPI_TMOD_TR			0x0		/* xmit & recv */
70 #define SPI_TMOD_TO			0x1		/* xmit only */
71 #define SPI_TMOD_RO			0x2		/* recv only */
72 #define SPI_TMOD_EPROMREAD		0x3		/* eeprom read mode */
73 
74 #define SPI_SLVOE_OFFSET		10
75 #define SPI_SRL_OFFSET			11
76 #define SPI_CFS_OFFSET			12
77 
78 /* Bit fields in SR, 7 bits */
79 #define SR_MASK				GENMASK(6, 0)	/* cover 7 bits */
80 #define SR_BUSY				BIT(0)
81 #define SR_TF_NOT_FULL			BIT(1)
82 #define SR_TF_EMPT			BIT(2)
83 #define SR_RF_NOT_EMPT			BIT(3)
84 #define SR_RF_FULL			BIT(4)
85 #define SR_TX_ERR			BIT(5)
86 #define SR_DCOL				BIT(6)
87 
88 #define RX_TIMEOUT			1000		/* timeout in ms */
89 
90 struct dw_spi_platdata {
91 	s32 frequency;		/* Default clock frequency, -1 for none */
92 	void __iomem *regs;
93 };
94 
95 struct dw_spi_priv {
96 	void __iomem *regs;
97 	unsigned int freq;		/* Default frequency */
98 	unsigned int mode;
99 	struct clk clk;
100 	unsigned long bus_clk_rate;
101 
102 	struct gpio_desc cs_gpio;	/* External chip-select gpio */
103 
104 	int bits_per_word;
105 	u8 cs;			/* chip select pin */
106 	u8 tmode;		/* TR/TO/RO/EEPROM */
107 	u8 type;		/* SPI/SSP/MicroWire */
108 	int len;
109 
110 	u32 fifo_len;		/* depth of the FIFO buffer */
111 	void *tx;
112 	void *tx_end;
113 	void *rx;
114 	void *rx_end;
115 
116 	struct reset_ctl_bulk	resets;
117 };
118 
119 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
120 {
121 	return __raw_readl(priv->regs + offset);
122 }
123 
124 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
125 {
126 	__raw_writel(val, priv->regs + offset);
127 }
128 
129 static int request_gpio_cs(struct udevice *bus)
130 {
131 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
132 	struct dw_spi_priv *priv = dev_get_priv(bus);
133 	int ret;
134 
135 	/* External chip select gpio line is optional */
136 	ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
137 	if (ret == -ENOENT)
138 		return 0;
139 
140 	if (ret < 0) {
141 		printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
142 		return ret;
143 	}
144 
145 	if (dm_gpio_is_valid(&priv->cs_gpio)) {
146 		dm_gpio_set_dir_flags(&priv->cs_gpio,
147 				      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
148 	}
149 
150 	debug("%s: used external gpio for CS management\n", __func__);
151 #endif
152 	return 0;
153 }
154 
155 static int dw_spi_ofdata_to_platdata(struct udevice *bus)
156 {
157 	struct dw_spi_platdata *plat = bus->platdata;
158 	const void *blob = gd->fdt_blob;
159 	int node = dev_of_offset(bus);
160 
161 	plat->regs = (struct dw_spi *)devfdt_get_addr(bus);
162 
163 	/* Use 500KHz as a suitable default */
164 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
165 					500000);
166 	debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
167 	      plat->frequency);
168 
169 	return request_gpio_cs(bus);
170 }
171 
172 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
173 {
174 	dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
175 }
176 
177 /* Restart the controller, disable all interrupts, clean rx fifo */
178 static void spi_hw_init(struct dw_spi_priv *priv)
179 {
180 	spi_enable_chip(priv, 0);
181 	dw_write(priv, DW_SPI_IMR, 0xff);
182 	spi_enable_chip(priv, 1);
183 
184 	/*
185 	 * Try to detect the FIFO depth if not set by interface driver,
186 	 * the depth could be from 2 to 256 from HW spec
187 	 */
188 	if (!priv->fifo_len) {
189 		u32 fifo;
190 
191 		for (fifo = 1; fifo < 256; fifo++) {
192 			dw_write(priv, DW_SPI_TXFLTR, fifo);
193 			if (fifo != dw_read(priv, DW_SPI_TXFLTR))
194 				break;
195 		}
196 
197 		priv->fifo_len = (fifo == 1) ? 0 : fifo;
198 		dw_write(priv, DW_SPI_TXFLTR, 0);
199 	}
200 	debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
201 }
202 
203 /*
204  * We define dw_spi_get_clk function as 'weak' as some targets
205  * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
206  * and implement dw_spi_get_clk their own way in their clock manager.
207  */
208 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
209 {
210 	struct dw_spi_priv *priv = dev_get_priv(bus);
211 	int ret;
212 
213 	ret = clk_get_by_index(bus, 0, &priv->clk);
214 	if (ret)
215 		return ret;
216 
217 	ret = clk_enable(&priv->clk);
218 	if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
219 		return ret;
220 
221 	*rate = clk_get_rate(&priv->clk);
222 	if (!*rate)
223 		goto err_rate;
224 
225 	debug("%s: get spi controller clk via device tree: %lu Hz\n",
226 	      __func__, *rate);
227 
228 	return 0;
229 
230 err_rate:
231 	clk_disable(&priv->clk);
232 	clk_free(&priv->clk);
233 
234 	return -EINVAL;
235 }
236 
237 static int dw_spi_reset(struct udevice *bus)
238 {
239 	int ret;
240 	struct dw_spi_priv *priv = dev_get_priv(bus);
241 
242 	ret = reset_get_bulk(bus, &priv->resets);
243 	if (ret) {
244 		/*
245 		 * Return 0 if error due to !CONFIG_DM_RESET and reset
246 		 * DT property is not present.
247 		 */
248 		if (ret == -ENOENT || ret == -ENOTSUPP)
249 			return 0;
250 
251 		dev_warn(bus, "Can't get reset: %d\n", ret);
252 		return ret;
253 	}
254 
255 	ret = reset_deassert_bulk(&priv->resets);
256 	if (ret) {
257 		reset_release_bulk(&priv->resets);
258 		dev_err(bus, "Failed to reset: %d\n", ret);
259 		return ret;
260 	}
261 
262 	return 0;
263 }
264 
265 static int dw_spi_probe(struct udevice *bus)
266 {
267 	struct dw_spi_platdata *plat = dev_get_platdata(bus);
268 	struct dw_spi_priv *priv = dev_get_priv(bus);
269 	int ret;
270 
271 	priv->regs = plat->regs;
272 	priv->freq = plat->frequency;
273 
274 	ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
275 	if (ret)
276 		return ret;
277 
278 	ret = dw_spi_reset(bus);
279 	if (ret)
280 		return ret;
281 
282 	/* Currently only bits_per_word == 8 supported */
283 	priv->bits_per_word = 8;
284 
285 	priv->tmode = 0; /* Tx & Rx */
286 
287 	/* Basic HW init */
288 	spi_hw_init(priv);
289 
290 	return 0;
291 }
292 
293 /* Return the max entries we can fill into tx fifo */
294 static inline u32 tx_max(struct dw_spi_priv *priv)
295 {
296 	u32 tx_left, tx_room, rxtx_gap;
297 
298 	tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
299 	tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
300 
301 	/*
302 	 * Another concern is about the tx/rx mismatch, we
303 	 * thought about using (priv->fifo_len - rxflr - txflr) as
304 	 * one maximum value for tx, but it doesn't cover the
305 	 * data which is out of tx/rx fifo and inside the
306 	 * shift registers. So a control from sw point of
307 	 * view is taken.
308 	 */
309 	rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
310 		(priv->bits_per_word >> 3);
311 
312 	return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
313 }
314 
315 /* Return the max entries we should read out of rx fifo */
316 static inline u32 rx_max(struct dw_spi_priv *priv)
317 {
318 	u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
319 
320 	return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
321 }
322 
323 static void dw_writer(struct dw_spi_priv *priv)
324 {
325 	u32 max = tx_max(priv);
326 	u16 txw = 0;
327 
328 	while (max--) {
329 		/* Set the tx word if the transfer's original "tx" is not null */
330 		if (priv->tx_end - priv->len) {
331 			if (priv->bits_per_word == 8)
332 				txw = *(u8 *)(priv->tx);
333 			else
334 				txw = *(u16 *)(priv->tx);
335 		}
336 		dw_write(priv, DW_SPI_DR, txw);
337 		debug("%s: tx=0x%02x\n", __func__, txw);
338 		priv->tx += priv->bits_per_word >> 3;
339 	}
340 }
341 
342 static void dw_reader(struct dw_spi_priv *priv)
343 {
344 	u32 max = rx_max(priv);
345 	u16 rxw;
346 
347 	while (max--) {
348 		rxw = dw_read(priv, DW_SPI_DR);
349 		debug("%s: rx=0x%02x\n", __func__, rxw);
350 
351 		/* Care about rx if the transfer's original "rx" is not null */
352 		if (priv->rx_end - priv->len) {
353 			if (priv->bits_per_word == 8)
354 				*(u8 *)(priv->rx) = rxw;
355 			else
356 				*(u16 *)(priv->rx) = rxw;
357 		}
358 		priv->rx += priv->bits_per_word >> 3;
359 	}
360 }
361 
362 static int poll_transfer(struct dw_spi_priv *priv)
363 {
364 	do {
365 		dw_writer(priv);
366 		dw_reader(priv);
367 	} while (priv->rx_end > priv->rx);
368 
369 	return 0;
370 }
371 
372 /*
373  * We define external_cs_manage function as 'weak' as some targets
374  * (like MSCC Ocelot) don't control the external CS pin using a GPIO
375  * controller. These SoCs use specific registers to control by
376  * software the SPI pins (and especially the CS).
377  */
378 __weak void external_cs_manage(struct udevice *dev, bool on)
379 {
380 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
381 	struct dw_spi_priv *priv = dev_get_priv(dev->parent);
382 
383 	if (!dm_gpio_is_valid(&priv->cs_gpio))
384 		return;
385 
386 	dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
387 #endif
388 }
389 
390 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
391 		       const void *dout, void *din, unsigned long flags)
392 {
393 	struct udevice *bus = dev->parent;
394 	struct dw_spi_priv *priv = dev_get_priv(bus);
395 	const u8 *tx = dout;
396 	u8 *rx = din;
397 	int ret = 0;
398 	u32 cr0 = 0;
399 	u32 val;
400 	u32 cs;
401 
402 	/* spi core configured to do 8 bit transfers */
403 	if (bitlen % 8) {
404 		debug("Non byte aligned SPI transfer.\n");
405 		return -1;
406 	}
407 
408 	/* Start the transaction if necessary. */
409 	if (flags & SPI_XFER_BEGIN)
410 		external_cs_manage(dev, false);
411 
412 	cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
413 		(priv->mode << SPI_MODE_OFFSET) |
414 		(priv->tmode << SPI_TMOD_OFFSET);
415 
416 	if (rx && tx)
417 		priv->tmode = SPI_TMOD_TR;
418 	else if (rx)
419 		priv->tmode = SPI_TMOD_RO;
420 	else
421 		/*
422 		 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
423 		 * any data which breaks our logic in poll_transfer() above.
424 		 */
425 		priv->tmode = SPI_TMOD_TR;
426 
427 	cr0 &= ~SPI_TMOD_MASK;
428 	cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
429 
430 	priv->len = bitlen >> 3;
431 	debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
432 
433 	priv->tx = (void *)tx;
434 	priv->tx_end = priv->tx + priv->len;
435 	priv->rx = rx;
436 	priv->rx_end = priv->rx + priv->len;
437 
438 	/* Disable controller before writing control registers */
439 	spi_enable_chip(priv, 0);
440 
441 	debug("%s: cr0=%08x\n", __func__, cr0);
442 	/* Reprogram cr0 only if changed */
443 	if (dw_read(priv, DW_SPI_CTRL0) != cr0)
444 		dw_write(priv, DW_SPI_CTRL0, cr0);
445 
446 	/*
447 	 * Configure the desired SS (slave select 0...3) in the controller
448 	 * The DW SPI controller will activate and deactivate this CS
449 	 * automatically. So no cs_activate() etc is needed in this driver.
450 	 */
451 	cs = spi_chip_select(dev);
452 	dw_write(priv, DW_SPI_SER, 1 << cs);
453 
454 	/* Enable controller after writing control registers */
455 	spi_enable_chip(priv, 1);
456 
457 	/* Start transfer in a polling loop */
458 	ret = poll_transfer(priv);
459 
460 	/*
461 	 * Wait for current transmit operation to complete.
462 	 * Otherwise if some data still exists in Tx FIFO it can be
463 	 * silently flushed, i.e. dropped on disabling of the controller,
464 	 * which happens when writing 0 to DW_SPI_SSIENR which happens
465 	 * in the beginning of new transfer.
466 	 */
467 	if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
468 			       (val & SR_TF_EMPT) && !(val & SR_BUSY),
469 			       RX_TIMEOUT * 1000)) {
470 		ret = -ETIMEDOUT;
471 	}
472 
473 	/* Stop the transaction if necessary */
474 	if (flags & SPI_XFER_END)
475 		external_cs_manage(dev, true);
476 
477 	return ret;
478 }
479 
480 static int dw_spi_set_speed(struct udevice *bus, uint speed)
481 {
482 	struct dw_spi_platdata *plat = bus->platdata;
483 	struct dw_spi_priv *priv = dev_get_priv(bus);
484 	u16 clk_div;
485 
486 	if (speed > plat->frequency)
487 		speed = plat->frequency;
488 
489 	/* Disable controller before writing control registers */
490 	spi_enable_chip(priv, 0);
491 
492 	/* clk_div doesn't support odd number */
493 	clk_div = priv->bus_clk_rate / speed;
494 	clk_div = (clk_div + 1) & 0xfffe;
495 	dw_write(priv, DW_SPI_BAUDR, clk_div);
496 
497 	/* Enable controller after writing control registers */
498 	spi_enable_chip(priv, 1);
499 
500 	priv->freq = speed;
501 	debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
502 	      priv->freq, clk_div);
503 
504 	return 0;
505 }
506 
507 static int dw_spi_set_mode(struct udevice *bus, uint mode)
508 {
509 	struct dw_spi_priv *priv = dev_get_priv(bus);
510 
511 	/*
512 	 * Can't set mode yet. Since this depends on if rx, tx, or
513 	 * rx & tx is requested. So we have to defer this to the
514 	 * real transfer function.
515 	 */
516 	priv->mode = mode;
517 	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
518 
519 	return 0;
520 }
521 
522 static int dw_spi_remove(struct udevice *bus)
523 {
524 	struct dw_spi_priv *priv = dev_get_priv(bus);
525 
526 	return reset_release_bulk(&priv->resets);
527 }
528 
529 static const struct dm_spi_ops dw_spi_ops = {
530 	.xfer		= dw_spi_xfer,
531 	.set_speed	= dw_spi_set_speed,
532 	.set_mode	= dw_spi_set_mode,
533 	/*
534 	 * cs_info is not needed, since we require all chip selects to be
535 	 * in the device tree explicitly
536 	 */
537 };
538 
539 static const struct udevice_id dw_spi_ids[] = {
540 	{ .compatible = "snps,dw-apb-ssi" },
541 	{ }
542 };
543 
544 U_BOOT_DRIVER(dw_spi) = {
545 	.name = "dw_spi",
546 	.id = UCLASS_SPI,
547 	.of_match = dw_spi_ids,
548 	.ops = &dw_spi_ops,
549 	.ofdata_to_platdata = dw_spi_ofdata_to_platdata,
550 	.platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
551 	.priv_auto_alloc_size = sizeof(struct dw_spi_priv),
552 	.probe = dw_spi_probe,
553 	.remove = dw_spi_remove,
554 };
555