xref: /openbmc/u-boot/drivers/spi/davinci_spi.c (revision ef64e782) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Driver for SPI controller on DaVinci. Based on atmel_spi.c
6  * by Atmel Corporation
7  *
8  * Copyright (C) 2007 Atmel Corporation
9  */
10 
11 #include <common.h>
12 #include <spi.h>
13 #include <malloc.h>
14 #include <asm/io.h>
15 #include <asm/arch/hardware.h>
16 #include <dm.h>
17 
18 /* SPIGCR0 */
19 #define SPIGCR0_SPIENA_MASK	0x1
20 #define SPIGCR0_SPIRST_MASK	0x0
21 
22 /* SPIGCR0 */
23 #define SPIGCR1_CLKMOD_MASK	BIT(1)
24 #define SPIGCR1_MASTER_MASK	BIT(0)
25 #define SPIGCR1_SPIENA_MASK	BIT(24)
26 
27 /* SPIPC0 */
28 #define SPIPC0_DIFUN_MASK	BIT(11)		/* SIMO */
29 #define SPIPC0_DOFUN_MASK	BIT(10)		/* SOMI */
30 #define SPIPC0_CLKFUN_MASK	BIT(9)		/* CLK */
31 #define SPIPC0_EN0FUN_MASK	BIT(0)
32 
33 /* SPIFMT0 */
34 #define SPIFMT_SHIFTDIR_SHIFT	20
35 #define SPIFMT_POLARITY_SHIFT	17
36 #define SPIFMT_PHASE_SHIFT	16
37 #define SPIFMT_PRESCALE_SHIFT	8
38 
39 /* SPIDAT1 */
40 #define SPIDAT1_CSHOLD_SHIFT	28
41 #define SPIDAT1_CSNR_SHIFT	16
42 
43 /* SPIDELAY */
44 #define SPI_C2TDELAY_SHIFT	24
45 #define SPI_T2CDELAY_SHIFT	16
46 
47 /* SPIBUF */
48 #define SPIBUF_RXEMPTY_MASK	BIT(31)
49 #define SPIBUF_TXFULL_MASK	BIT(29)
50 
51 /* SPIDEF */
52 #define SPIDEF_CSDEF0_MASK	BIT(0)
53 
54 #ifndef CONFIG_DM_SPI
55 #define SPI0_BUS		0
56 #define SPI0_BASE		CONFIG_SYS_SPI_BASE
57 /*
58  * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
59  * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
60  * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
61  */
62 #ifndef CONFIG_SYS_SPI0
63 #define SPI0_NUM_CS		1
64 #else
65 #define SPI0_NUM_CS		CONFIG_SYS_SPI0_NUM_CS
66 #endif
67 
68 /*
69  * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
70  * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
71  */
72 #ifdef CONFIG_SYS_SPI1
73 #define SPI1_BUS		1
74 #define SPI1_NUM_CS		CONFIG_SYS_SPI1_NUM_CS
75 #define SPI1_BASE		CONFIG_SYS_SPI1_BASE
76 #endif
77 
78 /*
79  * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
80  * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
81  */
82 #ifdef CONFIG_SYS_SPI2
83 #define SPI2_BUS		2
84 #define SPI2_NUM_CS		CONFIG_SYS_SPI2_NUM_CS
85 #define SPI2_BASE		CONFIG_SYS_SPI2_BASE
86 #endif
87 #endif
88 
89 DECLARE_GLOBAL_DATA_PTR;
90 
91 /* davinci spi register set */
92 struct davinci_spi_regs {
93 	dv_reg	gcr0;		/* 0x00 */
94 	dv_reg	gcr1;		/* 0x04 */
95 	dv_reg	int0;		/* 0x08 */
96 	dv_reg	lvl;		/* 0x0c */
97 	dv_reg	flg;		/* 0x10 */
98 	dv_reg	pc0;		/* 0x14 */
99 	dv_reg	pc1;		/* 0x18 */
100 	dv_reg	pc2;		/* 0x1c */
101 	dv_reg	pc3;		/* 0x20 */
102 	dv_reg	pc4;		/* 0x24 */
103 	dv_reg	pc5;		/* 0x28 */
104 	dv_reg	rsvd[3];
105 	dv_reg	dat0;		/* 0x38 */
106 	dv_reg	dat1;		/* 0x3c */
107 	dv_reg	buf;		/* 0x40 */
108 	dv_reg	emu;		/* 0x44 */
109 	dv_reg	delay;		/* 0x48 */
110 	dv_reg	def;		/* 0x4c */
111 	dv_reg	fmt0;		/* 0x50 */
112 	dv_reg	fmt1;		/* 0x54 */
113 	dv_reg	fmt2;		/* 0x58 */
114 	dv_reg	fmt3;		/* 0x5c */
115 	dv_reg	intvec0;	/* 0x60 */
116 	dv_reg	intvec1;	/* 0x64 */
117 };
118 
119 /* davinci spi slave */
120 struct davinci_spi_slave {
121 #ifndef CONFIG_DM_SPI
122 	struct spi_slave slave;
123 #endif
124 	struct davinci_spi_regs *regs;
125 	unsigned int freq; /* current SPI bus frequency */
126 	unsigned int mode; /* current SPI mode used */
127 	u8 num_cs;	   /* total no. of CS available */
128 	u8 cur_cs;	   /* CS of current slave */
129 	bool half_duplex;  /* true, if master is half-duplex only */
130 };
131 
132 /*
133  * This functions needs to act like a macro to avoid pipeline reloads in the
134  * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
135  * appears to be zero bytes (da830).
136  */
137 __attribute__((always_inline))
138 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
139 {
140 	u32	buf_reg_val;
141 
142 	/* send out data */
143 	writel(data, &ds->regs->dat1);
144 
145 	/* wait for the data to clock in/out */
146 	while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
147 		;
148 
149 	return buf_reg_val;
150 }
151 
152 static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
153 			    u8 *rxp, unsigned long flags)
154 {
155 	unsigned int data1_reg_val;
156 
157 	/* enable CS hold, CS[n] and clear the data bits */
158 	data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
159 			 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
160 
161 	/* wait till TXFULL is deasserted */
162 	while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
163 		;
164 
165 	/* preload the TX buffer to avoid clock starvation */
166 	writel(data1_reg_val, &ds->regs->dat1);
167 
168 	/* keep reading 1 byte until only 1 byte left */
169 	while ((len--) > 1)
170 		*rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
171 
172 	/* clear CS hold when we reach the end */
173 	if (flags & SPI_XFER_END)
174 		data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
175 
176 	/* read the last byte */
177 	*rxp = davinci_spi_xfer_data(ds, data1_reg_val);
178 
179 	return 0;
180 }
181 
182 static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
183 			     const u8 *txp, unsigned long flags)
184 {
185 	unsigned int data1_reg_val;
186 
187 	/* enable CS hold and clear the data bits */
188 	data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
189 			 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
190 
191 	/* wait till TXFULL is deasserted */
192 	while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
193 		;
194 
195 	/* preload the TX buffer to avoid clock starvation */
196 	if (len > 2) {
197 		writel(data1_reg_val | *txp++, &ds->regs->dat1);
198 		len--;
199 	}
200 
201 	/* keep writing 1 byte until only 1 byte left */
202 	while ((len--) > 1)
203 		davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
204 
205 	/* clear CS hold when we reach the end */
206 	if (flags & SPI_XFER_END)
207 		data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
208 
209 	/* write the last byte */
210 	davinci_spi_xfer_data(ds, data1_reg_val | *txp);
211 
212 	return 0;
213 }
214 
215 static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
216 				  int len, u8 *rxp, const u8 *txp,
217 				  unsigned long flags)
218 {
219 	unsigned int data1_reg_val;
220 
221 	/* enable CS hold and clear the data bits */
222 	data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
223 			 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
224 
225 	/* wait till TXFULL is deasserted */
226 	while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
227 		;
228 
229 	/* keep reading and writing 1 byte until only 1 byte left */
230 	while ((len--) > 1)
231 		*rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
232 
233 	/* clear CS hold when we reach the end */
234 	if (flags & SPI_XFER_END)
235 		data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
236 
237 	/* read and write the last byte */
238 	*rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
239 
240 	return 0;
241 }
242 
243 
244 static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
245 {
246 	unsigned int mode = 0, scalar;
247 
248 	/* Enable the SPI hardware */
249 	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
250 	udelay(1000);
251 	writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
252 
253 	/* Set master mode, powered up and not activated */
254 	writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
255 
256 	/* CS, CLK, SIMO and SOMI are functional pins */
257 	writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
258 		SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
259 
260 	/* setup format */
261 	scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
262 
263 	/*
264 	 * Use following format:
265 	 *   character length = 8,
266 	 *   MSB shifted out first
267 	 */
268 	if (ds->mode & SPI_CPOL)
269 		mode |= SPI_CPOL;
270 	if (!(ds->mode & SPI_CPHA))
271 		mode |= SPI_CPHA;
272 	writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
273 		(mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
274 
275 	/*
276 	 * Including a minor delay. No science here. Should be good even with
277 	 * no delay
278 	 */
279 	writel((50 << SPI_C2TDELAY_SHIFT) |
280 		(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
281 
282 	/* default chip select register */
283 	writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
284 
285 	/* no interrupts */
286 	writel(0, &ds->regs->int0);
287 	writel(0, &ds->regs->lvl);
288 
289 	/* enable SPI */
290 	writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
291 
292 	return 0;
293 }
294 
295 static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
296 {
297 	/* Disable the SPI hardware */
298 	writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
299 
300 	return 0;
301 }
302 
303 static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
304 		unsigned int bitlen,  const void *dout, void *din,
305 		unsigned long flags)
306 {
307 	unsigned int len;
308 
309 	if (bitlen == 0)
310 		/* Finish any previously submitted transfers */
311 		goto out;
312 
313 	/*
314 	 * It's not clear how non-8-bit-aligned transfers are supposed to be
315 	 * represented as a stream of bytes...this is a limitation of
316 	 * the current SPI interface - here we terminate on receiving such a
317 	 * transfer request.
318 	 */
319 	if (bitlen % 8) {
320 		/* Errors always terminate an ongoing transfer */
321 		flags |= SPI_XFER_END;
322 		goto out;
323 	}
324 
325 	len = bitlen / 8;
326 
327 	if (!dout)
328 		return davinci_spi_read(ds, len, din, flags);
329 	if (!din)
330 		return davinci_spi_write(ds, len, dout, flags);
331 	if (!ds->half_duplex)
332 		return davinci_spi_read_write(ds, len, din, dout, flags);
333 
334 	printf("SPI full duplex not supported\n");
335 	flags |= SPI_XFER_END;
336 
337 out:
338 	if (flags & SPI_XFER_END) {
339 		u8 dummy = 0;
340 		davinci_spi_write(ds, 1, &dummy, flags);
341 	}
342 	return 0;
343 }
344 
345 #ifndef CONFIG_DM_SPI
346 
347 static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
348 {
349 	return container_of(slave, struct davinci_spi_slave, slave);
350 }
351 
352 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
353 {
354 	int ret = 0;
355 
356 	switch (bus) {
357 	case SPI0_BUS:
358 		if (cs < SPI0_NUM_CS)
359 			ret = 1;
360 		break;
361 #ifdef CONFIG_SYS_SPI1
362 	case SPI1_BUS:
363 		if (cs < SPI1_NUM_CS)
364 			ret = 1;
365 		break;
366 #endif
367 #ifdef CONFIG_SYS_SPI2
368 	case SPI2_BUS:
369 		if (cs < SPI2_NUM_CS)
370 			ret = 1;
371 		break;
372 #endif
373 	default:
374 		/* Invalid bus number. Do nothing */
375 		break;
376 	}
377 	return ret;
378 }
379 
380 void spi_cs_activate(struct spi_slave *slave)
381 {
382 	/* do nothing */
383 }
384 
385 void spi_cs_deactivate(struct spi_slave *slave)
386 {
387 	/* do nothing */
388 }
389 
390 void spi_init(void)
391 {
392 	/* do nothing */
393 }
394 
395 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
396 			unsigned int max_hz, unsigned int mode)
397 {
398 	struct davinci_spi_slave	*ds;
399 
400 	if (!spi_cs_is_valid(bus, cs))
401 		return NULL;
402 
403 	ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
404 	if (!ds)
405 		return NULL;
406 
407 	switch (bus) {
408 	case SPI0_BUS:
409 		ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
410 		break;
411 #ifdef CONFIG_SYS_SPI1
412 	case SPI1_BUS:
413 		ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
414 		break;
415 #endif
416 #ifdef CONFIG_SYS_SPI2
417 	case SPI2_BUS:
418 		ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
419 		break;
420 #endif
421 	default: /* Invalid bus number */
422 		return NULL;
423 	}
424 
425 	ds->freq = max_hz;
426 	ds->mode = mode;
427 
428 	return &ds->slave;
429 }
430 
431 void spi_free_slave(struct spi_slave *slave)
432 {
433 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
434 
435 	free(ds);
436 }
437 
438 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
439 	     const void *dout, void *din, unsigned long flags)
440 {
441 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
442 
443 	ds->cur_cs = slave->cs;
444 
445 	return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
446 }
447 
448 int spi_claim_bus(struct spi_slave *slave)
449 {
450 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
451 
452 #ifdef CONFIG_SPI_HALF_DUPLEX
453 	ds->half_duplex = true;
454 #else
455 	ds->half_duplex = false;
456 #endif
457 	return __davinci_spi_claim_bus(ds, ds->slave.cs);
458 }
459 
460 void spi_release_bus(struct spi_slave *slave)
461 {
462 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
463 
464 	__davinci_spi_release_bus(ds);
465 }
466 
467 #else
468 static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
469 {
470 	struct davinci_spi_slave *ds = dev_get_priv(bus);
471 
472 	debug("%s speed %u\n", __func__, max_hz);
473 	if (max_hz > CONFIG_SYS_SPI_CLK / 2)
474 		return -EINVAL;
475 
476 	ds->freq = max_hz;
477 
478 	return 0;
479 }
480 
481 static int davinci_spi_set_mode(struct udevice *bus, uint mode)
482 {
483 	struct davinci_spi_slave *ds = dev_get_priv(bus);
484 
485 	debug("%s mode %u\n", __func__, mode);
486 	ds->mode = mode;
487 
488 	return 0;
489 }
490 
491 static int davinci_spi_claim_bus(struct udevice *dev)
492 {
493 	struct dm_spi_slave_platdata *slave_plat =
494 		dev_get_parent_platdata(dev);
495 	struct udevice *bus = dev->parent;
496 	struct davinci_spi_slave *ds = dev_get_priv(bus);
497 
498 	if (slave_plat->cs >= ds->num_cs) {
499 		printf("Invalid SPI chipselect\n");
500 		return -EINVAL;
501 	}
502 	ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
503 
504 	return __davinci_spi_claim_bus(ds, slave_plat->cs);
505 }
506 
507 static int davinci_spi_release_bus(struct udevice *dev)
508 {
509 	struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
510 
511 	return __davinci_spi_release_bus(ds);
512 }
513 
514 static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
515 			    const void *dout, void *din,
516 			    unsigned long flags)
517 {
518 	struct dm_spi_slave_platdata *slave =
519 		dev_get_parent_platdata(dev);
520 	struct udevice *bus = dev->parent;
521 	struct davinci_spi_slave *ds = dev_get_priv(bus);
522 
523 	if (slave->cs >= ds->num_cs) {
524 		printf("Invalid SPI chipselect\n");
525 		return -EINVAL;
526 	}
527 	ds->cur_cs = slave->cs;
528 
529 	return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
530 }
531 
532 static int davinci_spi_probe(struct udevice *bus)
533 {
534 	/* Nothing to do */
535 	return 0;
536 }
537 
538 static int davinci_ofdata_to_platadata(struct udevice *bus)
539 {
540 	struct davinci_spi_slave *ds = dev_get_priv(bus);
541 	const void *blob = gd->fdt_blob;
542 	int node = dev_of_offset(bus);
543 
544 	ds->regs = devfdt_map_physmem(bus, sizeof(struct davinci_spi_regs));
545 	if (!ds->regs) {
546 		printf("%s: could not map device address\n", __func__);
547 		return -EINVAL;
548 	}
549 	ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
550 
551 	return 0;
552 }
553 
554 static const struct dm_spi_ops davinci_spi_ops = {
555 	.claim_bus	= davinci_spi_claim_bus,
556 	.release_bus	= davinci_spi_release_bus,
557 	.xfer		= davinci_spi_xfer,
558 	.set_speed	= davinci_spi_set_speed,
559 	.set_mode	= davinci_spi_set_mode,
560 };
561 
562 static const struct udevice_id davinci_spi_ids[] = {
563 	{ .compatible = "ti,keystone-spi" },
564 	{ .compatible = "ti,dm6441-spi" },
565 	{ .compatible = "ti,da830-spi" },
566 	{ }
567 };
568 
569 U_BOOT_DRIVER(davinci_spi) = {
570 	.name = "davinci_spi",
571 	.id = UCLASS_SPI,
572 	.of_match = davinci_spi_ids,
573 	.ops = &davinci_spi_ops,
574 	.ofdata_to_platdata = davinci_ofdata_to_platadata,
575 	.priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
576 	.probe = davinci_spi_probe,
577 };
578 #endif
579