1 /* 2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Driver for SPI controller on DaVinci. Based on atmel_spi.c 5 * by Atmel Corporation 6 * 7 * Copyright (C) 2007 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <spi.h> 14 #include <malloc.h> 15 #include <asm/io.h> 16 #include <asm/arch/hardware.h> 17 18 #define BIT(x) (1 << (x)) 19 20 /* SPIGCR0 */ 21 #define SPIGCR0_SPIENA_MASK 0x1 22 #define SPIGCR0_SPIRST_MASK 0x0 23 24 /* SPIGCR0 */ 25 #define SPIGCR1_CLKMOD_MASK BIT(1) 26 #define SPIGCR1_MASTER_MASK BIT(0) 27 #define SPIGCR1_SPIENA_MASK BIT(24) 28 29 /* SPIPC0 */ 30 #define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ 31 #define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ 32 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 33 #define SPIPC0_EN0FUN_MASK BIT(0) 34 35 /* SPIFMT0 */ 36 #define SPIFMT_SHIFTDIR_SHIFT 20 37 #define SPIFMT_POLARITY_SHIFT 17 38 #define SPIFMT_PHASE_SHIFT 16 39 #define SPIFMT_PRESCALE_SHIFT 8 40 41 /* SPIDAT1 */ 42 #define SPIDAT1_CSHOLD_SHIFT 28 43 #define SPIDAT1_CSNR_SHIFT 16 44 45 /* SPIDELAY */ 46 #define SPI_C2TDELAY_SHIFT 24 47 #define SPI_T2CDELAY_SHIFT 16 48 49 /* SPIBUF */ 50 #define SPIBUF_RXEMPTY_MASK BIT(31) 51 #define SPIBUF_TXFULL_MASK BIT(29) 52 53 /* SPIDEF */ 54 #define SPIDEF_CSDEF0_MASK BIT(0) 55 56 #define SPI0_BUS 0 57 #define SPI0_BASE CONFIG_SYS_SPI_BASE 58 /* 59 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this 60 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS 61 * if more than one CS is supported and by defining CONFIG_SYS_SPI0. 62 */ 63 #ifndef CONFIG_SYS_SPI0 64 #define SPI0_NUM_CS 1 65 #else 66 #define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS 67 #endif 68 69 /* 70 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and 71 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus 72 */ 73 #ifdef CONFIG_SYS_SPI1 74 #define SPI1_BUS 1 75 #define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS 76 #define SPI1_BASE CONFIG_SYS_SPI1_BASE 77 #endif 78 79 /* 80 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and 81 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus 82 */ 83 #ifdef CONFIG_SYS_SPI2 84 #define SPI2_BUS 2 85 #define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS 86 #define SPI2_BASE CONFIG_SYS_SPI2_BASE 87 #endif 88 89 /* davinci spi register set */ 90 struct davinci_spi_regs { 91 dv_reg gcr0; /* 0x00 */ 92 dv_reg gcr1; /* 0x04 */ 93 dv_reg int0; /* 0x08 */ 94 dv_reg lvl; /* 0x0c */ 95 dv_reg flg; /* 0x10 */ 96 dv_reg pc0; /* 0x14 */ 97 dv_reg pc1; /* 0x18 */ 98 dv_reg pc2; /* 0x1c */ 99 dv_reg pc3; /* 0x20 */ 100 dv_reg pc4; /* 0x24 */ 101 dv_reg pc5; /* 0x28 */ 102 dv_reg rsvd[3]; 103 dv_reg dat0; /* 0x38 */ 104 dv_reg dat1; /* 0x3c */ 105 dv_reg buf; /* 0x40 */ 106 dv_reg emu; /* 0x44 */ 107 dv_reg delay; /* 0x48 */ 108 dv_reg def; /* 0x4c */ 109 dv_reg fmt0; /* 0x50 */ 110 dv_reg fmt1; /* 0x54 */ 111 dv_reg fmt2; /* 0x58 */ 112 dv_reg fmt3; /* 0x5c */ 113 dv_reg intvec0; /* 0x60 */ 114 dv_reg intvec1; /* 0x64 */ 115 }; 116 117 /* davinci spi slave */ 118 struct davinci_spi_slave { 119 struct spi_slave slave; 120 struct davinci_spi_regs *regs; 121 unsigned int freq; 122 }; 123 124 static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) 125 { 126 return container_of(slave, struct davinci_spi_slave, slave); 127 } 128 129 /* 130 * This functions needs to act like a macro to avoid pipeline reloads in the 131 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat 132 * appears to be zero bytes (da830). 133 */ 134 __attribute__((always_inline)) 135 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data) 136 { 137 u32 buf_reg_val; 138 139 /* send out data */ 140 writel(data, &ds->regs->dat1); 141 142 /* wait for the data to clock in/out */ 143 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK) 144 ; 145 146 return buf_reg_val; 147 } 148 149 static int davinci_spi_read(struct spi_slave *slave, unsigned int len, 150 u8 *rxp, unsigned long flags) 151 { 152 struct davinci_spi_slave *ds = to_davinci_spi(slave); 153 unsigned int data1_reg_val; 154 155 /* enable CS hold, CS[n] and clear the data bits */ 156 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 157 (slave->cs << SPIDAT1_CSNR_SHIFT)); 158 159 /* wait till TXFULL is deasserted */ 160 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 161 ; 162 163 /* preload the TX buffer to avoid clock starvation */ 164 writel(data1_reg_val, &ds->regs->dat1); 165 166 /* keep reading 1 byte until only 1 byte left */ 167 while ((len--) > 1) 168 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val); 169 170 /* clear CS hold when we reach the end */ 171 if (flags & SPI_XFER_END) 172 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 173 174 /* read the last byte */ 175 *rxp = davinci_spi_xfer_data(ds, data1_reg_val); 176 177 return 0; 178 } 179 180 static int davinci_spi_write(struct spi_slave *slave, unsigned int len, 181 const u8 *txp, unsigned long flags) 182 { 183 struct davinci_spi_slave *ds = to_davinci_spi(slave); 184 unsigned int data1_reg_val; 185 186 /* enable CS hold and clear the data bits */ 187 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 188 (slave->cs << SPIDAT1_CSNR_SHIFT)); 189 190 /* wait till TXFULL is deasserted */ 191 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 192 ; 193 194 /* preload the TX buffer to avoid clock starvation */ 195 if (len > 2) { 196 writel(data1_reg_val | *txp++, &ds->regs->dat1); 197 len--; 198 } 199 200 /* keep writing 1 byte until only 1 byte left */ 201 while ((len--) > 1) 202 davinci_spi_xfer_data(ds, data1_reg_val | *txp++); 203 204 /* clear CS hold when we reach the end */ 205 if (flags & SPI_XFER_END) 206 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 207 208 /* write the last byte */ 209 davinci_spi_xfer_data(ds, data1_reg_val | *txp); 210 211 return 0; 212 } 213 214 #ifndef CONFIG_SPI_HALF_DUPLEX 215 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, 216 u8 *rxp, const u8 *txp, unsigned long flags) 217 { 218 struct davinci_spi_slave *ds = to_davinci_spi(slave); 219 unsigned int data1_reg_val; 220 221 /* enable CS hold and clear the data bits */ 222 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 223 (slave->cs << SPIDAT1_CSNR_SHIFT)); 224 225 /* wait till TXFULL is deasserted */ 226 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 227 ; 228 229 /* keep reading and writing 1 byte until only 1 byte left */ 230 while ((len--) > 1) 231 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++); 232 233 /* clear CS hold when we reach the end */ 234 if (flags & SPI_XFER_END) 235 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 236 237 /* read and write the last byte */ 238 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp); 239 240 return 0; 241 } 242 #endif 243 244 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 245 { 246 int ret = 0; 247 248 switch (bus) { 249 case SPI0_BUS: 250 if (cs < SPI0_NUM_CS) 251 ret = 1; 252 break; 253 #ifdef CONFIG_SYS_SPI1 254 case SPI1_BUS: 255 if (cs < SPI1_NUM_CS) 256 ret = 1; 257 break; 258 #endif 259 #ifdef CONFIG_SYS_SPI2 260 case SPI2_BUS: 261 if (cs < SPI2_NUM_CS) 262 ret = 1; 263 break; 264 #endif 265 default: 266 /* Invalid bus number. Do nothing */ 267 break; 268 } 269 return ret; 270 } 271 272 void spi_cs_activate(struct spi_slave *slave) 273 { 274 /* do nothing */ 275 } 276 277 void spi_cs_deactivate(struct spi_slave *slave) 278 { 279 /* do nothing */ 280 } 281 282 void spi_init(void) 283 { 284 /* do nothing */ 285 } 286 287 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 288 unsigned int max_hz, unsigned int mode) 289 { 290 struct davinci_spi_slave *ds; 291 292 if (!spi_cs_is_valid(bus, cs)) 293 return NULL; 294 295 ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); 296 if (!ds) 297 return NULL; 298 299 switch (bus) { 300 case SPI0_BUS: 301 ds->regs = (struct davinci_spi_regs *)SPI0_BASE; 302 break; 303 #ifdef CONFIG_SYS_SPI1 304 case SPI1_BUS: 305 ds->regs = (struct davinci_spi_regs *)SPI1_BASE; 306 break; 307 #endif 308 #ifdef CONFIG_SYS_SPI2 309 case SPI2_BUS: 310 ds->regs = (struct davinci_spi_regs *)SPI2_BASE; 311 break; 312 #endif 313 default: /* Invalid bus number */ 314 return NULL; 315 } 316 317 ds->freq = max_hz; 318 319 return &ds->slave; 320 } 321 322 void spi_free_slave(struct spi_slave *slave) 323 { 324 struct davinci_spi_slave *ds = to_davinci_spi(slave); 325 326 free(ds); 327 } 328 329 int spi_claim_bus(struct spi_slave *slave) 330 { 331 struct davinci_spi_slave *ds = to_davinci_spi(slave); 332 unsigned int scalar; 333 334 /* Enable the SPI hardware */ 335 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); 336 udelay(1000); 337 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); 338 339 /* Set master mode, powered up and not activated */ 340 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); 341 342 /* CS, CLK, SIMO and SOMI are functional pins */ 343 writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | 344 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); 345 346 /* setup format */ 347 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; 348 349 /* 350 * Use following format: 351 * character length = 8, 352 * clock signal delayed by half clk cycle, 353 * clock low in idle state - Mode 0, 354 * MSB shifted out first 355 */ 356 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | 357 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); 358 359 /* 360 * Including a minor delay. No science here. Should be good even with 361 * no delay 362 */ 363 writel((50 << SPI_C2TDELAY_SHIFT) | 364 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); 365 366 /* default chip select register */ 367 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); 368 369 /* no interrupts */ 370 writel(0, &ds->regs->int0); 371 writel(0, &ds->regs->lvl); 372 373 /* enable SPI */ 374 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); 375 376 return 0; 377 } 378 379 void spi_release_bus(struct spi_slave *slave) 380 { 381 struct davinci_spi_slave *ds = to_davinci_spi(slave); 382 383 /* Disable the SPI hardware */ 384 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); 385 } 386 387 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 388 const void *dout, void *din, unsigned long flags) 389 { 390 unsigned int len; 391 392 if (bitlen == 0) 393 /* Finish any previously submitted transfers */ 394 goto out; 395 396 /* 397 * It's not clear how non-8-bit-aligned transfers are supposed to be 398 * represented as a stream of bytes...this is a limitation of 399 * the current SPI interface - here we terminate on receiving such a 400 * transfer request. 401 */ 402 if (bitlen % 8) { 403 /* Errors always terminate an ongoing transfer */ 404 flags |= SPI_XFER_END; 405 goto out; 406 } 407 408 len = bitlen / 8; 409 410 if (!dout) 411 return davinci_spi_read(slave, len, din, flags); 412 else if (!din) 413 return davinci_spi_write(slave, len, dout, flags); 414 #ifndef CONFIG_SPI_HALF_DUPLEX 415 else 416 return davinci_spi_read_write(slave, len, din, dout, flags); 417 #else 418 printf("SPI full duplex transaction requested with " 419 "CONFIG_SPI_HALF_DUPLEX defined.\n"); 420 flags |= SPI_XFER_END; 421 #endif 422 423 out: 424 if (flags & SPI_XFER_END) { 425 u8 dummy = 0; 426 davinci_spi_write(slave, 1, &dummy, flags); 427 } 428 return 0; 429 } 430