1 /* 2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Driver for SPI controller on DaVinci. Based on atmel_spi.c 5 * by Atmel Corporation 6 * 7 * Copyright (C) 2007 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 #include <common.h> 12 #include <spi.h> 13 #include <malloc.h> 14 #include <asm/io.h> 15 #include <asm/arch/hardware.h> 16 #include "davinci_spi.h" 17 18 void spi_init() 19 { 20 /* do nothing */ 21 } 22 23 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 24 unsigned int max_hz, unsigned int mode) 25 { 26 struct davinci_spi_slave *ds; 27 28 if (!spi_cs_is_valid(bus, cs)) 29 return NULL; 30 31 ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); 32 if (!ds) 33 return NULL; 34 35 ds->slave.bus = bus; 36 ds->slave.cs = cs; 37 38 switch (bus) { 39 case SPI0_BUS: 40 ds->regs = (struct davinci_spi_regs *)SPI0_BASE; 41 break; 42 #ifdef CONFIG_SYS_SPI1 43 case SPI1_BUS: 44 ds->regs = (struct davinci_spi_regs *)SPI1_BASE; 45 break; 46 #endif 47 #ifdef CONFIG_SYS_SPI2 48 case SPI2_BUS: 49 ds->regs = (struct davinci_spi_regs *)SPI2_BASE; 50 break; 51 #endif 52 default: /* Invalid bus number */ 53 return NULL; 54 } 55 56 ds->freq = max_hz; 57 58 return &ds->slave; 59 } 60 61 void spi_free_slave(struct spi_slave *slave) 62 { 63 struct davinci_spi_slave *ds = to_davinci_spi(slave); 64 65 free(ds); 66 } 67 68 int spi_claim_bus(struct spi_slave *slave) 69 { 70 struct davinci_spi_slave *ds = to_davinci_spi(slave); 71 unsigned int scalar; 72 73 /* Enable the SPI hardware */ 74 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); 75 udelay(1000); 76 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); 77 78 /* Set master mode, powered up and not activated */ 79 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); 80 81 /* CS, CLK, SIMO and SOMI are functional pins */ 82 writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | 83 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); 84 85 /* setup format */ 86 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; 87 88 /* 89 * Use following format: 90 * character length = 8, 91 * clock signal delayed by half clk cycle, 92 * clock low in idle state - Mode 0, 93 * MSB shifted out first 94 */ 95 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | 96 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); 97 98 /* 99 * Including a minor delay. No science here. Should be good even with 100 * no delay 101 */ 102 writel((50 << SPI_C2TDELAY_SHIFT) | 103 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); 104 105 /* default chip select register */ 106 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); 107 108 /* no interrupts */ 109 writel(0, &ds->regs->int0); 110 writel(0, &ds->regs->lvl); 111 112 /* enable SPI */ 113 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); 114 115 return 0; 116 } 117 118 void spi_release_bus(struct spi_slave *slave) 119 { 120 struct davinci_spi_slave *ds = to_davinci_spi(slave); 121 122 /* Disable the SPI hardware */ 123 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); 124 } 125 126 /* 127 * This functions needs to act like a macro to avoid pipeline reloads in the 128 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat 129 * appears to be zero bytes (da830). 130 */ 131 __attribute__((always_inline)) 132 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data) 133 { 134 u32 buf_reg_val; 135 136 /* send out data */ 137 writel(data, &ds->regs->dat1); 138 139 /* wait for the data to clock in/out */ 140 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK) 141 ; 142 143 return buf_reg_val; 144 } 145 146 static int davinci_spi_read(struct spi_slave *slave, unsigned int len, 147 u8 *rxp, unsigned long flags) 148 { 149 struct davinci_spi_slave *ds = to_davinci_spi(slave); 150 unsigned int data1_reg_val; 151 152 /* enable CS hold, CS[n] and clear the data bits */ 153 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 154 (slave->cs << SPIDAT1_CSNR_SHIFT)); 155 156 /* wait till TXFULL is deasserted */ 157 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 158 ; 159 160 /* preload the TX buffer to avoid clock starvation */ 161 writel(data1_reg_val, &ds->regs->dat1); 162 163 /* keep reading 1 byte until only 1 byte left */ 164 while ((len--) > 1) 165 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val); 166 167 /* clear CS hold when we reach the end */ 168 if (flags & SPI_XFER_END) 169 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 170 171 /* read the last byte */ 172 *rxp = davinci_spi_xfer_data(ds, data1_reg_val); 173 174 return 0; 175 } 176 177 static int davinci_spi_write(struct spi_slave *slave, unsigned int len, 178 const u8 *txp, unsigned long flags) 179 { 180 struct davinci_spi_slave *ds = to_davinci_spi(slave); 181 unsigned int data1_reg_val; 182 183 /* enable CS hold and clear the data bits */ 184 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 185 (slave->cs << SPIDAT1_CSNR_SHIFT)); 186 187 /* wait till TXFULL is deasserted */ 188 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 189 ; 190 191 /* preload the TX buffer to avoid clock starvation */ 192 if (len > 2) { 193 writel(data1_reg_val | *txp++, &ds->regs->dat1); 194 len--; 195 } 196 197 /* keep writing 1 byte until only 1 byte left */ 198 while ((len--) > 1) 199 davinci_spi_xfer_data(ds, data1_reg_val | *txp++); 200 201 /* clear CS hold when we reach the end */ 202 if (flags & SPI_XFER_END) 203 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 204 205 /* write the last byte */ 206 davinci_spi_xfer_data(ds, data1_reg_val | *txp); 207 208 return 0; 209 } 210 211 #ifndef CONFIG_SPI_HALF_DUPLEX 212 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, 213 u8 *rxp, const u8 *txp, unsigned long flags) 214 { 215 struct davinci_spi_slave *ds = to_davinci_spi(slave); 216 unsigned int data1_reg_val; 217 218 /* enable CS hold and clear the data bits */ 219 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | 220 (slave->cs << SPIDAT1_CSNR_SHIFT)); 221 222 /* wait till TXFULL is deasserted */ 223 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) 224 ; 225 226 /* keep reading and writing 1 byte until only 1 byte left */ 227 while ((len--) > 1) 228 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++); 229 230 /* clear CS hold when we reach the end */ 231 if (flags & SPI_XFER_END) 232 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); 233 234 /* read and write the last byte */ 235 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp); 236 237 return 0; 238 } 239 #endif 240 241 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 242 const void *dout, void *din, unsigned long flags) 243 { 244 unsigned int len; 245 246 if (bitlen == 0) 247 /* Finish any previously submitted transfers */ 248 goto out; 249 250 /* 251 * It's not clear how non-8-bit-aligned transfers are supposed to be 252 * represented as a stream of bytes...this is a limitation of 253 * the current SPI interface - here we terminate on receiving such a 254 * transfer request. 255 */ 256 if (bitlen % 8) { 257 /* Errors always terminate an ongoing transfer */ 258 flags |= SPI_XFER_END; 259 goto out; 260 } 261 262 len = bitlen / 8; 263 264 if (!dout) 265 return davinci_spi_read(slave, len, din, flags); 266 else if (!din) 267 return davinci_spi_write(slave, len, dout, flags); 268 #ifndef CONFIG_SPI_HALF_DUPLEX 269 else 270 return davinci_spi_read_write(slave, len, din, dout, flags); 271 #else 272 printf("SPI full duplex transaction requested with " 273 "CONFIG_SPI_HALF_DUPLEX defined.\n"); 274 flags |= SPI_XFER_END; 275 #endif 276 277 out: 278 if (flags & SPI_XFER_END) { 279 u8 dummy = 0; 280 davinci_spi_write(slave, 1, &dummy, flags); 281 } 282 return 0; 283 } 284 285 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 286 { 287 int ret = 0; 288 289 switch (bus) { 290 case SPI0_BUS: 291 if (cs < SPI0_NUM_CS) 292 ret = 1; 293 break; 294 #ifdef CONFIG_SYS_SPI1 295 case SPI1_BUS: 296 if (cs < SPI1_NUM_CS) 297 ret = 1; 298 break; 299 #endif 300 #ifdef CONFIG_SYS_SPI2 301 case SPI2_BUS: 302 if (cs < SPI2_NUM_CS) 303 ret = 1; 304 break; 305 #endif 306 default: 307 /* Invalid bus number. Do nothing */ 308 break; 309 } 310 return ret; 311 } 312 313 void spi_cs_activate(struct spi_slave *slave) 314 { 315 /* do nothing */ 316 } 317 318 void spi_cs_deactivate(struct spi_slave *slave) 319 { 320 /* do nothing */ 321 } 322