1 /*
2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *  - Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  *  - Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *  - Neither the name of the Altera Corporation nor the
13  *    names of its contributors may be used to endorse or promote products
14  *    derived from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <common.h>
29 #include <asm/io.h>
30 #include <asm/errno.h>
31 #include <wait_bit.h>
32 #include <spi.h>
33 #include "cadence_qspi.h"
34 
35 #define CQSPI_REG_POLL_US			(1) /* 1us */
36 #define CQSPI_REG_RETRY				(10000)
37 #define CQSPI_POLL_IDLE_RETRY			(3)
38 
39 #define CQSPI_FIFO_WIDTH			(4)
40 
41 #define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
42 
43 /* Transfer mode */
44 #define CQSPI_INST_TYPE_SINGLE			(0)
45 #define CQSPI_INST_TYPE_DUAL			(1)
46 #define CQSPI_INST_TYPE_QUAD			(2)
47 
48 #define CQSPI_STIG_DATA_LEN_MAX			(8)
49 
50 #define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
51 #define CQSPI_DUMMY_BYTES_MAX			(4)
52 
53 
54 #define CQSPI_REG_SRAM_FILL_THRESHOLD	\
55 	((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
56 /****************************************************************************
57  * Controller's configuration and status register (offset from QSPI_BASE)
58  ****************************************************************************/
59 #define	CQSPI_REG_CONFIG			0x00
60 #define	CQSPI_REG_CONFIG_CLK_POL_LSB		1
61 #define	CQSPI_REG_CONFIG_CLK_PHA_LSB		2
62 #define	CQSPI_REG_CONFIG_ENABLE_MASK		BIT(0)
63 #define	CQSPI_REG_CONFIG_DIRECT_MASK		BIT(7)
64 #define	CQSPI_REG_CONFIG_DECODE_MASK		BIT(9)
65 #define	CQSPI_REG_CONFIG_XIP_IMM_MASK		BIT(18)
66 #define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
67 #define	CQSPI_REG_CONFIG_BAUD_LSB		19
68 #define	CQSPI_REG_CONFIG_IDLE_LSB		31
69 #define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
70 #define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
71 
72 #define	CQSPI_REG_RD_INSTR			0x04
73 #define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
74 #define	CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB	8
75 #define	CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB	12
76 #define	CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
77 #define	CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
78 #define	CQSPI_REG_RD_INSTR_DUMMY_LSB		24
79 #define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
80 #define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
81 #define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
82 #define	CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
83 
84 #define	CQSPI_REG_WR_INSTR			0x08
85 #define	CQSPI_REG_WR_INSTR_OPCODE_LSB		0
86 
87 #define	CQSPI_REG_DELAY				0x0C
88 #define	CQSPI_REG_DELAY_TSLCH_LSB		0
89 #define	CQSPI_REG_DELAY_TCHSH_LSB		8
90 #define	CQSPI_REG_DELAY_TSD2D_LSB		16
91 #define	CQSPI_REG_DELAY_TSHSL_LSB		24
92 #define	CQSPI_REG_DELAY_TSLCH_MASK		0xFF
93 #define	CQSPI_REG_DELAY_TCHSH_MASK		0xFF
94 #define	CQSPI_REG_DELAY_TSD2D_MASK		0xFF
95 #define	CQSPI_REG_DELAY_TSHSL_MASK		0xFF
96 
97 #define	CQSPI_READLCAPTURE			0x10
98 #define	CQSPI_READLCAPTURE_BYPASS_LSB		0
99 #define	CQSPI_READLCAPTURE_DELAY_LSB		1
100 #define	CQSPI_READLCAPTURE_DELAY_MASK		0xF
101 
102 #define	CQSPI_REG_SIZE				0x14
103 #define	CQSPI_REG_SIZE_ADDRESS_LSB		0
104 #define	CQSPI_REG_SIZE_PAGE_LSB			4
105 #define	CQSPI_REG_SIZE_BLOCK_LSB		16
106 #define	CQSPI_REG_SIZE_ADDRESS_MASK		0xF
107 #define	CQSPI_REG_SIZE_PAGE_MASK		0xFFF
108 #define	CQSPI_REG_SIZE_BLOCK_MASK		0x3F
109 
110 #define	CQSPI_REG_SRAMPARTITION			0x18
111 #define	CQSPI_REG_INDIRECTTRIGGER		0x1C
112 
113 #define	CQSPI_REG_REMAP				0x24
114 #define	CQSPI_REG_MODE_BIT			0x28
115 
116 #define	CQSPI_REG_SDRAMLEVEL			0x2C
117 #define	CQSPI_REG_SDRAMLEVEL_RD_LSB		0
118 #define	CQSPI_REG_SDRAMLEVEL_WR_LSB		16
119 #define	CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
120 #define	CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
121 
122 #define	CQSPI_REG_IRQSTATUS			0x40
123 #define	CQSPI_REG_IRQMASK			0x44
124 
125 #define	CQSPI_REG_INDIRECTRD			0x60
126 #define	CQSPI_REG_INDIRECTRD_START_MASK		BIT(0)
127 #define	CQSPI_REG_INDIRECTRD_CANCEL_MASK	BIT(1)
128 #define	CQSPI_REG_INDIRECTRD_INPROGRESS_MASK	BIT(2)
129 #define	CQSPI_REG_INDIRECTRD_DONE_MASK		BIT(5)
130 
131 #define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
132 #define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
133 #define	CQSPI_REG_INDIRECTRDBYTES		0x6C
134 
135 #define	CQSPI_REG_CMDCTRL			0x90
136 #define	CQSPI_REG_CMDCTRL_EXECUTE_MASK		BIT(0)
137 #define	CQSPI_REG_CMDCTRL_INPROGRESS_MASK	BIT(1)
138 #define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
139 #define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
140 #define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
141 #define	CQSPI_REG_CMDCTRL_ADD_BYTES_LSB		16
142 #define	CQSPI_REG_CMDCTRL_ADDR_EN_LSB		19
143 #define	CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
144 #define	CQSPI_REG_CMDCTRL_RD_EN_LSB		23
145 #define	CQSPI_REG_CMDCTRL_OPCODE_LSB		24
146 #define	CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
147 #define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
148 #define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
149 #define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
150 #define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
151 
152 #define	CQSPI_REG_INDIRECTWR			0x70
153 #define	CQSPI_REG_INDIRECTWR_START_MASK		BIT(0)
154 #define	CQSPI_REG_INDIRECTWR_CANCEL_MASK	BIT(1)
155 #define	CQSPI_REG_INDIRECTWR_INPROGRESS_MASK	BIT(2)
156 #define	CQSPI_REG_INDIRECTWR_DONE_MASK		BIT(5)
157 
158 #define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
159 #define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
160 #define	CQSPI_REG_INDIRECTWRBYTES		0x7C
161 
162 #define	CQSPI_REG_CMDADDRESS			0x94
163 #define	CQSPI_REG_CMDREADDATALOWER		0xA0
164 #define	CQSPI_REG_CMDREADDATAUPPER		0xA4
165 #define	CQSPI_REG_CMDWRITEDATALOWER		0xA8
166 #define	CQSPI_REG_CMDWRITEDATAUPPER		0xAC
167 
168 #define CQSPI_REG_IS_IDLE(base)					\
169 	((readl(base + CQSPI_REG_CONFIG) >>		\
170 		CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
171 
172 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)		\
173 	((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
174 
175 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)			\
176 	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
177 	CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
178 
179 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)			\
180 	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
181 	CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
182 
183 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
184 	unsigned int addr_width)
185 {
186 	unsigned int addr;
187 
188 	addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
189 
190 	if (addr_width == 4)
191 		addr = (addr << 8) | addr_buf[3];
192 
193 	return addr;
194 }
195 
196 void cadence_qspi_apb_controller_enable(void *reg_base)
197 {
198 	unsigned int reg;
199 	reg = readl(reg_base + CQSPI_REG_CONFIG);
200 	reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
201 	writel(reg, reg_base + CQSPI_REG_CONFIG);
202 	return;
203 }
204 
205 void cadence_qspi_apb_controller_disable(void *reg_base)
206 {
207 	unsigned int reg;
208 	reg = readl(reg_base + CQSPI_REG_CONFIG);
209 	reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
210 	writel(reg, reg_base + CQSPI_REG_CONFIG);
211 	return;
212 }
213 
214 /* Return 1 if idle, otherwise return 0 (busy). */
215 static unsigned int cadence_qspi_wait_idle(void *reg_base)
216 {
217 	unsigned int start, count = 0;
218 	/* timeout in unit of ms */
219 	unsigned int timeout = 5000;
220 
221 	start = get_timer(0);
222 	for ( ; get_timer(start) < timeout ; ) {
223 		if (CQSPI_REG_IS_IDLE(reg_base))
224 			count++;
225 		else
226 			count = 0;
227 		/*
228 		 * Ensure the QSPI controller is in true idle state after
229 		 * reading back the same idle status consecutively
230 		 */
231 		if (count >= CQSPI_POLL_IDLE_RETRY)
232 			return 1;
233 	}
234 
235 	/* Timeout, still in busy mode. */
236 	printf("QSPI: QSPI is still busy after poll for %d times.\n",
237 	       CQSPI_REG_RETRY);
238 	return 0;
239 }
240 
241 void cadence_qspi_apb_readdata_capture(void *reg_base,
242 				unsigned int bypass, unsigned int delay)
243 {
244 	unsigned int reg;
245 	cadence_qspi_apb_controller_disable(reg_base);
246 
247 	reg = readl(reg_base + CQSPI_READLCAPTURE);
248 
249 	if (bypass)
250 		reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
251 	else
252 		reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
253 
254 	reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
255 		<< CQSPI_READLCAPTURE_DELAY_LSB);
256 
257 	reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
258 		<< CQSPI_READLCAPTURE_DELAY_LSB);
259 
260 	writel(reg, reg_base + CQSPI_READLCAPTURE);
261 
262 	cadence_qspi_apb_controller_enable(reg_base);
263 	return;
264 }
265 
266 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
267 	unsigned int ref_clk_hz, unsigned int sclk_hz)
268 {
269 	unsigned int reg;
270 	unsigned int div;
271 
272 	cadence_qspi_apb_controller_disable(reg_base);
273 	reg = readl(reg_base + CQSPI_REG_CONFIG);
274 	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
275 
276 	div = ref_clk_hz / sclk_hz;
277 
278 	if (div > 32)
279 		div = 32;
280 
281 	/* Check if even number. */
282 	if ((div & 1)) {
283 		div = (div / 2);
284 	} else {
285 		if (ref_clk_hz % sclk_hz)
286 			/* ensure generated SCLK doesn't exceed user
287 			specified sclk_hz */
288 			div = (div / 2);
289 		else
290 			div = (div / 2) - 1;
291 	}
292 
293 	debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
294 	      ref_clk_hz, sclk_hz, div);
295 
296 	/* ensure the baud rate doesn't exceed the max value */
297 	if (div > CQSPI_REG_CONFIG_BAUD_MASK)
298 		div = CQSPI_REG_CONFIG_BAUD_MASK;
299 
300 	reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
301 	writel(reg, reg_base + CQSPI_REG_CONFIG);
302 
303 	cadence_qspi_apb_controller_enable(reg_base);
304 	return;
305 }
306 
307 void cadence_qspi_apb_set_clk_mode(void *reg_base,
308 	unsigned int clk_pol, unsigned int clk_pha)
309 {
310 	unsigned int reg;
311 
312 	cadence_qspi_apb_controller_disable(reg_base);
313 	reg = readl(reg_base + CQSPI_REG_CONFIG);
314 	reg &= ~(1 <<
315 		(CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
316 
317 	reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
318 	reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
319 
320 	writel(reg, reg_base + CQSPI_REG_CONFIG);
321 
322 	cadence_qspi_apb_controller_enable(reg_base);
323 	return;
324 }
325 
326 void cadence_qspi_apb_chipselect(void *reg_base,
327 	unsigned int chip_select, unsigned int decoder_enable)
328 {
329 	unsigned int reg;
330 
331 	cadence_qspi_apb_controller_disable(reg_base);
332 
333 	debug("%s : chipselect %d decode %d\n", __func__, chip_select,
334 	      decoder_enable);
335 
336 	reg = readl(reg_base + CQSPI_REG_CONFIG);
337 	/* docoder */
338 	if (decoder_enable) {
339 		reg |= CQSPI_REG_CONFIG_DECODE_MASK;
340 	} else {
341 		reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
342 		/* Convert CS if without decoder.
343 		 * CS0 to 4b'1110
344 		 * CS1 to 4b'1101
345 		 * CS2 to 4b'1011
346 		 * CS3 to 4b'0111
347 		 */
348 		chip_select = 0xF & ~(1 << chip_select);
349 	}
350 
351 	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
352 			<< CQSPI_REG_CONFIG_CHIPSELECT_LSB);
353 	reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
354 			<< CQSPI_REG_CONFIG_CHIPSELECT_LSB;
355 	writel(reg, reg_base + CQSPI_REG_CONFIG);
356 
357 	cadence_qspi_apb_controller_enable(reg_base);
358 	return;
359 }
360 
361 void cadence_qspi_apb_delay(void *reg_base,
362 	unsigned int ref_clk, unsigned int sclk_hz,
363 	unsigned int tshsl_ns, unsigned int tsd2d_ns,
364 	unsigned int tchsh_ns, unsigned int tslch_ns)
365 {
366 	unsigned int ref_clk_ns;
367 	unsigned int sclk_ns;
368 	unsigned int tshsl, tchsh, tslch, tsd2d;
369 	unsigned int reg;
370 
371 	cadence_qspi_apb_controller_disable(reg_base);
372 
373 	/* Convert to ns. */
374 	ref_clk_ns = (1000000000) / ref_clk;
375 
376 	/* Convert to ns. */
377 	sclk_ns = (1000000000) / sclk_hz;
378 
379 	/* Plus 1 to round up 1 clock cycle. */
380 	tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
381 	tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
382 	tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
383 	tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
384 
385 	reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
386 			<< CQSPI_REG_DELAY_TSHSL_LSB);
387 	reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
388 			<< CQSPI_REG_DELAY_TCHSH_LSB);
389 	reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
390 			<< CQSPI_REG_DELAY_TSLCH_LSB);
391 	reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
392 			<< CQSPI_REG_DELAY_TSD2D_LSB);
393 	writel(reg, reg_base + CQSPI_REG_DELAY);
394 
395 	cadence_qspi_apb_controller_enable(reg_base);
396 	return;
397 }
398 
399 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
400 {
401 	unsigned reg;
402 
403 	cadence_qspi_apb_controller_disable(plat->regbase);
404 
405 	/* Configure the device size and address bytes */
406 	reg = readl(plat->regbase + CQSPI_REG_SIZE);
407 	/* Clear the previous value */
408 	reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
409 	reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
410 	reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
411 	reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
412 	writel(reg, plat->regbase + CQSPI_REG_SIZE);
413 
414 	/* Configure the remap address register, no remap */
415 	writel(0, plat->regbase + CQSPI_REG_REMAP);
416 
417 	/* Indirect mode configurations */
418 	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
419 
420 	/* Disable all interrupts */
421 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
422 
423 	cadence_qspi_apb_controller_enable(plat->regbase);
424 	return;
425 }
426 
427 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
428 	unsigned int reg)
429 {
430 	unsigned int retry = CQSPI_REG_RETRY;
431 
432 	/* Write the CMDCTRL without start execution. */
433 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
434 	/* Start execute */
435 	reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
436 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
437 
438 	while (retry--) {
439 		reg = readl(reg_base + CQSPI_REG_CMDCTRL);
440 		if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
441 			break;
442 		udelay(1);
443 	}
444 
445 	if (!retry) {
446 		printf("QSPI: flash command execution timeout\n");
447 		return -EIO;
448 	}
449 
450 	/* Polling QSPI idle status. */
451 	if (!cadence_qspi_wait_idle(reg_base))
452 		return -EIO;
453 
454 	return 0;
455 }
456 
457 /* For command RDID, RDSR. */
458 int cadence_qspi_apb_command_read(void *reg_base,
459 	unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
460 	u8 *rxbuf)
461 {
462 	unsigned int reg;
463 	unsigned int read_len;
464 	int status;
465 
466 	if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
467 		printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
468 		       cmdlen, rxlen);
469 		return -EINVAL;
470 	}
471 
472 	reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
473 
474 	reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
475 
476 	/* 0 means 1 byte. */
477 	reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
478 		<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
479 	status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
480 	if (status != 0)
481 		return status;
482 
483 	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
484 
485 	/* Put the read value into rx_buf */
486 	read_len = (rxlen > 4) ? 4 : rxlen;
487 	memcpy(rxbuf, &reg, read_len);
488 	rxbuf += read_len;
489 
490 	if (rxlen > 4) {
491 		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
492 
493 		read_len = rxlen - read_len;
494 		memcpy(rxbuf, &reg, read_len);
495 	}
496 	return 0;
497 }
498 
499 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
500 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
501 	const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
502 {
503 	unsigned int reg = 0;
504 	unsigned int addr_value;
505 	unsigned int wr_data;
506 	unsigned int wr_len;
507 
508 	if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
509 		printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
510 		       cmdlen, txlen);
511 		return -EINVAL;
512 	}
513 
514 	reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
515 
516 	if (cmdlen == 4 || cmdlen == 5) {
517 		/* Command with address */
518 		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
519 		/* Number of bytes to write. */
520 		reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
521 			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
522 		/* Get address */
523 		addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
524 			cmdlen >= 5 ? 4 : 3);
525 
526 		writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
527 	}
528 
529 	if (txlen) {
530 		/* writing data = yes */
531 		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
532 		reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
533 			<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
534 
535 		wr_len = txlen > 4 ? 4 : txlen;
536 		memcpy(&wr_data, txbuf, wr_len);
537 		writel(wr_data, reg_base +
538 			CQSPI_REG_CMDWRITEDATALOWER);
539 
540 		if (txlen > 4) {
541 			txbuf += wr_len;
542 			wr_len = txlen - wr_len;
543 			memcpy(&wr_data, txbuf, wr_len);
544 			writel(wr_data, reg_base +
545 				CQSPI_REG_CMDWRITEDATAUPPER);
546 		}
547 	}
548 
549 	/* Execute the command */
550 	return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
551 }
552 
553 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
554 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
555 	unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
556 {
557 	unsigned int reg;
558 	unsigned int rd_reg;
559 	unsigned int addr_value;
560 	unsigned int dummy_clk;
561 	unsigned int dummy_bytes;
562 	unsigned int addr_bytes;
563 
564 	/*
565 	 * Identify addr_byte. All NOR flash device drivers are using fast read
566 	 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
567 	 * With that, the length is in value of 5 or 6. Only FRAM chip from
568 	 * ramtron using normal read (which won't need dummy byte).
569 	 * Unlikely NOR flash using normal read due to performance issue.
570 	 */
571 	if (cmdlen >= 5)
572 		/* to cater fast read where cmd + addr + dummy */
573 		addr_bytes = cmdlen - 2;
574 	else
575 		/* for normal read (only ramtron as of now) */
576 		addr_bytes = cmdlen - 1;
577 
578 	/* Setup the indirect trigger address */
579 	writel((u32)plat->ahbbase,
580 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
581 
582 	/* Configure the opcode */
583 	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
584 
585 	if (rx_width & SPI_RX_QUAD)
586 		/* Instruction and address at DQ0, data at DQ0-3. */
587 		rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
588 
589 	/* Get address */
590 	addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
591 	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
592 
593 	/* The remaining lenght is dummy bytes. */
594 	dummy_bytes = cmdlen - addr_bytes - 1;
595 	if (dummy_bytes) {
596 		if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
597 			dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
598 
599 		rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
600 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
601 		writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
602 #else
603 		writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
604 #endif
605 
606 		/* Convert to clock cycles. */
607 		dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
608 		/* Need to minus the mode byte (8 clocks). */
609 		dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
610 
611 		if (dummy_clk)
612 			rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
613 				<< CQSPI_REG_RD_INSTR_DUMMY_LSB;
614 	}
615 
616 	writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
617 
618 	/* set device size */
619 	reg = readl(plat->regbase + CQSPI_REG_SIZE);
620 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
621 	reg |= (addr_bytes - 1);
622 	writel(reg, plat->regbase + CQSPI_REG_SIZE);
623 	return 0;
624 }
625 
626 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
627 {
628 	u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
629 	reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
630 	return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
631 }
632 
633 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
634 {
635 	unsigned int timeout = 10000;
636 	u32 reg;
637 
638 	while (timeout--) {
639 		reg = cadence_qspi_get_rd_sram_level(plat);
640 		if (reg)
641 			return reg;
642 		udelay(1);
643 	}
644 
645 	return -ETIMEDOUT;
646 }
647 
648 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
649 	unsigned int n_rx, u8 *rxbuf)
650 {
651 	unsigned int remaining = n_rx;
652 	unsigned int bytes_to_read = 0;
653 	int ret;
654 
655 	writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
656 
657 	/* Start the indirect read transfer */
658 	writel(CQSPI_REG_INDIRECTRD_START_MASK,
659 	       plat->regbase + CQSPI_REG_INDIRECTRD);
660 
661 	while (remaining > 0) {
662 		ret = cadence_qspi_wait_for_data(plat);
663 		if (ret < 0) {
664 			printf("Indirect write timed out (%i)\n", ret);
665 			goto failrd;
666 		}
667 
668 		bytes_to_read = ret;
669 
670 		while (bytes_to_read != 0) {
671 			bytes_to_read *= CQSPI_FIFO_WIDTH;
672 			bytes_to_read = bytes_to_read > remaining ?
673 					remaining : bytes_to_read;
674 			/* Handle non-4-byte aligned access to avoid data abort. */
675 			if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
676 				readsb(plat->ahbbase, rxbuf, bytes_to_read);
677 			else
678 				readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
679 			rxbuf += bytes_to_read;
680 			remaining -= bytes_to_read;
681 			bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
682 		}
683 	}
684 
685 	/* Check indirect done status */
686 	ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
687 			   CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
688 	if (ret) {
689 		printf("Indirect read completion error (%i)\n", ret);
690 		goto failrd;
691 	}
692 
693 	/* Clear indirect completion status */
694 	writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
695 	       plat->regbase + CQSPI_REG_INDIRECTRD);
696 
697 	return 0;
698 
699 failrd:
700 	/* Cancel the indirect read */
701 	writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
702 	       plat->regbase + CQSPI_REG_INDIRECTRD);
703 	return ret;
704 }
705 
706 /* Opcode + Address (3/4 bytes) */
707 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
708 	unsigned int cmdlen, const u8 *cmdbuf)
709 {
710 	unsigned int reg;
711 	unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
712 
713 	if (cmdlen < 4 || cmdbuf == NULL) {
714 		printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
715 		       cmdlen, (unsigned int)cmdbuf);
716 		return -EINVAL;
717 	}
718 	/* Setup the indirect trigger address */
719 	writel((u32)plat->ahbbase,
720 	       plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
721 
722 	/* Configure the opcode */
723 	reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
724 	writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
725 
726 	/* Setup write address. */
727 	reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
728 	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
729 
730 	reg = readl(plat->regbase + CQSPI_REG_SIZE);
731 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
732 	reg |= (addr_bytes - 1);
733 	writel(reg, plat->regbase + CQSPI_REG_SIZE);
734 	return 0;
735 }
736 
737 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
738 	unsigned int n_tx, const u8 *txbuf)
739 {
740 	unsigned int page_size = plat->page_size;
741 	unsigned int remaining = n_tx;
742 	unsigned int write_bytes;
743 	int ret;
744 
745 	/* Configure the indirect read transfer bytes */
746 	writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
747 
748 	/* Start the indirect write transfer */
749 	writel(CQSPI_REG_INDIRECTWR_START_MASK,
750 	       plat->regbase + CQSPI_REG_INDIRECTWR);
751 
752 	while (remaining > 0) {
753 		write_bytes = remaining > page_size ? page_size : remaining;
754 		/* Handle non-4-byte aligned access to avoid data abort. */
755 		if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
756 			writesb(plat->ahbbase, txbuf, write_bytes);
757 		else
758 			writesl(plat->ahbbase, txbuf, write_bytes >> 2);
759 
760 		ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
761 				   CQSPI_REG_SDRAMLEVEL_WR_MASK <<
762 				   CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
763 		if (ret) {
764 			printf("Indirect write timed out (%i)\n", ret);
765 			goto failwr;
766 		}
767 
768 		txbuf += write_bytes;
769 		remaining -= write_bytes;
770 	}
771 
772 	/* Check indirect done status */
773 	ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
774 			   CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
775 	if (ret) {
776 		printf("Indirect write completion error (%i)\n", ret);
777 		goto failwr;
778 	}
779 
780 	/* Clear indirect completion status */
781 	writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
782 	       plat->regbase + CQSPI_REG_INDIRECTWR);
783 	return 0;
784 
785 failwr:
786 	/* Cancel the indirect write */
787 	writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
788 	       plat->regbase + CQSPI_REG_INDIRECTWR);
789 	return ret;
790 }
791 
792 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
793 {
794 	unsigned int reg;
795 
796 	/* enter XiP mode immediately and enable direct mode */
797 	reg = readl(reg_base + CQSPI_REG_CONFIG);
798 	reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
799 	reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
800 	reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
801 	writel(reg, reg_base + CQSPI_REG_CONFIG);
802 
803 	/* keep the XiP mode */
804 	writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
805 
806 	/* Enable mode bit at devrd */
807 	reg = readl(reg_base + CQSPI_REG_RD_INSTR);
808 	reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
809 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);
810 }
811