110e8bf88SStefan Roese /* 210e8bf88SStefan Roese * Copyright (C) 2012 310e8bf88SStefan Roese * Altera Corporation <www.altera.com> 410e8bf88SStefan Roese * 510e8bf88SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 610e8bf88SStefan Roese */ 710e8bf88SStefan Roese 810e8bf88SStefan Roese #ifndef __CADENCE_QSPI_H__ 910e8bf88SStefan Roese #define __CADENCE_QSPI_H__ 1010e8bf88SStefan Roese 1110e8bf88SStefan Roese #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) 1210e8bf88SStefan Roese 1310e8bf88SStefan Roese #define CQSPI_NO_DECODER_MAX_CS 4 1410e8bf88SStefan Roese #define CQSPI_DECODER_MAX_CS 16 1510e8bf88SStefan Roese #define CQSPI_READ_CAPTURE_MAX_DELAY 16 1610e8bf88SStefan Roese 1710e8bf88SStefan Roese struct cadence_spi_platdata { 1810e8bf88SStefan Roese unsigned int max_hz; 1910e8bf88SStefan Roese void *regbase; 2010e8bf88SStefan Roese void *ahbbase; 2110e8bf88SStefan Roese 2210e8bf88SStefan Roese u32 page_size; 2310e8bf88SStefan Roese u32 block_size; 2410e8bf88SStefan Roese u32 tshsl_ns; 2510e8bf88SStefan Roese u32 tsd2d_ns; 2610e8bf88SStefan Roese u32 tchsh_ns; 2710e8bf88SStefan Roese u32 tslch_ns; 2890a2f717SVikas Manocha u32 sram_size; 2910e8bf88SStefan Roese }; 3010e8bf88SStefan Roese 3110e8bf88SStefan Roese struct cadence_spi_priv { 3210e8bf88SStefan Roese void *regbase; 3310e8bf88SStefan Roese void *ahbbase; 3410e8bf88SStefan Roese size_t cmd_len; 3510e8bf88SStefan Roese u8 cmd_buf[32]; 3610e8bf88SStefan Roese size_t data_len; 3710e8bf88SStefan Roese 3810e8bf88SStefan Roese int qspi_is_init; 3910e8bf88SStefan Roese unsigned int qspi_calibrated_hz; 4010e8bf88SStefan Roese unsigned int qspi_calibrated_cs; 4198fbd71dSChin Liang See unsigned int previous_hz; 4210e8bf88SStefan Roese }; 4310e8bf88SStefan Roese 4410e8bf88SStefan Roese /* Functions call declaration */ 4510e8bf88SStefan Roese void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); 4610e8bf88SStefan Roese void cadence_qspi_apb_controller_enable(void *reg_base_addr); 4710e8bf88SStefan Roese void cadence_qspi_apb_controller_disable(void *reg_base_addr); 4810e8bf88SStefan Roese 4910e8bf88SStefan Roese int cadence_qspi_apb_command_read(void *reg_base_addr, 5010e8bf88SStefan Roese unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf); 5110e8bf88SStefan Roese int cadence_qspi_apb_command_write(void *reg_base_addr, 5210e8bf88SStefan Roese unsigned int cmdlen, const u8 *cmdbuf, 5310e8bf88SStefan Roese unsigned int txlen, const u8 *txbuf); 5410e8bf88SStefan Roese 5510e8bf88SStefan Roese int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, 562372e14fSVignesh R unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf); 5710e8bf88SStefan Roese int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, 5810e8bf88SStefan Roese unsigned int rxlen, u8 *rxbuf); 5910e8bf88SStefan Roese int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, 6010e8bf88SStefan Roese unsigned int cmdlen, const u8 *cmdbuf); 6110e8bf88SStefan Roese int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, 6210e8bf88SStefan Roese unsigned int txlen, const u8 *txbuf); 6310e8bf88SStefan Roese 6410e8bf88SStefan Roese void cadence_qspi_apb_chipselect(void *reg_base, 6510e8bf88SStefan Roese unsigned int chip_select, unsigned int decoder_enable); 66*7d403f28SPhil Edworthy void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); 6710e8bf88SStefan Roese void cadence_qspi_apb_config_baudrate_div(void *reg_base, 6810e8bf88SStefan Roese unsigned int ref_clk_hz, unsigned int sclk_hz); 6910e8bf88SStefan Roese void cadence_qspi_apb_delay(void *reg_base, 7010e8bf88SStefan Roese unsigned int ref_clk, unsigned int sclk_hz, 7110e8bf88SStefan Roese unsigned int tshsl_ns, unsigned int tsd2d_ns, 7210e8bf88SStefan Roese unsigned int tchsh_ns, unsigned int tslch_ns); 7310e8bf88SStefan Roese void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); 7410e8bf88SStefan Roese void cadence_qspi_apb_readdata_capture(void *reg_base, 7510e8bf88SStefan Roese unsigned int bypass, unsigned int delay); 7610e8bf88SStefan Roese 7710e8bf88SStefan Roese #endif /* __CADENCE_QSPI_H__ */ 78