1 /* 2 * Copyright (C) 2012 3 * Altera Corporation <www.altera.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <malloc.h> 12 #include <spi.h> 13 #include <asm/errno.h> 14 #include "cadence_qspi.h" 15 16 #define CQSPI_STIG_READ 0 17 #define CQSPI_STIG_WRITE 1 18 #define CQSPI_INDIRECT_READ 2 19 #define CQSPI_INDIRECT_WRITE 3 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static int cadence_spi_write_speed(struct udevice *bus, uint hz) 24 { 25 struct cadence_spi_platdata *plat = bus->platdata; 26 struct cadence_spi_priv *priv = dev_get_priv(bus); 27 28 cadence_qspi_apb_config_baudrate_div(priv->regbase, 29 CONFIG_CQSPI_REF_CLK, hz); 30 31 /* Reconfigure delay timing if speed is changed. */ 32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, 33 plat->tshsl_ns, plat->tsd2d_ns, 34 plat->tchsh_ns, plat->tslch_ns); 35 36 return 0; 37 } 38 39 /* Calibration sequence to determine the read data capture delay register */ 40 static int spi_calibration(struct udevice *bus) 41 { 42 struct cadence_spi_platdata *plat = bus->platdata; 43 struct cadence_spi_priv *priv = dev_get_priv(bus); 44 void *base = priv->regbase; 45 u8 opcode_rdid = 0x9F; 46 unsigned int idcode = 0, temp = 0; 47 int err = 0, i, range_lo = -1, range_hi = -1; 48 49 /* start with slowest clock (1 MHz) */ 50 cadence_spi_write_speed(bus, 1000000); 51 52 /* configure the read data capture delay register to 0 */ 53 cadence_qspi_apb_readdata_capture(base, 1, 0); 54 55 /* Enable QSPI */ 56 cadence_qspi_apb_controller_enable(base); 57 58 /* read the ID which will be our golden value */ 59 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, 60 3, (u8 *)&idcode); 61 if (err) { 62 puts("SF: Calibration failed (read)\n"); 63 return err; 64 } 65 66 /* use back the intended clock and find low range */ 67 cadence_spi_write_speed(bus, plat->max_hz); 68 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { 69 /* Disable QSPI */ 70 cadence_qspi_apb_controller_disable(base); 71 72 /* reconfigure the read data capture delay register */ 73 cadence_qspi_apb_readdata_capture(base, 1, i); 74 75 /* Enable back QSPI */ 76 cadence_qspi_apb_controller_enable(base); 77 78 /* issue a RDID to get the ID value */ 79 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, 80 3, (u8 *)&temp); 81 if (err) { 82 puts("SF: Calibration failed (read)\n"); 83 return err; 84 } 85 86 /* search for range lo */ 87 if (range_lo == -1 && temp == idcode) { 88 range_lo = i; 89 continue; 90 } 91 92 /* search for range hi */ 93 if (range_lo != -1 && temp != idcode) { 94 range_hi = i - 1; 95 break; 96 } 97 range_hi = i; 98 } 99 100 if (range_lo == -1) { 101 puts("SF: Calibration failed (low range)\n"); 102 return err; 103 } 104 105 /* Disable QSPI for subsequent initialization */ 106 cadence_qspi_apb_controller_disable(base); 107 108 /* configure the final value for read data capture delay register */ 109 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); 110 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", 111 (range_hi + range_lo) / 2, range_lo, range_hi); 112 113 /* just to ensure we do once only when speed or chip select change */ 114 priv->qspi_calibrated_hz = plat->max_hz; 115 priv->qspi_calibrated_cs = spi_chip_select(bus); 116 117 return 0; 118 } 119 120 static int cadence_spi_set_speed(struct udevice *bus, uint hz) 121 { 122 struct cadence_spi_platdata *plat = bus->platdata; 123 struct cadence_spi_priv *priv = dev_get_priv(bus); 124 int err; 125 126 /* Disable QSPI */ 127 cadence_qspi_apb_controller_disable(priv->regbase); 128 129 cadence_spi_write_speed(bus, hz); 130 131 /* Calibration required for different SCLK speed or chip select */ 132 if (priv->qspi_calibrated_hz != plat->max_hz || 133 priv->qspi_calibrated_cs != spi_chip_select(bus)) { 134 err = spi_calibration(bus); 135 if (err) 136 return err; 137 } 138 139 /* Enable QSPI */ 140 cadence_qspi_apb_controller_enable(priv->regbase); 141 142 debug("%s: speed=%d\n", __func__, hz); 143 144 return 0; 145 } 146 147 static int cadence_spi_probe(struct udevice *bus) 148 { 149 struct cadence_spi_platdata *plat = bus->platdata; 150 struct cadence_spi_priv *priv = dev_get_priv(bus); 151 152 priv->regbase = plat->regbase; 153 priv->ahbbase = plat->ahbbase; 154 155 if (!priv->qspi_is_init) { 156 cadence_qspi_apb_controller_init(plat); 157 priv->qspi_is_init = 1; 158 } 159 160 return 0; 161 } 162 163 static int cadence_spi_set_mode(struct udevice *bus, uint mode) 164 { 165 struct cadence_spi_priv *priv = dev_get_priv(bus); 166 unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0; 167 unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0; 168 169 /* Disable QSPI */ 170 cadence_qspi_apb_controller_disable(priv->regbase); 171 172 /* Set SPI mode */ 173 cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); 174 175 /* Enable QSPI */ 176 cadence_qspi_apb_controller_enable(priv->regbase); 177 178 return 0; 179 } 180 181 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, 182 const void *dout, void *din, unsigned long flags) 183 { 184 struct udevice *bus = dev->parent; 185 struct cadence_spi_platdata *plat = bus->platdata; 186 struct cadence_spi_priv *priv = dev_get_priv(bus); 187 void *base = priv->regbase; 188 u8 *cmd_buf = priv->cmd_buf; 189 size_t data_bytes; 190 int err = 0; 191 u32 mode = CQSPI_STIG_WRITE; 192 193 if (flags & SPI_XFER_BEGIN) { 194 /* copy command to local buffer */ 195 priv->cmd_len = bitlen / 8; 196 memcpy(cmd_buf, dout, priv->cmd_len); 197 } 198 199 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 200 /* if start and end bit are set, the data bytes is 0. */ 201 data_bytes = 0; 202 } else { 203 data_bytes = bitlen / 8; 204 } 205 debug("%s: len=%d [bytes]\n", __func__, data_bytes); 206 207 /* Set Chip select */ 208 cadence_qspi_apb_chipselect(base, spi_chip_select(dev), 209 CONFIG_CQSPI_DECODER); 210 211 if ((flags & SPI_XFER_END) || (flags == 0)) { 212 if (priv->cmd_len == 0) { 213 printf("QSPI: Error, command is empty.\n"); 214 return -1; 215 } 216 217 if (din && data_bytes) { 218 /* read */ 219 /* Use STIG if no address. */ 220 if (!CQSPI_IS_ADDR(priv->cmd_len)) 221 mode = CQSPI_STIG_READ; 222 else 223 mode = CQSPI_INDIRECT_READ; 224 } else if (dout && !(flags & SPI_XFER_BEGIN)) { 225 /* write */ 226 if (!CQSPI_IS_ADDR(priv->cmd_len)) 227 mode = CQSPI_STIG_WRITE; 228 else 229 mode = CQSPI_INDIRECT_WRITE; 230 } 231 232 switch (mode) { 233 case CQSPI_STIG_READ: 234 err = cadence_qspi_apb_command_read( 235 base, priv->cmd_len, cmd_buf, 236 data_bytes, din); 237 238 break; 239 case CQSPI_STIG_WRITE: 240 err = cadence_qspi_apb_command_write(base, 241 priv->cmd_len, cmd_buf, 242 data_bytes, dout); 243 break; 244 case CQSPI_INDIRECT_READ: 245 err = cadence_qspi_apb_indirect_read_setup(plat, 246 priv->cmd_len, cmd_buf); 247 if (!err) { 248 err = cadence_qspi_apb_indirect_read_execute 249 (plat, data_bytes, din); 250 } 251 break; 252 case CQSPI_INDIRECT_WRITE: 253 err = cadence_qspi_apb_indirect_write_setup 254 (plat, priv->cmd_len, cmd_buf); 255 if (!err) { 256 err = cadence_qspi_apb_indirect_write_execute 257 (plat, data_bytes, dout); 258 } 259 break; 260 default: 261 err = -1; 262 break; 263 } 264 265 if (flags & SPI_XFER_END) { 266 /* clear command buffer */ 267 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 268 priv->cmd_len = 0; 269 } 270 } 271 272 return err; 273 } 274 275 static int cadence_spi_ofdata_to_platdata(struct udevice *bus) 276 { 277 struct cadence_spi_platdata *plat = bus->platdata; 278 const void *blob = gd->fdt_blob; 279 int node = bus->of_offset; 280 int subnode; 281 u32 data[4]; 282 int ret; 283 284 /* 2 base addresses are needed, lets get them from the DT */ 285 ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); 286 if (ret) { 287 printf("Error: Can't get base addresses (ret=%d)!\n", ret); 288 return -ENODEV; 289 } 290 291 plat->regbase = (void *)data[0]; 292 plat->ahbbase = (void *)data[2]; 293 294 /* Use 500KHz as a suitable default */ 295 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 296 500000); 297 298 /* All other paramters are embedded in the child node */ 299 subnode = fdt_first_subnode(blob, node); 300 if (subnode < 0) { 301 printf("Error: subnode with SPI flash config missing!\n"); 302 return -ENODEV; 303 } 304 305 /* Read other parameters from DT */ 306 plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); 307 plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); 308 plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200); 309 plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); 310 plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); 311 plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); 312 plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); 313 314 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", 315 __func__, plat->regbase, plat->ahbbase, plat->max_hz, 316 plat->page_size); 317 318 return 0; 319 } 320 321 static const struct dm_spi_ops cadence_spi_ops = { 322 .xfer = cadence_spi_xfer, 323 .set_speed = cadence_spi_set_speed, 324 .set_mode = cadence_spi_set_mode, 325 /* 326 * cs_info is not needed, since we require all chip selects to be 327 * in the device tree explicitly 328 */ 329 }; 330 331 static const struct udevice_id cadence_spi_ids[] = { 332 { .compatible = "cadence,qspi" }, 333 { } 334 }; 335 336 U_BOOT_DRIVER(cadence_spi) = { 337 .name = "cadence_spi", 338 .id = UCLASS_SPI, 339 .of_match = cadence_spi_ids, 340 .ops = &cadence_spi_ops, 341 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata, 342 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata), 343 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv), 344 .probe = cadence_spi_probe, 345 }; 346