1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> 4 * 5 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: 6 * Copyright (C) 2000-2010 Broadcom Corporation 7 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org> 8 */ 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <reset.h> 15 #include <wait_bit.h> 16 #include <asm/io.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define HSSPI_PP 0 21 22 #define SPI_MAX_SYNC_CLOCK 30000000 23 24 /* SPI Control register */ 25 #define SPI_CTL_REG 0x000 26 #define SPI_CTL_CS_POL_SHIFT 0 27 #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT) 28 #define SPI_CTL_CLK_GATE_SHIFT 16 29 #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT) 30 #define SPI_CTL_CLK_POL_SHIFT 17 31 #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT) 32 33 /* SPI Interrupts registers */ 34 #define SPI_IR_STAT_REG 0x008 35 #define SPI_IR_ST_MASK_REG 0x00c 36 #define SPI_IR_MASK_REG 0x010 37 38 #define SPI_IR_CLEAR_ALL 0xff001f1f 39 40 /* SPI Ping-Pong Command registers */ 41 #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00) 42 #define SPI_CMD_OP_SHIFT 0 43 #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT) 44 #define SPI_CMD_PFL_SHIFT 8 45 #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT) 46 #define SPI_CMD_SLAVE_SHIFT 12 47 #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT) 48 49 /* SPI Ping-Pong Status registers */ 50 #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04) 51 #define SPI_STAT_SRCBUSY_SHIFT 1 52 #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT) 53 54 /* SPI Profile Clock registers */ 55 #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) 56 #define SPI_PFL_CLK_FREQ_SHIFT 0 57 #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT) 58 #define SPI_PFL_CLK_RSTLOOP_SHIFT 15 59 #define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT) 60 61 /* SPI Profile Signal registers */ 62 #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) 63 #define SPI_PFL_SIG_LATCHRIS_SHIFT 12 64 #define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT) 65 #define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13 66 #define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT) 67 #define SPI_PFL_SIG_ASYNCIN_SHIFT 16 68 #define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT) 69 70 /* SPI Profile Mode registers */ 71 #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) 72 #define SPI_PFL_MODE_FILL_SHIFT 0 73 #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT) 74 #define SPI_PFL_MODE_MDRDSZ_SHIFT 16 75 #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT) 76 #define SPI_PFL_MODE_MDWRSZ_SHIFT 18 77 #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT) 78 #define SPI_PFL_MODE_3WIRE_SHIFT 20 79 #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT) 80 81 /* SPI Ping-Pong FIFO registers */ 82 #define HSSPI_FIFO_SIZE 0x200 83 #define HSSPI_FIFO_BASE (0x200 + \ 84 (HSSPI_FIFO_SIZE * HSSPI_PP)) 85 86 /* SPI Ping-Pong FIFO OP register */ 87 #define HSSPI_FIFO_OP_SIZE 0x2 88 #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00) 89 #define HSSPI_FIFO_OP_BYTES_SHIFT 0 90 #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT) 91 #define HSSPI_FIFO_OP_MBIT_SHIFT 11 92 #define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT) 93 #define HSSPI_FIFO_OP_CODE_SHIFT 13 94 #define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT) 95 #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT) 96 #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT) 97 98 struct bcm63xx_hsspi_priv { 99 void __iomem *regs; 100 ulong clk_rate; 101 uint8_t num_cs; 102 uint8_t cs_pols; 103 uint speed; 104 }; 105 106 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, 107 struct spi_cs_info *info) 108 { 109 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); 110 111 if (cs >= priv->num_cs) { 112 printf("no cs %u\n", cs); 113 return -ENODEV; 114 } 115 116 return 0; 117 } 118 119 static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode) 120 { 121 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); 122 123 /* clock polarity */ 124 if (mode & SPI_CPOL) 125 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); 126 else 127 clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); 128 129 return 0; 130 } 131 132 static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed) 133 { 134 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus); 135 136 priv->speed = speed; 137 138 return 0; 139 } 140 141 static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv, 142 struct dm_spi_slave_platdata *plat) 143 { 144 uint32_t clr, set; 145 146 /* profile clock */ 147 set = DIV_ROUND_UP(priv->clk_rate, priv->speed); 148 set = DIV_ROUND_UP(2048, set); 149 set &= SPI_PFL_CLK_FREQ_MASK; 150 set |= SPI_PFL_CLK_RSTLOOP_MASK; 151 writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); 152 153 /* profile signal */ 154 set = 0; 155 clr = SPI_PFL_SIG_LAUNCHRIS_MASK | 156 SPI_PFL_SIG_LATCHRIS_MASK | 157 SPI_PFL_SIG_ASYNCIN_MASK; 158 159 /* latch/launch config */ 160 if (plat->mode & SPI_CPHA) 161 set |= SPI_PFL_SIG_LAUNCHRIS_MASK; 162 else 163 set |= SPI_PFL_SIG_LATCHRIS_MASK; 164 165 /* async clk */ 166 if (priv->speed > SPI_MAX_SYNC_CLOCK) 167 set |= SPI_PFL_SIG_ASYNCIN_MASK; 168 169 clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); 170 171 /* global control */ 172 set = 0; 173 clr = 0; 174 175 /* invert cs polarity */ 176 if (priv->cs_pols & BIT(plat->cs)) 177 clr |= BIT(plat->cs); 178 else 179 set |= BIT(plat->cs); 180 181 /* invert dummy cs polarity */ 182 if (priv->cs_pols & BIT(!plat->cs)) 183 clr |= BIT(!plat->cs); 184 else 185 set |= BIT(!plat->cs); 186 187 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); 188 } 189 190 static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv) 191 { 192 /* restore cs polarities */ 193 clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, 194 priv->cs_pols); 195 } 196 197 /* 198 * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers 199 * because they are controlled by HW. 200 * However, it provides a mechanism to prepend write transfers prior to read 201 * transfers (with a maximum prepend of 15 bytes), which is usually enough for 202 * SPI-connected flashes since reading requires prepending a write transfer of 203 * 5 bytes. On the other hand it also provides a way to invert each CS 204 * polarity, not only between transfers like the older BCM63xx SPI driver, but 205 * also the rest of the time. 206 * 207 * Instead of using the prepend mechanism, this implementation inverts the 208 * polarity of both the desired CS and another dummy CS when the bus is 209 * claimed. This way, the dummy CS is restored to its inactive value when 210 * transfers are issued and the desired CS is preserved in its active value 211 * all the time. This hack is also used in the upstream linux driver and 212 * allows keeping CS active between trasnfers even if the HW doesn't give 213 * this possibility. 214 */ 215 static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen, 216 const void *dout, void *din, unsigned long flags) 217 { 218 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); 219 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); 220 size_t data_bytes = bitlen / 8; 221 size_t step_size = HSSPI_FIFO_SIZE; 222 uint16_t opcode = 0; 223 uint32_t val; 224 const uint8_t *tx = dout; 225 uint8_t *rx = din; 226 227 if (flags & SPI_XFER_BEGIN) 228 bcm63xx_hsspi_activate_cs(priv, plat); 229 230 /* fifo operation */ 231 if (tx && rx) 232 opcode = HSSPI_FIFO_OP_READ_WRITE; 233 else if (rx) 234 opcode = HSSPI_FIFO_OP_CODE_R; 235 else if (tx) 236 opcode = HSSPI_FIFO_OP_CODE_W; 237 238 if (opcode != HSSPI_FIFO_OP_CODE_R) 239 step_size -= HSSPI_FIFO_OP_SIZE; 240 241 /* dual mode */ 242 if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || 243 (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) 244 opcode |= HSSPI_FIFO_OP_MBIT_MASK; 245 246 /* profile mode */ 247 val = SPI_PFL_MODE_FILL_MASK | 248 SPI_PFL_MODE_MDRDSZ_MASK | 249 SPI_PFL_MODE_MDWRSZ_MASK; 250 if (plat->mode & SPI_3WIRE) 251 val |= SPI_PFL_MODE_3WIRE_MASK; 252 writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); 253 254 /* transfer loop */ 255 while (data_bytes > 0) { 256 size_t curr_step = min(step_size, data_bytes); 257 int ret; 258 259 /* copy tx data */ 260 if (tx) { 261 memcpy_toio(priv->regs + HSSPI_FIFO_BASE + 262 HSSPI_FIFO_OP_SIZE, tx, curr_step); 263 tx += curr_step; 264 } 265 266 /* set fifo operation */ 267 writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK), 268 priv->regs + HSSPI_FIFO_OP_REG); 269 270 /* issue the transfer */ 271 val = SPI_CMD_OP_START; 272 val |= (plat->cs << SPI_CMD_PFL_SHIFT) & 273 SPI_CMD_PFL_MASK; 274 val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) & 275 SPI_CMD_SLAVE_MASK; 276 writel_be(val, priv->regs + SPI_CMD_REG); 277 278 /* wait for completion */ 279 ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG, 280 SPI_STAT_SRCBUSY_MASK, false, 281 1000, false); 282 if (ret) { 283 printf("interrupt timeout\n"); 284 return ret; 285 } 286 287 /* copy rx data */ 288 if (rx) { 289 memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE, 290 curr_step); 291 rx += curr_step; 292 } 293 294 data_bytes -= curr_step; 295 } 296 297 if (flags & SPI_XFER_END) 298 bcm63xx_hsspi_deactivate_cs(priv); 299 300 return 0; 301 } 302 303 static const struct dm_spi_ops bcm63xx_hsspi_ops = { 304 .cs_info = bcm63xx_hsspi_cs_info, 305 .set_mode = bcm63xx_hsspi_set_mode, 306 .set_speed = bcm63xx_hsspi_set_speed, 307 .xfer = bcm63xx_hsspi_xfer, 308 }; 309 310 static const struct udevice_id bcm63xx_hsspi_ids[] = { 311 { .compatible = "brcm,bcm6328-hsspi", }, 312 { /* sentinel */ } 313 }; 314 315 static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev) 316 { 317 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); 318 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); 319 320 /* check cs */ 321 if (plat->cs >= priv->num_cs) { 322 printf("no cs %u\n", plat->cs); 323 return -ENODEV; 324 } 325 326 /* cs polarity */ 327 if (plat->mode & SPI_CS_HIGH) 328 priv->cs_pols |= BIT(plat->cs); 329 else 330 priv->cs_pols &= ~BIT(plat->cs); 331 332 return 0; 333 } 334 335 static int bcm63xx_hsspi_probe(struct udevice *dev) 336 { 337 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev); 338 struct reset_ctl rst_ctl; 339 struct clk clk; 340 fdt_addr_t addr; 341 fdt_size_t size; 342 int ret; 343 344 addr = devfdt_get_addr_size_index(dev, 0, &size); 345 if (addr == FDT_ADDR_T_NONE) 346 return -EINVAL; 347 348 priv->regs = ioremap(addr, size); 349 priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), 350 "num-cs", 8); 351 352 /* enable clock */ 353 ret = clk_get_by_name(dev, "hsspi", &clk); 354 if (ret < 0) 355 return ret; 356 357 ret = clk_enable(&clk); 358 if (ret < 0) 359 return ret; 360 361 ret = clk_free(&clk); 362 if (ret < 0) 363 return ret; 364 365 /* get clock rate */ 366 ret = clk_get_by_name(dev, "pll", &clk); 367 if (ret < 0) 368 return ret; 369 370 priv->clk_rate = clk_get_rate(&clk); 371 372 ret = clk_free(&clk); 373 if (ret < 0) 374 return ret; 375 376 /* perform reset */ 377 ret = reset_get_by_index(dev, 0, &rst_ctl); 378 if (ret < 0) 379 return ret; 380 381 ret = reset_deassert(&rst_ctl); 382 if (ret < 0) 383 return ret; 384 385 ret = reset_free(&rst_ctl); 386 if (ret < 0) 387 return ret; 388 389 /* initialize hardware */ 390 writel_be(0, priv->regs + SPI_IR_MASK_REG); 391 392 /* clear pending interrupts */ 393 writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); 394 395 /* enable clk gate */ 396 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); 397 398 /* read default cs polarities */ 399 priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & 400 SPI_CTL_CS_POL_MASK; 401 402 return 0; 403 } 404 405 U_BOOT_DRIVER(bcm63xx_hsspi) = { 406 .name = "bcm63xx_hsspi", 407 .id = UCLASS_SPI, 408 .of_match = bcm63xx_hsspi_ids, 409 .ops = &bcm63xx_hsspi_ops, 410 .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv), 411 .child_pre_probe = bcm63xx_hsspi_child_pre_probe, 412 .probe = bcm63xx_hsspi_probe, 413 }; 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