1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
6 * Copyright (C) 2000-2010 Broadcom Corporation
7 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <spi.h>
14 #include <reset.h>
15 #include <wait_bit.h>
16 #include <asm/io.h>
17
18 #define HSSPI_PP 0
19
20 #define SPI_MAX_SYNC_CLOCK 30000000
21
22 /* SPI Control register */
23 #define SPI_CTL_REG 0x000
24 #define SPI_CTL_CS_POL_SHIFT 0
25 #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
26 #define SPI_CTL_CLK_GATE_SHIFT 16
27 #define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
28 #define SPI_CTL_CLK_POL_SHIFT 17
29 #define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
30
31 /* SPI Interrupts registers */
32 #define SPI_IR_STAT_REG 0x008
33 #define SPI_IR_ST_MASK_REG 0x00c
34 #define SPI_IR_MASK_REG 0x010
35
36 #define SPI_IR_CLEAR_ALL 0xff001f1f
37
38 /* SPI Ping-Pong Command registers */
39 #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
40 #define SPI_CMD_OP_SHIFT 0
41 #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
42 #define SPI_CMD_PFL_SHIFT 8
43 #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
44 #define SPI_CMD_SLAVE_SHIFT 12
45 #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
46
47 /* SPI Ping-Pong Status registers */
48 #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
49 #define SPI_STAT_SRCBUSY_SHIFT 1
50 #define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
51
52 /* SPI Profile Clock registers */
53 #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
54 #define SPI_PFL_CLK_FREQ_SHIFT 0
55 #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
56 #define SPI_PFL_CLK_RSTLOOP_SHIFT 15
57 #define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
58
59 /* SPI Profile Signal registers */
60 #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
61 #define SPI_PFL_SIG_LATCHRIS_SHIFT 12
62 #define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
63 #define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
64 #define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
65 #define SPI_PFL_SIG_ASYNCIN_SHIFT 16
66 #define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
67
68 /* SPI Profile Mode registers */
69 #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
70 #define SPI_PFL_MODE_FILL_SHIFT 0
71 #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
72 #define SPI_PFL_MODE_MDRDSZ_SHIFT 16
73 #define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
74 #define SPI_PFL_MODE_MDWRSZ_SHIFT 18
75 #define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
76 #define SPI_PFL_MODE_3WIRE_SHIFT 20
77 #define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
78
79 /* SPI Ping-Pong FIFO registers */
80 #define HSSPI_FIFO_SIZE 0x200
81 #define HSSPI_FIFO_BASE (0x200 + \
82 (HSSPI_FIFO_SIZE * HSSPI_PP))
83
84 /* SPI Ping-Pong FIFO OP register */
85 #define HSSPI_FIFO_OP_SIZE 0x2
86 #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
87 #define HSSPI_FIFO_OP_BYTES_SHIFT 0
88 #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
89 #define HSSPI_FIFO_OP_MBIT_SHIFT 11
90 #define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
91 #define HSSPI_FIFO_OP_CODE_SHIFT 13
92 #define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
93 #define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
94 #define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
95
96 struct bcm63xx_hsspi_priv {
97 void __iomem *regs;
98 ulong clk_rate;
99 uint8_t num_cs;
100 uint8_t cs_pols;
101 uint speed;
102 };
103
bcm63xx_hsspi_cs_info(struct udevice * bus,uint cs,struct spi_cs_info * info)104 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
105 struct spi_cs_info *info)
106 {
107 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
108
109 if (cs >= priv->num_cs) {
110 printf("no cs %u\n", cs);
111 return -ENODEV;
112 }
113
114 return 0;
115 }
116
bcm63xx_hsspi_set_mode(struct udevice * bus,uint mode)117 static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
118 {
119 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
120
121 /* clock polarity */
122 if (mode & SPI_CPOL)
123 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
124 else
125 clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
126
127 return 0;
128 }
129
bcm63xx_hsspi_set_speed(struct udevice * bus,uint speed)130 static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
131 {
132 struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
133
134 priv->speed = speed;
135
136 return 0;
137 }
138
bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv * priv,struct dm_spi_slave_platdata * plat)139 static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
140 struct dm_spi_slave_platdata *plat)
141 {
142 uint32_t clr, set;
143
144 /* profile clock */
145 set = DIV_ROUND_UP(priv->clk_rate, priv->speed);
146 set = DIV_ROUND_UP(2048, set);
147 set &= SPI_PFL_CLK_FREQ_MASK;
148 set |= SPI_PFL_CLK_RSTLOOP_MASK;
149 writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
150
151 /* profile signal */
152 set = 0;
153 clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
154 SPI_PFL_SIG_LATCHRIS_MASK |
155 SPI_PFL_SIG_ASYNCIN_MASK;
156
157 /* latch/launch config */
158 if (plat->mode & SPI_CPHA)
159 set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
160 else
161 set |= SPI_PFL_SIG_LATCHRIS_MASK;
162
163 /* async clk */
164 if (priv->speed > SPI_MAX_SYNC_CLOCK)
165 set |= SPI_PFL_SIG_ASYNCIN_MASK;
166
167 clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
168
169 /* global control */
170 set = 0;
171 clr = 0;
172
173 /* invert cs polarity */
174 if (priv->cs_pols & BIT(plat->cs))
175 clr |= BIT(plat->cs);
176 else
177 set |= BIT(plat->cs);
178
179 /* invert dummy cs polarity */
180 if (priv->cs_pols & BIT(!plat->cs))
181 clr |= BIT(!plat->cs);
182 else
183 set |= BIT(!plat->cs);
184
185 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);
186 }
187
bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv * priv)188 static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
189 {
190 /* restore cs polarities */
191 clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
192 priv->cs_pols);
193 }
194
195 /*
196 * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
197 * because they are controlled by HW.
198 * However, it provides a mechanism to prepend write transfers prior to read
199 * transfers (with a maximum prepend of 15 bytes), which is usually enough for
200 * SPI-connected flashes since reading requires prepending a write transfer of
201 * 5 bytes. On the other hand it also provides a way to invert each CS
202 * polarity, not only between transfers like the older BCM63xx SPI driver, but
203 * also the rest of the time.
204 *
205 * Instead of using the prepend mechanism, this implementation inverts the
206 * polarity of both the desired CS and another dummy CS when the bus is
207 * claimed. This way, the dummy CS is restored to its inactive value when
208 * transfers are issued and the desired CS is preserved in its active value
209 * all the time. This hack is also used in the upstream linux driver and
210 * allows keeping CS active between trasnfers even if the HW doesn't give
211 * this possibility.
212 */
bcm63xx_hsspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)213 static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
214 const void *dout, void *din, unsigned long flags)
215 {
216 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
217 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
218 size_t data_bytes = bitlen / 8;
219 size_t step_size = HSSPI_FIFO_SIZE;
220 uint16_t opcode = 0;
221 uint32_t val;
222 const uint8_t *tx = dout;
223 uint8_t *rx = din;
224
225 if (flags & SPI_XFER_BEGIN)
226 bcm63xx_hsspi_activate_cs(priv, plat);
227
228 /* fifo operation */
229 if (tx && rx)
230 opcode = HSSPI_FIFO_OP_READ_WRITE;
231 else if (rx)
232 opcode = HSSPI_FIFO_OP_CODE_R;
233 else if (tx)
234 opcode = HSSPI_FIFO_OP_CODE_W;
235
236 if (opcode != HSSPI_FIFO_OP_CODE_R)
237 step_size -= HSSPI_FIFO_OP_SIZE;
238
239 /* dual mode */
240 if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
241 (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
242 opcode |= HSSPI_FIFO_OP_MBIT_MASK;
243
244 /* profile mode */
245 val = SPI_PFL_MODE_FILL_MASK |
246 SPI_PFL_MODE_MDRDSZ_MASK |
247 SPI_PFL_MODE_MDWRSZ_MASK;
248 if (plat->mode & SPI_3WIRE)
249 val |= SPI_PFL_MODE_3WIRE_MASK;
250 writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
251
252 /* transfer loop */
253 while (data_bytes > 0) {
254 size_t curr_step = min(step_size, data_bytes);
255 int ret;
256
257 /* copy tx data */
258 if (tx) {
259 memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
260 HSSPI_FIFO_OP_SIZE, tx, curr_step);
261 tx += curr_step;
262 }
263
264 /* set fifo operation */
265 writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK),
266 priv->regs + HSSPI_FIFO_OP_REG);
267
268 /* issue the transfer */
269 val = SPI_CMD_OP_START;
270 val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
271 SPI_CMD_PFL_MASK;
272 val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
273 SPI_CMD_SLAVE_MASK;
274 writel_be(val, priv->regs + SPI_CMD_REG);
275
276 /* wait for completion */
277 ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG,
278 SPI_STAT_SRCBUSY_MASK, false,
279 1000, false);
280 if (ret) {
281 printf("interrupt timeout\n");
282 return ret;
283 }
284
285 /* copy rx data */
286 if (rx) {
287 memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
288 curr_step);
289 rx += curr_step;
290 }
291
292 data_bytes -= curr_step;
293 }
294
295 if (flags & SPI_XFER_END)
296 bcm63xx_hsspi_deactivate_cs(priv);
297
298 return 0;
299 }
300
301 static const struct dm_spi_ops bcm63xx_hsspi_ops = {
302 .cs_info = bcm63xx_hsspi_cs_info,
303 .set_mode = bcm63xx_hsspi_set_mode,
304 .set_speed = bcm63xx_hsspi_set_speed,
305 .xfer = bcm63xx_hsspi_xfer,
306 };
307
308 static const struct udevice_id bcm63xx_hsspi_ids[] = {
309 { .compatible = "brcm,bcm6328-hsspi", },
310 { /* sentinel */ }
311 };
312
bcm63xx_hsspi_child_pre_probe(struct udevice * dev)313 static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
314 {
315 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
316 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
317
318 /* check cs */
319 if (plat->cs >= priv->num_cs) {
320 printf("no cs %u\n", plat->cs);
321 return -ENODEV;
322 }
323
324 /* cs polarity */
325 if (plat->mode & SPI_CS_HIGH)
326 priv->cs_pols |= BIT(plat->cs);
327 else
328 priv->cs_pols &= ~BIT(plat->cs);
329
330 return 0;
331 }
332
bcm63xx_hsspi_probe(struct udevice * dev)333 static int bcm63xx_hsspi_probe(struct udevice *dev)
334 {
335 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
336 struct reset_ctl rst_ctl;
337 struct clk clk;
338 int ret;
339
340 priv->regs = dev_remap_addr(dev);
341 if (!priv->regs)
342 return -EINVAL;
343
344 priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
345
346 /* enable clock */
347 ret = clk_get_by_name(dev, "hsspi", &clk);
348 if (ret < 0)
349 return ret;
350
351 ret = clk_enable(&clk);
352 if (ret < 0)
353 return ret;
354
355 ret = clk_free(&clk);
356 if (ret < 0)
357 return ret;
358
359 /* get clock rate */
360 ret = clk_get_by_name(dev, "pll", &clk);
361 if (ret < 0)
362 return ret;
363
364 priv->clk_rate = clk_get_rate(&clk);
365
366 ret = clk_free(&clk);
367 if (ret < 0)
368 return ret;
369
370 /* perform reset */
371 ret = reset_get_by_index(dev, 0, &rst_ctl);
372 if (ret < 0)
373 return ret;
374
375 ret = reset_deassert(&rst_ctl);
376 if (ret < 0)
377 return ret;
378
379 ret = reset_free(&rst_ctl);
380 if (ret < 0)
381 return ret;
382
383 /* initialize hardware */
384 writel_be(0, priv->regs + SPI_IR_MASK_REG);
385
386 /* clear pending interrupts */
387 writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
388
389 /* enable clk gate */
390 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
391
392 /* read default cs polarities */
393 priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &
394 SPI_CTL_CS_POL_MASK;
395
396 return 0;
397 }
398
399 U_BOOT_DRIVER(bcm63xx_hsspi) = {
400 .name = "bcm63xx_hsspi",
401 .id = UCLASS_SPI,
402 .of_match = bcm63xx_hsspi_ids,
403 .ops = &bcm63xx_hsspi_ops,
404 .priv_auto_alloc_size = sizeof(struct bcm63xx_hsspi_priv),
405 .child_pre_probe = bcm63xx_hsspi_child_pre_probe,
406 .probe = bcm63xx_hsspi_probe,
407 };
408