1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2007 Atmel Corporation 4 */ 5 #include <common.h> 6 #include <clk.h> 7 #include <dm.h> 8 #include <fdtdec.h> 9 #include <spi.h> 10 #include <malloc.h> 11 #include <wait_bit.h> 12 13 #include <asm/io.h> 14 15 #include <asm/arch/clk.h> 16 #include <asm/arch/hardware.h> 17 #ifdef CONFIG_DM_SPI 18 #include <asm/arch/at91_spi.h> 19 #endif 20 #ifdef CONFIG_DM_GPIO 21 #include <asm/gpio.h> 22 #endif 23 24 #include "atmel_spi.h" 25 26 #ifndef CONFIG_DM_SPI 27 28 static int spi_has_wdrbt(struct atmel_spi_slave *slave) 29 { 30 unsigned int ver; 31 32 ver = spi_readl(slave, VERSION); 33 34 return (ATMEL_SPI_VERSION_REV(ver) >= 0x210); 35 } 36 37 void spi_init() 38 { 39 40 } 41 42 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 43 unsigned int max_hz, unsigned int mode) 44 { 45 struct atmel_spi_slave *as; 46 unsigned int scbr; 47 u32 csrx; 48 void *regs; 49 50 if (!spi_cs_is_valid(bus, cs)) 51 return NULL; 52 53 switch (bus) { 54 case 0: 55 regs = (void *)ATMEL_BASE_SPI0; 56 break; 57 #ifdef ATMEL_BASE_SPI1 58 case 1: 59 regs = (void *)ATMEL_BASE_SPI1; 60 break; 61 #endif 62 #ifdef ATMEL_BASE_SPI2 63 case 2: 64 regs = (void *)ATMEL_BASE_SPI2; 65 break; 66 #endif 67 #ifdef ATMEL_BASE_SPI3 68 case 3: 69 regs = (void *)ATMEL_BASE_SPI3; 70 break; 71 #endif 72 default: 73 return NULL; 74 } 75 76 77 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; 78 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) 79 /* Too low max SCK rate */ 80 return NULL; 81 if (scbr < 1) 82 scbr = 1; 83 84 csrx = ATMEL_SPI_CSRx_SCBR(scbr); 85 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); 86 if (!(mode & SPI_CPHA)) 87 csrx |= ATMEL_SPI_CSRx_NCPHA; 88 if (mode & SPI_CPOL) 89 csrx |= ATMEL_SPI_CSRx_CPOL; 90 91 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); 92 if (!as) 93 return NULL; 94 95 as->regs = regs; 96 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS 97 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); 98 if (spi_has_wdrbt(as)) 99 as->mr |= ATMEL_SPI_MR_WDRBT; 100 101 spi_writel(as, CSR(cs), csrx); 102 103 return &as->slave; 104 } 105 106 void spi_free_slave(struct spi_slave *slave) 107 { 108 struct atmel_spi_slave *as = to_atmel_spi(slave); 109 110 free(as); 111 } 112 113 int spi_claim_bus(struct spi_slave *slave) 114 { 115 struct atmel_spi_slave *as = to_atmel_spi(slave); 116 117 /* Enable the SPI hardware */ 118 spi_writel(as, CR, ATMEL_SPI_CR_SPIEN); 119 120 /* 121 * Select the slave. This should set SCK to the correct 122 * initial state, etc. 123 */ 124 spi_writel(as, MR, as->mr); 125 126 return 0; 127 } 128 129 void spi_release_bus(struct spi_slave *slave) 130 { 131 struct atmel_spi_slave *as = to_atmel_spi(slave); 132 133 /* Disable the SPI hardware */ 134 spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS); 135 } 136 137 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 138 const void *dout, void *din, unsigned long flags) 139 { 140 struct atmel_spi_slave *as = to_atmel_spi(slave); 141 unsigned int len_tx; 142 unsigned int len_rx; 143 unsigned int len; 144 u32 status; 145 const u8 *txp = dout; 146 u8 *rxp = din; 147 u8 value; 148 149 if (bitlen == 0) 150 /* Finish any previously submitted transfers */ 151 goto out; 152 153 /* 154 * TODO: The controller can do non-multiple-of-8 bit 155 * transfers, but this driver currently doesn't support it. 156 * 157 * It's also not clear how such transfers are supposed to be 158 * represented as a stream of bytes...this is a limitation of 159 * the current SPI interface. 160 */ 161 if (bitlen % 8) { 162 /* Errors always terminate an ongoing transfer */ 163 flags |= SPI_XFER_END; 164 goto out; 165 } 166 167 len = bitlen / 8; 168 169 /* 170 * The controller can do automatic CS control, but it is 171 * somewhat quirky, and it doesn't really buy us much anyway 172 * in the context of U-Boot. 173 */ 174 if (flags & SPI_XFER_BEGIN) { 175 spi_cs_activate(slave); 176 /* 177 * sometimes the RDR is not empty when we get here, 178 * in theory that should not happen, but it DOES happen. 179 * Read it here to be on the safe side. 180 * That also clears the OVRES flag. Required if the 181 * following loop exits due to OVRES! 182 */ 183 spi_readl(as, RDR); 184 } 185 186 for (len_tx = 0, len_rx = 0; len_rx < len; ) { 187 status = spi_readl(as, SR); 188 189 if (status & ATMEL_SPI_SR_OVRES) 190 return -1; 191 192 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) { 193 if (txp) 194 value = *txp++; 195 else 196 value = 0; 197 spi_writel(as, TDR, value); 198 len_tx++; 199 } 200 if (status & ATMEL_SPI_SR_RDRF) { 201 value = spi_readl(as, RDR); 202 if (rxp) 203 *rxp++ = value; 204 len_rx++; 205 } 206 } 207 208 out: 209 if (flags & SPI_XFER_END) { 210 /* 211 * Wait until the transfer is completely done before 212 * we deactivate CS. 213 */ 214 do { 215 status = spi_readl(as, SR); 216 } while (!(status & ATMEL_SPI_SR_TXEMPTY)); 217 218 spi_cs_deactivate(slave); 219 } 220 221 return 0; 222 } 223 224 #else 225 226 #define MAX_CS_COUNT 4 227 228 struct atmel_spi_platdata { 229 struct at91_spi *regs; 230 }; 231 232 struct atmel_spi_priv { 233 unsigned int freq; /* Default frequency */ 234 unsigned int mode; 235 ulong bus_clk_rate; 236 #ifdef CONFIG_DM_GPIO 237 struct gpio_desc cs_gpios[MAX_CS_COUNT]; 238 #endif 239 }; 240 241 static int atmel_spi_claim_bus(struct udevice *dev) 242 { 243 struct udevice *bus = dev_get_parent(dev); 244 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 245 struct atmel_spi_priv *priv = dev_get_priv(bus); 246 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 247 struct at91_spi *reg_base = bus_plat->regs; 248 u32 cs = slave_plat->cs; 249 u32 freq = priv->freq; 250 u32 scbr, csrx, mode; 251 252 scbr = (priv->bus_clk_rate + freq - 1) / freq; 253 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) 254 return -EINVAL; 255 256 if (scbr < 1) 257 scbr = 1; 258 259 csrx = ATMEL_SPI_CSRx_SCBR(scbr); 260 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); 261 262 if (!(priv->mode & SPI_CPHA)) 263 csrx |= ATMEL_SPI_CSRx_NCPHA; 264 if (priv->mode & SPI_CPOL) 265 csrx |= ATMEL_SPI_CSRx_CPOL; 266 267 writel(csrx, ®_base->csr[cs]); 268 269 mode = ATMEL_SPI_MR_MSTR | 270 ATMEL_SPI_MR_MODFDIS | 271 ATMEL_SPI_MR_WDRBT | 272 ATMEL_SPI_MR_PCS(~(1 << cs)); 273 274 writel(mode, ®_base->mr); 275 276 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr); 277 278 return 0; 279 } 280 281 static int atmel_spi_release_bus(struct udevice *dev) 282 { 283 struct udevice *bus = dev_get_parent(dev); 284 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 285 286 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr); 287 288 return 0; 289 } 290 291 static void atmel_spi_cs_activate(struct udevice *dev) 292 { 293 #ifdef CONFIG_DM_GPIO 294 struct udevice *bus = dev_get_parent(dev); 295 struct atmel_spi_priv *priv = dev_get_priv(bus); 296 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 297 u32 cs = slave_plat->cs; 298 299 if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) 300 return; 301 302 dm_gpio_set_value(&priv->cs_gpios[cs], 0); 303 #endif 304 } 305 306 static void atmel_spi_cs_deactivate(struct udevice *dev) 307 { 308 #ifdef CONFIG_DM_GPIO 309 struct udevice *bus = dev_get_parent(dev); 310 struct atmel_spi_priv *priv = dev_get_priv(bus); 311 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 312 u32 cs = slave_plat->cs; 313 314 if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) 315 return; 316 317 dm_gpio_set_value(&priv->cs_gpios[cs], 1); 318 #endif 319 } 320 321 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen, 322 const void *dout, void *din, unsigned long flags) 323 { 324 struct udevice *bus = dev_get_parent(dev); 325 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 326 struct at91_spi *reg_base = bus_plat->regs; 327 328 u32 len_tx, len_rx, len; 329 u32 status; 330 const u8 *txp = dout; 331 u8 *rxp = din; 332 u8 value; 333 334 if (bitlen == 0) 335 goto out; 336 337 /* 338 * The controller can do non-multiple-of-8 bit 339 * transfers, but this driver currently doesn't support it. 340 * 341 * It's also not clear how such transfers are supposed to be 342 * represented as a stream of bytes...this is a limitation of 343 * the current SPI interface. 344 */ 345 if (bitlen % 8) { 346 /* Errors always terminate an ongoing transfer */ 347 flags |= SPI_XFER_END; 348 goto out; 349 } 350 351 len = bitlen / 8; 352 353 /* 354 * The controller can do automatic CS control, but it is 355 * somewhat quirky, and it doesn't really buy us much anyway 356 * in the context of U-Boot. 357 */ 358 if (flags & SPI_XFER_BEGIN) { 359 atmel_spi_cs_activate(dev); 360 361 /* 362 * sometimes the RDR is not empty when we get here, 363 * in theory that should not happen, but it DOES happen. 364 * Read it here to be on the safe side. 365 * That also clears the OVRES flag. Required if the 366 * following loop exits due to OVRES! 367 */ 368 readl(®_base->rdr); 369 } 370 371 for (len_tx = 0, len_rx = 0; len_rx < len; ) { 372 status = readl(®_base->sr); 373 374 if (status & ATMEL_SPI_SR_OVRES) 375 return -1; 376 377 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) { 378 if (txp) 379 value = *txp++; 380 else 381 value = 0; 382 writel(value, ®_base->tdr); 383 len_tx++; 384 } 385 386 if (status & ATMEL_SPI_SR_RDRF) { 387 value = readl(®_base->rdr); 388 if (rxp) 389 *rxp++ = value; 390 len_rx++; 391 } 392 } 393 394 out: 395 if (flags & SPI_XFER_END) { 396 /* 397 * Wait until the transfer is completely done before 398 * we deactivate CS. 399 */ 400 wait_for_bit_le32(®_base->sr, 401 ATMEL_SPI_SR_TXEMPTY, true, 1000, false); 402 403 atmel_spi_cs_deactivate(dev); 404 } 405 406 return 0; 407 } 408 409 static int atmel_spi_set_speed(struct udevice *bus, uint speed) 410 { 411 struct atmel_spi_priv *priv = dev_get_priv(bus); 412 413 priv->freq = speed; 414 415 return 0; 416 } 417 418 static int atmel_spi_set_mode(struct udevice *bus, uint mode) 419 { 420 struct atmel_spi_priv *priv = dev_get_priv(bus); 421 422 priv->mode = mode; 423 424 return 0; 425 } 426 427 static const struct dm_spi_ops atmel_spi_ops = { 428 .claim_bus = atmel_spi_claim_bus, 429 .release_bus = atmel_spi_release_bus, 430 .xfer = atmel_spi_xfer, 431 .set_speed = atmel_spi_set_speed, 432 .set_mode = atmel_spi_set_mode, 433 /* 434 * cs_info is not needed, since we require all chip selects to be 435 * in the device tree explicitly 436 */ 437 }; 438 439 static int atmel_spi_enable_clk(struct udevice *bus) 440 { 441 struct atmel_spi_priv *priv = dev_get_priv(bus); 442 struct clk clk; 443 ulong clk_rate; 444 int ret; 445 446 ret = clk_get_by_index(bus, 0, &clk); 447 if (ret) 448 return -EINVAL; 449 450 ret = clk_enable(&clk); 451 if (ret) 452 return ret; 453 454 clk_rate = clk_get_rate(&clk); 455 if (!clk_rate) 456 return -EINVAL; 457 458 priv->bus_clk_rate = clk_rate; 459 460 clk_free(&clk); 461 462 return 0; 463 } 464 465 static int atmel_spi_probe(struct udevice *bus) 466 { 467 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 468 int ret; 469 470 ret = atmel_spi_enable_clk(bus); 471 if (ret) 472 return ret; 473 474 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus); 475 476 #ifdef CONFIG_DM_GPIO 477 struct atmel_spi_priv *priv = dev_get_priv(bus); 478 int i; 479 480 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios, 481 ARRAY_SIZE(priv->cs_gpios), 0); 482 if (ret < 0) { 483 pr_err("Can't get %s gpios! Error: %d", bus->name, ret); 484 return ret; 485 } 486 487 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) { 488 if (!dm_gpio_is_valid(&priv->cs_gpios[i])) 489 continue; 490 491 dm_gpio_set_dir_flags(&priv->cs_gpios[i], 492 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 493 } 494 #endif 495 496 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr); 497 498 return 0; 499 } 500 501 static const struct udevice_id atmel_spi_ids[] = { 502 { .compatible = "atmel,at91rm9200-spi" }, 503 { } 504 }; 505 506 U_BOOT_DRIVER(atmel_spi) = { 507 .name = "atmel_spi", 508 .id = UCLASS_SPI, 509 .of_match = atmel_spi_ids, 510 .ops = &atmel_spi_ops, 511 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata), 512 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), 513 .probe = atmel_spi_probe, 514 }; 515 #endif 516