1 /* 2 * Copyright (C) 2007 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <spi.h> 11 #include <malloc.h> 12 #include <wait_bit.h> 13 14 #include <asm/io.h> 15 16 #include <asm/arch/clk.h> 17 #include <asm/arch/hardware.h> 18 #ifdef CONFIG_DM_SPI 19 #include <asm/arch/at91_spi.h> 20 #endif 21 #ifdef CONFIG_DM_GPIO 22 #include <asm/gpio.h> 23 #endif 24 25 #include "atmel_spi.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #ifndef CONFIG_DM_SPI 30 31 static int spi_has_wdrbt(struct atmel_spi_slave *slave) 32 { 33 unsigned int ver; 34 35 ver = spi_readl(slave, VERSION); 36 37 return (ATMEL_SPI_VERSION_REV(ver) >= 0x210); 38 } 39 40 void spi_init() 41 { 42 43 } 44 45 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 46 unsigned int max_hz, unsigned int mode) 47 { 48 struct atmel_spi_slave *as; 49 unsigned int scbr; 50 u32 csrx; 51 void *regs; 52 53 if (!spi_cs_is_valid(bus, cs)) 54 return NULL; 55 56 switch (bus) { 57 case 0: 58 regs = (void *)ATMEL_BASE_SPI0; 59 break; 60 #ifdef ATMEL_BASE_SPI1 61 case 1: 62 regs = (void *)ATMEL_BASE_SPI1; 63 break; 64 #endif 65 #ifdef ATMEL_BASE_SPI2 66 case 2: 67 regs = (void *)ATMEL_BASE_SPI2; 68 break; 69 #endif 70 #ifdef ATMEL_BASE_SPI3 71 case 3: 72 regs = (void *)ATMEL_BASE_SPI3; 73 break; 74 #endif 75 default: 76 return NULL; 77 } 78 79 80 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; 81 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) 82 /* Too low max SCK rate */ 83 return NULL; 84 if (scbr < 1) 85 scbr = 1; 86 87 csrx = ATMEL_SPI_CSRx_SCBR(scbr); 88 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); 89 if (!(mode & SPI_CPHA)) 90 csrx |= ATMEL_SPI_CSRx_NCPHA; 91 if (mode & SPI_CPOL) 92 csrx |= ATMEL_SPI_CSRx_CPOL; 93 94 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); 95 if (!as) 96 return NULL; 97 98 as->regs = regs; 99 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS 100 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); 101 if (spi_has_wdrbt(as)) 102 as->mr |= ATMEL_SPI_MR_WDRBT; 103 104 spi_writel(as, CSR(cs), csrx); 105 106 return &as->slave; 107 } 108 109 void spi_free_slave(struct spi_slave *slave) 110 { 111 struct atmel_spi_slave *as = to_atmel_spi(slave); 112 113 free(as); 114 } 115 116 int spi_claim_bus(struct spi_slave *slave) 117 { 118 struct atmel_spi_slave *as = to_atmel_spi(slave); 119 120 /* Enable the SPI hardware */ 121 spi_writel(as, CR, ATMEL_SPI_CR_SPIEN); 122 123 /* 124 * Select the slave. This should set SCK to the correct 125 * initial state, etc. 126 */ 127 spi_writel(as, MR, as->mr); 128 129 return 0; 130 } 131 132 void spi_release_bus(struct spi_slave *slave) 133 { 134 struct atmel_spi_slave *as = to_atmel_spi(slave); 135 136 /* Disable the SPI hardware */ 137 spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS); 138 } 139 140 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, 141 const void *dout, void *din, unsigned long flags) 142 { 143 struct atmel_spi_slave *as = to_atmel_spi(slave); 144 unsigned int len_tx; 145 unsigned int len_rx; 146 unsigned int len; 147 u32 status; 148 const u8 *txp = dout; 149 u8 *rxp = din; 150 u8 value; 151 152 if (bitlen == 0) 153 /* Finish any previously submitted transfers */ 154 goto out; 155 156 /* 157 * TODO: The controller can do non-multiple-of-8 bit 158 * transfers, but this driver currently doesn't support it. 159 * 160 * It's also not clear how such transfers are supposed to be 161 * represented as a stream of bytes...this is a limitation of 162 * the current SPI interface. 163 */ 164 if (bitlen % 8) { 165 /* Errors always terminate an ongoing transfer */ 166 flags |= SPI_XFER_END; 167 goto out; 168 } 169 170 len = bitlen / 8; 171 172 /* 173 * The controller can do automatic CS control, but it is 174 * somewhat quirky, and it doesn't really buy us much anyway 175 * in the context of U-Boot. 176 */ 177 if (flags & SPI_XFER_BEGIN) { 178 spi_cs_activate(slave); 179 /* 180 * sometimes the RDR is not empty when we get here, 181 * in theory that should not happen, but it DOES happen. 182 * Read it here to be on the safe side. 183 * That also clears the OVRES flag. Required if the 184 * following loop exits due to OVRES! 185 */ 186 spi_readl(as, RDR); 187 } 188 189 for (len_tx = 0, len_rx = 0; len_rx < len; ) { 190 status = spi_readl(as, SR); 191 192 if (status & ATMEL_SPI_SR_OVRES) 193 return -1; 194 195 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) { 196 if (txp) 197 value = *txp++; 198 else 199 value = 0; 200 spi_writel(as, TDR, value); 201 len_tx++; 202 } 203 if (status & ATMEL_SPI_SR_RDRF) { 204 value = spi_readl(as, RDR); 205 if (rxp) 206 *rxp++ = value; 207 len_rx++; 208 } 209 } 210 211 out: 212 if (flags & SPI_XFER_END) { 213 /* 214 * Wait until the transfer is completely done before 215 * we deactivate CS. 216 */ 217 do { 218 status = spi_readl(as, SR); 219 } while (!(status & ATMEL_SPI_SR_TXEMPTY)); 220 221 spi_cs_deactivate(slave); 222 } 223 224 return 0; 225 } 226 227 #else 228 229 #define MAX_CS_COUNT 4 230 231 struct atmel_spi_platdata { 232 struct at91_spi *regs; 233 }; 234 235 struct atmel_spi_priv { 236 unsigned int freq; /* Default frequency */ 237 unsigned int mode; 238 ulong bus_clk_rate; 239 #ifdef CONFIG_DM_GPIO 240 struct gpio_desc cs_gpios[MAX_CS_COUNT]; 241 #endif 242 }; 243 244 static int atmel_spi_claim_bus(struct udevice *dev) 245 { 246 struct udevice *bus = dev_get_parent(dev); 247 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 248 struct atmel_spi_priv *priv = dev_get_priv(bus); 249 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 250 struct at91_spi *reg_base = bus_plat->regs; 251 u32 cs = slave_plat->cs; 252 u32 freq = priv->freq; 253 u32 scbr, csrx, mode; 254 255 scbr = (priv->bus_clk_rate + freq - 1) / freq; 256 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) 257 return -EINVAL; 258 259 if (scbr < 1) 260 scbr = 1; 261 262 csrx = ATMEL_SPI_CSRx_SCBR(scbr); 263 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); 264 265 if (!(priv->mode & SPI_CPHA)) 266 csrx |= ATMEL_SPI_CSRx_NCPHA; 267 if (priv->mode & SPI_CPOL) 268 csrx |= ATMEL_SPI_CSRx_CPOL; 269 270 writel(csrx, ®_base->csr[cs]); 271 272 mode = ATMEL_SPI_MR_MSTR | 273 ATMEL_SPI_MR_MODFDIS | 274 ATMEL_SPI_MR_WDRBT | 275 ATMEL_SPI_MR_PCS(~(1 << cs)); 276 277 writel(mode, ®_base->mr); 278 279 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr); 280 281 return 0; 282 } 283 284 static int atmel_spi_release_bus(struct udevice *dev) 285 { 286 struct udevice *bus = dev_get_parent(dev); 287 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 288 289 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr); 290 291 return 0; 292 } 293 294 static void atmel_spi_cs_activate(struct udevice *dev) 295 { 296 #ifdef CONFIG_DM_GPIO 297 struct udevice *bus = dev_get_parent(dev); 298 struct atmel_spi_priv *priv = dev_get_priv(bus); 299 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 300 u32 cs = slave_plat->cs; 301 302 if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) 303 return; 304 305 dm_gpio_set_value(&priv->cs_gpios[cs], 0); 306 #endif 307 } 308 309 static void atmel_spi_cs_deactivate(struct udevice *dev) 310 { 311 #ifdef CONFIG_DM_GPIO 312 struct udevice *bus = dev_get_parent(dev); 313 struct atmel_spi_priv *priv = dev_get_priv(bus); 314 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 315 u32 cs = slave_plat->cs; 316 317 if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) 318 return; 319 320 dm_gpio_set_value(&priv->cs_gpios[cs], 1); 321 #endif 322 } 323 324 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen, 325 const void *dout, void *din, unsigned long flags) 326 { 327 struct udevice *bus = dev_get_parent(dev); 328 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 329 struct at91_spi *reg_base = bus_plat->regs; 330 331 u32 len_tx, len_rx, len; 332 u32 status; 333 const u8 *txp = dout; 334 u8 *rxp = din; 335 u8 value; 336 337 if (bitlen == 0) 338 goto out; 339 340 /* 341 * The controller can do non-multiple-of-8 bit 342 * transfers, but this driver currently doesn't support it. 343 * 344 * It's also not clear how such transfers are supposed to be 345 * represented as a stream of bytes...this is a limitation of 346 * the current SPI interface. 347 */ 348 if (bitlen % 8) { 349 /* Errors always terminate an ongoing transfer */ 350 flags |= SPI_XFER_END; 351 goto out; 352 } 353 354 len = bitlen / 8; 355 356 /* 357 * The controller can do automatic CS control, but it is 358 * somewhat quirky, and it doesn't really buy us much anyway 359 * in the context of U-Boot. 360 */ 361 if (flags & SPI_XFER_BEGIN) { 362 atmel_spi_cs_activate(dev); 363 364 /* 365 * sometimes the RDR is not empty when we get here, 366 * in theory that should not happen, but it DOES happen. 367 * Read it here to be on the safe side. 368 * That also clears the OVRES flag. Required if the 369 * following loop exits due to OVRES! 370 */ 371 readl(®_base->rdr); 372 } 373 374 for (len_tx = 0, len_rx = 0; len_rx < len; ) { 375 status = readl(®_base->sr); 376 377 if (status & ATMEL_SPI_SR_OVRES) 378 return -1; 379 380 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) { 381 if (txp) 382 value = *txp++; 383 else 384 value = 0; 385 writel(value, ®_base->tdr); 386 len_tx++; 387 } 388 389 if (status & ATMEL_SPI_SR_RDRF) { 390 value = readl(®_base->rdr); 391 if (rxp) 392 *rxp++ = value; 393 len_rx++; 394 } 395 } 396 397 out: 398 if (flags & SPI_XFER_END) { 399 /* 400 * Wait until the transfer is completely done before 401 * we deactivate CS. 402 */ 403 wait_for_bit_le32(®_base->sr, 404 ATMEL_SPI_SR_TXEMPTY, true, 1000, false); 405 406 atmel_spi_cs_deactivate(dev); 407 } 408 409 return 0; 410 } 411 412 static int atmel_spi_set_speed(struct udevice *bus, uint speed) 413 { 414 struct atmel_spi_priv *priv = dev_get_priv(bus); 415 416 priv->freq = speed; 417 418 return 0; 419 } 420 421 static int atmel_spi_set_mode(struct udevice *bus, uint mode) 422 { 423 struct atmel_spi_priv *priv = dev_get_priv(bus); 424 425 priv->mode = mode; 426 427 return 0; 428 } 429 430 static const struct dm_spi_ops atmel_spi_ops = { 431 .claim_bus = atmel_spi_claim_bus, 432 .release_bus = atmel_spi_release_bus, 433 .xfer = atmel_spi_xfer, 434 .set_speed = atmel_spi_set_speed, 435 .set_mode = atmel_spi_set_mode, 436 /* 437 * cs_info is not needed, since we require all chip selects to be 438 * in the device tree explicitly 439 */ 440 }; 441 442 static int atmel_spi_enable_clk(struct udevice *bus) 443 { 444 struct atmel_spi_priv *priv = dev_get_priv(bus); 445 struct clk clk; 446 ulong clk_rate; 447 int ret; 448 449 ret = clk_get_by_index(bus, 0, &clk); 450 if (ret) 451 return -EINVAL; 452 453 ret = clk_enable(&clk); 454 if (ret) 455 return ret; 456 457 clk_rate = clk_get_rate(&clk); 458 if (!clk_rate) 459 return -EINVAL; 460 461 priv->bus_clk_rate = clk_rate; 462 463 clk_free(&clk); 464 465 return 0; 466 } 467 468 static int atmel_spi_probe(struct udevice *bus) 469 { 470 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus); 471 int ret; 472 473 ret = atmel_spi_enable_clk(bus); 474 if (ret) 475 return ret; 476 477 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus); 478 479 #ifdef CONFIG_DM_GPIO 480 struct atmel_spi_priv *priv = dev_get_priv(bus); 481 int i; 482 483 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios, 484 ARRAY_SIZE(priv->cs_gpios), 0); 485 if (ret < 0) { 486 pr_err("Can't get %s gpios! Error: %d", bus->name, ret); 487 return ret; 488 } 489 490 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) { 491 if (!dm_gpio_is_valid(&priv->cs_gpios[i])) 492 continue; 493 494 dm_gpio_set_dir_flags(&priv->cs_gpios[i], 495 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 496 } 497 #endif 498 499 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr); 500 501 return 0; 502 } 503 504 static const struct udevice_id atmel_spi_ids[] = { 505 { .compatible = "atmel,at91rm9200-spi" }, 506 { } 507 }; 508 509 U_BOOT_DRIVER(atmel_spi) = { 510 .name = "atmel_spi", 511 .id = UCLASS_SPI, 512 .of_match = atmel_spi_ids, 513 .ops = &atmel_spi_ops, 514 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata), 515 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), 516 .probe = atmel_spi_probe, 517 }; 518 #endif 519