1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ASPEED AST2500 FMC/SPI Controller driver 4 * 5 * Copyright (c) 2015-2018, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <asm/io.h> 16 #include <linux/ioport.h> 17 18 #define ASPEED_SPI_MAX_CS 3 19 20 struct aspeed_spi_regs { 21 u32 conf; /* 0x00 CE Type Setting */ 22 u32 ctrl; /* 0x04 Control */ 23 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 24 u32 cmd_ctrl; /* 0x0c Command Control */ 25 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 26 u32 _reserved0[5]; /* .. */ 27 u32 segment_addr[ASPEED_SPI_MAX_CS]; 28 /* 0x30 .. 0x38 Segment Address */ 29 u32 _reserved1[17]; /* .. */ 30 u32 dma_ctrl; /* 0x80 DMA Control/Status */ 31 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 32 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 33 u32 dma_len; /* 0x8c DMA Length Register */ 34 u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 35 u32 timings; /* 0x94 Read Timing Compensation */ 36 37 /* not used */ 38 u32 soft_strap_status; /* 0x9c Software Strap Status */ 39 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 40 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 41 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 42 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 43 u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 44 }; 45 46 /* CE Type Setting Register */ 47 #define CONF_ENABLE_W2 BIT(18) 48 #define CONF_ENABLE_W1 BIT(17) 49 #define CONF_ENABLE_W0 BIT(16) 50 #define CONF_FLASH_TYPE2 4 51 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 52 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 53 #define CONF_FLASH_TYPE_NOR 0x0 54 #define CONF_FLASH_TYPE_SPI 0x2 55 56 /* CE Control Register */ 57 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 58 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 59 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 60 61 /* Interrupt Control and Status Register */ 62 #define INTR_CTRL_DMA_STATUS BIT(11) 63 #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 64 #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 65 #define INTR_CTRL_DMA_EN BIT(3) 66 #define INTR_CTRL_CMD_ABORT_EN BIT(2) 67 #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 68 69 /* CEx Control Register */ 70 #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 71 #define CE_CTRL_IO_DUAL_DATA BIT(29) 72 #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 73 #define CE_CTRL_IO_QUAD_DATA BIT(30) 74 #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 75 #define CE_CTRL_CMD_SHIFT 16 76 #define CE_CTRL_CMD_MASK 0xff 77 #define CE_CTRL_CMD(cmd) \ 78 (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 79 #define CE_CTRL_DUMMY_HIGH_SHIFT 14 80 #define CE_CTRL_DUMMY_HIGH_MASK 0x1 81 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 82 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 83 #define CE_CTRL_CLOCK_FREQ(div) \ 84 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 85 #define CE_G6_CTRL_CLOCK_FREQ(div) \ 86 ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20)) 87 #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 88 #define CE_CTRL_DUMMY_LOW_MASK 0x3 89 #define CE_CTRL_DUMMY(dummy) \ 90 (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 91 << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 92 (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 93 #define CE_CTRL_STOP_ACTIVE BIT(2) 94 #define CE_CTRL_MODE_MASK 0x3 95 #define CE_CTRL_READMODE 0x0 96 #define CE_CTRL_FREADMODE 0x1 97 #define CE_CTRL_WRITEMODE 0x2 98 #define CE_CTRL_USERMODE 0x3 99 100 /* 101 * The Segment Register uses a 8MB unit to encode the start address 102 * and the end address of the AHB window of a SPI flash device. 103 * Default segment addresses are : 104 * 105 * CE0 0x20000000 - 0x2fffffff 128MB 106 * CE1 0x28000000 - 0x29ffffff 32MB 107 * CE2 0x2a000000 - 0x2bffffff 32MB 108 * 109 * The full address space of the AHB window of the controller is 110 * covered and CE0 start address and CE2 end addresses are read-only. 111 */ 112 #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 113 #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 114 #define SEGMENT_ADDR_VALUE(start, end) \ 115 (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 116 117 #define G6_SEGMENT_ADDR_START(reg) (reg & 0xffff) 118 #define G6_SEGMENT_ADDR_END(reg) ((reg >> 16) & 0xffff) 119 #define G6_SEGMENT_ADDR_VALUE(start, end) \ 120 ((((start) >> 16) & 0xffff) | (((end) - 0x100000) & 0xfff00000)) 121 122 /* DMA Control/Status Register */ 123 #define DMA_CTRL_DELAY_SHIFT 8 124 #define DMA_CTRL_DELAY_MASK 0xf 125 #define DMA_CTRL_FREQ_SHIFT 4 126 #define DMA_CTRL_FREQ_MASK 0xf 127 #define TIMING_MASK(div, delay) \ 128 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 129 ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 130 #define DMA_CTRL_CALIB BIT(3) 131 #define DMA_CTRL_CKSUM BIT(2) 132 #define DMA_CTRL_WRITE BIT(1) 133 #define DMA_CTRL_ENABLE BIT(0) 134 135 /* 136 * 137 */ 138 struct aspeed_spi_flash { 139 u8 cs; 140 bool init; /* Initialized when the SPI bus is 141 * first claimed 142 */ 143 void __iomem *ahb_base; /* AHB Window for this device */ 144 u32 ahb_size; /* AHB Window segment size */ 145 u32 ce_ctrl_user; /* CE Control Register for USER mode */ 146 u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 147 u32 iomode; 148 149 struct spi_flash *spi; /* Associated SPI Flash device */ 150 }; 151 152 struct aspeed_spi_priv { 153 struct aspeed_spi_regs *regs; 154 void __iomem *ahb_base; /* AHB Window for all flash devices */ 155 int new_ver; 156 u32 ahb_size; /* AHB Window segments size */ 157 158 ulong hclk_rate; /* AHB clock rate */ 159 u32 max_hz; 160 u8 num_cs; 161 bool is_fmc; 162 163 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 164 u32 flash_count; 165 166 u8 cmd_buf[16]; /* SPI command in progress */ 167 size_t cmd_len; 168 }; 169 170 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 171 { 172 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 173 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 174 u8 cs = slave_plat->cs; 175 176 if (cs >= priv->flash_count) { 177 pr_err("invalid CS %u\n", cs); 178 return NULL; 179 } 180 181 return &priv->flashes[cs]; 182 } 183 184 static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 185 { 186 u32 hclk_rate = priv->hclk_rate; 187 /* HCLK/1 .. HCLK/16 */ 188 const u8 hclk_masks[] = { 189 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 190 }; 191 u8 base_div = 0; 192 // int done = 0; 193 u32 i, j; 194 u32 hclk_div_setting = 0; 195 196 //for ast2600 spi freq = hclk / (([27:24] * 16) + [11:8]) 197 for (j = 0; j < ARRAY_SIZE(hclk_masks); i++) { 198 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 199 if (max_hz >= (hclk_rate / ((i + 1) + (j * 16)))) { 200 base_div = j * 16; 201 // done = 1; 202 break; 203 } 204 } 205 // if (done) 206 // break; 207 if( j == 0) break; // todo check 208 } 209 210 debug("hclk=%d required=%d base_div is %d (mask %x, base_div %x) speed=%d\n", 211 hclk_rate, max_hz, i + 1, hclk_masks[i], base_div, hclk_rate / ((i + 1) + base_div)); 212 213 hclk_div_setting = ((j << 4) | hclk_masks[i]); 214 215 return hclk_div_setting; 216 217 } 218 219 static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 220 { 221 u32 hclk_rate = priv->hclk_rate; 222 /* HCLK/1 .. HCLK/16 */ 223 const u8 hclk_masks[] = { 224 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 225 }; 226 u32 i; 227 u32 hclk_div_setting = 0; 228 229 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 230 if (max_hz >= (hclk_rate / (i + 1))) 231 break; 232 } 233 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 234 hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 235 236 hclk_div_setting = hclk_masks[i]; 237 238 return hclk_div_setting; 239 } 240 241 /* 242 * Use some address/size under the first flash device CE0 243 */ 244 static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, 245 u8 delay) 246 { 247 u32 flash_addr = (u32)priv->ahb_base + 0x10000; 248 u32 flash_len = 0x200; 249 u32 dma_ctrl; 250 u32 checksum; 251 252 writel(flash_addr, &priv->regs->dma_flash_addr); 253 writel(flash_len, &priv->regs->dma_len); 254 255 /* 256 * When doing calibration, the SPI clock rate in the CE0 257 * Control Register and the data input delay cycles in the 258 * Read Timing Compensation Register are replaced by bit[11:4]. 259 */ 260 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 261 TIMING_MASK(div, delay); 262 writel(dma_ctrl, &priv->regs->dma_ctrl); 263 264 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 265 ; 266 267 writel(0x0, &priv->regs->intr_ctrl); 268 269 checksum = readl(&priv->regs->dma_checksum); 270 271 writel(0x0, &priv->regs->dma_ctrl); 272 273 return checksum; 274 } 275 276 static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, 277 u8 delay) 278 { 279 /* TODO(clg@kaod.org): the SPI controllers do not have the DMA 280 * registers. The algorithm is the same. 281 */ 282 if (!priv->is_fmc) { 283 pr_warn("No timing calibration support for SPI controllers"); 284 return 0xbadc0de; 285 } 286 287 return aspeed_spi_fmc_checksum(priv, div, delay); 288 } 289 290 #define TIMING_DELAY_DI_4NS BIT(3) 291 #define TIMING_DELAY_HCYCLE_MAX 5 292 293 static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) 294 { 295 /* HCLK/5 .. HCLK/1 */ 296 const u8 hclk_masks[] = { 13, 6, 14, 7, 15 }; 297 u32 timing_reg = 0; 298 u32 checksum, gold_checksum; 299 int i, hcycle; 300 301 debug("Read timing calibration :\n"); 302 303 /* Compute reference checksum at lowest freq HCLK/16 */ 304 gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); 305 306 /* 307 * Set CE0 Control Register to FAST READ command mode. The 308 * HCLK divisor will be set through the DMA Control Register. 309 */ 310 writel(CE_CTRL_CMD(0xb) | CE_CTRL_DUMMY(1) | CE_CTRL_FREADMODE, 311 &priv->regs->ce_ctrl[0]); 312 313 /* Increase HCLK freq */ 314 if (priv->new_ver) { 315 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 316 u32 hdiv = 5 - i; 317 u32 hshift = (hdiv - 1) << 2; 318 bool pass = false; 319 u8 delay; 320 321 if (priv->hclk_rate / hdiv > priv->max_hz) { 322 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 323 continue; 324 } 325 326 /* Increase HCLK cycles until read succeeds */ 327 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 328 /* Try first with a 4ns DI delay */ 329 delay = TIMING_DELAY_DI_4NS | hcycle; 330 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 331 delay); 332 pass = (checksum == gold_checksum); 333 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 334 hdiv, hcycle, pass ? "PASS" : "FAIL"); 335 336 /* Try again with more HCLK cycles */ 337 if (!pass) 338 continue; 339 340 /* Try without the 4ns DI delay */ 341 delay = hcycle; 342 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 343 delay); 344 pass = (checksum == gold_checksum); 345 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 346 hdiv, hcycle, pass ? "PASS" : "FAIL"); 347 348 /* All good for this freq */ 349 if (pass) 350 break; 351 } 352 353 if (pass) { 354 timing_reg &= ~(0xfu << hshift); 355 timing_reg |= delay << hshift; 356 } 357 } 358 } else { 359 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 360 u32 hdiv = 5 - i; 361 u32 hshift = (hdiv - 1) << 2; 362 bool pass = false; 363 u8 delay; 364 365 if (priv->hclk_rate / hdiv > priv->max_hz) { 366 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 367 continue; 368 } 369 370 /* Increase HCLK cycles until read succeeds */ 371 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 372 /* Try first with a 4ns DI delay */ 373 delay = TIMING_DELAY_DI_4NS | hcycle; 374 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 375 delay); 376 pass = (checksum == gold_checksum); 377 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 378 hdiv, hcycle, pass ? "PASS" : "FAIL"); 379 380 /* Try again with more HCLK cycles */ 381 if (!pass) 382 continue; 383 384 /* Try without the 4ns DI delay */ 385 delay = hcycle; 386 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 387 delay); 388 pass = (checksum == gold_checksum); 389 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 390 hdiv, hcycle, pass ? "PASS" : "FAIL"); 391 392 /* All good for this freq */ 393 if (pass) 394 break; 395 } 396 397 if (pass) { 398 timing_reg &= ~(0xfu << hshift); 399 timing_reg |= delay << hshift; 400 } 401 } 402 } 403 debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 404 writel(timing_reg, &priv->regs->timings); 405 406 /* Reset CE0 Control Register */ 407 writel(0x0, &priv->regs->ce_ctrl[0]); 408 409 return 0; 410 } 411 412 static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 413 { 414 int cs, ret; 415 416 /* 417 * Enable write on all flash devices as USER command mode 418 * requires it. 419 */ 420 setbits_le32(&priv->regs->conf, 421 CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 422 423 /* 424 * Set the Read Timing Compensation Register. This setting 425 * applies to all devices. 426 */ 427 ret = aspeed_spi_timing_calibration(priv); 428 if (ret) 429 return ret; 430 431 /* 432 * Set safe default settings for each device. These will be 433 * tuned after the SPI flash devices are probed. 434 */ 435 if (priv->new_ver) { 436 for (cs = 0; cs < priv->flash_count; cs++) { 437 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 438 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 439 u32 addr_config = 0; 440 switch(cs) { 441 case 0: 442 flash->ahb_base = cs ? (void *)G6_SEGMENT_ADDR_START(seg_addr) : 443 priv->ahb_base; 444 debug("cs0 mem-map : %x \n", (u32)flash->ahb_base); 445 break; 446 case 1: 447 flash->ahb_base = priv->flashes[0].ahb_base + 0x8000000; //cs0 + 128Mb 448 debug("cs1 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x8000000); 449 addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x8000000); //add 128Mb 450 writel(addr_config, &priv->regs->segment_addr[cs]); 451 break; 452 case 2: 453 flash->ahb_base = priv->flashes[0].ahb_base + 0xc000000; //cs0 + 196Mb 454 printf("cs2 mem-map : %x \n", (u32)flash->ahb_base); 455 break; 456 } 457 flash->cs = cs; 458 flash->ce_ctrl_user = CE_CTRL_USERMODE; 459 flash->ce_ctrl_fread = CE_CTRL_READMODE; 460 } 461 } else { 462 for (cs = 0; cs < priv->flash_count; cs++) { 463 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 464 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 465 /* 466 * The start address of the AHB window of CE0 is 467 * read-only and is the same as the address of the 468 * overall AHB window of the controller for all flash 469 * devices. 470 */ 471 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 472 priv->ahb_base; 473 474 flash->cs = cs; 475 flash->ce_ctrl_user = CE_CTRL_USERMODE; 476 flash->ce_ctrl_fread = CE_CTRL_READMODE; 477 } 478 } 479 return 0; 480 } 481 482 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 483 size_t len) 484 { 485 size_t offset = 0; 486 487 if (!((uintptr_t)buf % 4)) { 488 readsl(ahb_base, buf, len >> 2); 489 offset = len & ~0x3; 490 len -= offset; 491 } 492 readsb(ahb_base, (u8 *)buf + offset, len); 493 494 return 0; 495 } 496 497 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 498 size_t len) 499 { 500 size_t offset = 0; 501 502 if (!((uintptr_t)buf % 4)) { 503 writesl(ahb_base, buf, len >> 2); 504 offset = len & ~0x3; 505 len -= offset; 506 } 507 writesb(ahb_base, (u8 *)buf + offset, len); 508 509 return 0; 510 } 511 512 static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 513 struct aspeed_spi_flash *flash) 514 { 515 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 516 517 /* Deselect CS and set USER command mode */ 518 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 519 520 /* Select CS */ 521 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 522 } 523 524 static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 525 struct aspeed_spi_flash *flash) 526 { 527 /* Deselect CS first */ 528 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 529 530 /* Restore default command mode */ 531 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 532 } 533 534 static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 535 struct aspeed_spi_flash *flash, 536 u8 opcode, u8 *read_buf, int len) 537 { 538 aspeed_spi_start_user(priv, flash); 539 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 540 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 541 aspeed_spi_stop_user(priv, flash); 542 543 return 0; 544 } 545 546 static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 547 struct aspeed_spi_flash *flash, 548 u8 opcode, const u8 *write_buf, int len) 549 { 550 aspeed_spi_start_user(priv, flash); 551 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 552 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 553 aspeed_spi_stop_user(priv, flash); 554 555 switch(opcode) { 556 case SPINOR_OP_EN4B: 557 writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); 558 break; 559 case SPINOR_OP_EX4B: 560 writel(readl(&priv->regs->ctrl) & ~BIT(flash->cs), &priv->regs->ctrl); 561 break; 562 } 563 return 0; 564 } 565 566 static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 567 struct aspeed_spi_flash *flash, 568 const u8 *cmdbuf, unsigned int cmdlen) 569 { 570 int i; 571 u8 byte0 = 0x0; 572 u8 addrlen = cmdlen - 1; 573 574 /* First, send the opcode */ 575 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 576 577 /* 578 * The controller is configured for 4BYTE address mode. Fix 579 * the address width and send an extra byte if the SPI Flash 580 * layer uses 3 bytes addresses. 581 */ 582 if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) 583 aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); 584 585 /* Then the address */ 586 for (i = 1 ; i < cmdlen; i++) 587 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 588 } 589 590 static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 591 struct aspeed_spi_flash *flash, 592 unsigned int cmdlen, const u8 *cmdbuf, 593 unsigned int len, u8 *read_buf) 594 { 595 u8 dummy = 0xff; 596 int i; 597 598 aspeed_spi_start_user(priv, flash); 599 600 /* cmd buffer = cmd + addr + dummies */ 601 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 602 cmdlen - (flash->spi->read_dummy/8)); 603 604 for (i = 0 ; i < (flash->spi->read_dummy/8); i++) 605 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 606 607 if (flash->iomode) { 608 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 609 CE_CTRL_IO_MODE_MASK); 610 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->iomode); 611 } 612 613 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 614 aspeed_spi_stop_user(priv, flash); 615 616 return 0; 617 } 618 619 static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 620 struct aspeed_spi_flash *flash, 621 unsigned int cmdlen, const u8 *cmdbuf, 622 unsigned int len, const u8 *write_buf) 623 { 624 aspeed_spi_start_user(priv, flash); 625 626 /* cmd buffer = cmd + addr */ 627 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); 628 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 629 630 aspeed_spi_stop_user(priv, flash); 631 632 return 0; 633 } 634 635 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 636 const u8 *cmdbuf, unsigned int cmdlen) 637 { 638 u8 addrlen = cmdlen - 1; 639 u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 640 641 /* 642 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 643 * change one day 644 */ 645 if (addrlen == 4) 646 addr = (addr << 8) | cmdbuf[4]; 647 648 return addr; 649 } 650 651 /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 652 static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 653 struct aspeed_spi_flash *flash, 654 unsigned int cmdlen, const u8 *cmdbuf, 655 unsigned int len, u8 *read_buf) 656 { 657 /* cmd buffer = cmd + addr + dummies */ 658 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 659 cmdlen - (flash->spi->read_dummy/8)); 660 661 /* 662 * Switch to USER command mode if the AHB window configured 663 * for the device is too small for the read operation 664 */ 665 if (offset + len >= flash->ahb_size) { 666 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 667 len, read_buf); 668 } 669 670 memcpy_fromio(read_buf, flash->ahb_base + offset, len); 671 672 return 0; 673 } 674 675 static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 676 const void *dout, void *din, unsigned long flags) 677 { 678 struct udevice *bus = dev->parent; 679 struct aspeed_spi_priv *priv = dev_get_priv(bus); 680 struct aspeed_spi_flash *flash; 681 u8 *cmd_buf = priv->cmd_buf; 682 size_t data_bytes; 683 int err = 0; 684 685 flash = aspeed_spi_get_flash(dev); 686 if (!flash) 687 return -ENXIO; 688 689 if (flags & SPI_XFER_BEGIN) { 690 /* save command in progress */ 691 priv->cmd_len = bitlen / 8; 692 memcpy(cmd_buf, dout, priv->cmd_len); 693 } 694 695 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 696 /* if start and end bit are set, the data bytes is 0. */ 697 data_bytes = 0; 698 } else { 699 data_bytes = bitlen / 8; 700 } 701 702 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 703 din ? "read" : "write", priv->cmd_len, data_bytes); 704 705 if ((flags & SPI_XFER_END) || flags == 0) { 706 if (priv->cmd_len == 0) { 707 pr_err("No command is progress !\n"); 708 return -1; 709 } 710 711 if (din && data_bytes) { 712 if (priv->cmd_len == 1) 713 err = aspeed_spi_read_reg(priv, flash, 714 cmd_buf[0], 715 din, data_bytes); 716 else 717 err = aspeed_spi_read(priv, flash, 718 priv->cmd_len, 719 cmd_buf, data_bytes, 720 din); 721 } else if (dout) { 722 if (priv->cmd_len == 1) 723 err = aspeed_spi_write_reg(priv, flash, 724 cmd_buf[0], 725 dout, data_bytes); 726 else 727 err = aspeed_spi_write_user(priv, flash, 728 priv->cmd_len, 729 cmd_buf, data_bytes, 730 dout); 731 } 732 733 if (flags & SPI_XFER_END) { 734 /* clear command */ 735 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 736 priv->cmd_len = 0; 737 } 738 } 739 740 return err; 741 } 742 743 static int aspeed_spi_child_pre_probe(struct udevice *dev) 744 { 745 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 746 747 debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 748 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 749 750 if (!aspeed_spi_get_flash(dev)) 751 return -ENXIO; 752 753 return 0; 754 } 755 756 /* 757 * It is possible to automatically define a contiguous address space 758 * on top of all CEs in the AHB window of the controller but it would 759 * require much more work. Let's start with a simple mapping scheme 760 * which should work fine for a single flash device. 761 * 762 * More complex schemes should probably be defined with the device 763 * tree. 764 */ 765 static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 766 struct aspeed_spi_flash *flash) 767 { 768 u32 seg_addr; 769 770 /* could be configured through the device tree */ 771 flash->ahb_size = flash->spi->size; 772 773 if (priv->new_ver) { 774 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 775 (u32)flash->ahb_base + flash->ahb_size); 776 } else { 777 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 778 (u32)flash->ahb_base + flash->ahb_size); 779 } 780 writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 781 782 return 0; 783 } 784 785 static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 786 struct aspeed_spi_flash *flash, 787 struct udevice *dev) 788 { 789 struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 790 struct spi_slave *slave = dev_get_parent_priv(dev); 791 u32 read_hclk; 792 793 /* 794 * The SPI flash device slave should not change, so initialize 795 * it only once. 796 */ 797 if (flash->init) 798 return 0; 799 800 /* 801 * The flash device has not been probed yet. Initial transfers 802 * to read the JEDEC of the device will use the initial 803 * default settings of the registers. 804 */ 805 if (!spi_flash->name) 806 return 0; 807 808 debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " 809 "cmds [ erase:%x read=%x write:%x ] dummy:%d\n", 810 flash->cs, 811 spi_flash->name, spi_flash->flags, spi_flash->size, 812 spi_flash->page_size, spi_flash->sector_size, 813 spi_flash->erase_size, spi_flash->erase_opcode, 814 spi_flash->read_opcode, spi_flash->program_opcode, 815 spi_flash->read_dummy); 816 817 flash->spi = spi_flash; 818 819 flash->ce_ctrl_user = CE_CTRL_USERMODE; 820 821 if(priv->new_ver) 822 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 823 else 824 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 825 826 if (slave->mode & (SPI_RX_DUAL | SPI_TX_DUAL)) { 827 debug("CS%u: setting dual data mode\n", flash->cs); 828 flash->iomode = CE_CTRL_IO_DUAL_DATA; 829 flash->spi->read_opcode = SPINOR_OP_READ_1_1_2; 830 } else if (slave->mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 831 flash->iomode = CE_CTRL_IO_QUAD_DATA; 832 flash->spi->read_opcode = SPINOR_OP_READ_1_4_4; 833 } else { 834 debug("normal read \n"); 835 } 836 837 if(priv->new_ver) { 838 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 839 flash->iomode | 840 CE_CTRL_CMD(flash->spi->read_opcode) | 841 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 842 CE_CTRL_FREADMODE; 843 } else { 844 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 845 flash->iomode | 846 CE_CTRL_CMD(flash->spi->read_opcode) | 847 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 848 CE_CTRL_FREADMODE; 849 } 850 851 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 852 flash->ce_ctrl_user, flash->ce_ctrl_fread); 853 854 /* Set the CE Control Register default (FAST READ) */ 855 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 856 857 /* Set Address Segment Register for direct AHB accesses */ 858 aspeed_spi_flash_set_segment(priv, flash); 859 860 /* All done */ 861 flash->init = true; 862 863 return 0; 864 } 865 866 static int aspeed_spi_claim_bus(struct udevice *dev) 867 { 868 struct udevice *bus = dev->parent; 869 struct aspeed_spi_priv *priv = dev_get_priv(bus); 870 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 871 struct aspeed_spi_flash *flash; 872 873 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 874 875 flash = aspeed_spi_get_flash(dev); 876 if (!flash) 877 return -ENODEV; 878 879 return aspeed_spi_flash_init(priv, flash, dev); 880 } 881 882 static int aspeed_spi_release_bus(struct udevice *dev) 883 { 884 struct udevice *bus = dev->parent; 885 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 886 887 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 888 889 if (!aspeed_spi_get_flash(dev)) 890 return -ENODEV; 891 892 return 0; 893 } 894 895 static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 896 { 897 debug("%s: setting mode to %x\n", bus->name, mode); 898 899 if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 900 pr_err("%s invalid QUAD IO mode\n", bus->name); 901 return -EINVAL; 902 } 903 904 /* The CE Control Register is set in claim_bus() */ 905 return 0; 906 } 907 908 static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 909 { 910 debug("%s: setting speed to %u\n", bus->name, hz); 911 912 /* The CE Control Register is set in claim_bus() */ 913 return 0; 914 } 915 916 static int aspeed_spi_count_flash_devices(struct udevice *bus) 917 { 918 ofnode node; 919 int count = 0; 920 921 dev_for_each_subnode(node, bus) { 922 if (ofnode_is_available(node) && 923 ofnode_device_is_compatible(node, "spi-flash")) 924 count++; 925 } 926 927 return count; 928 } 929 930 static int aspeed_spi_bind(struct udevice *bus) 931 { 932 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 933 bus->seq); 934 935 return 0; 936 } 937 938 static int aspeed_spi_probe(struct udevice *bus) 939 { 940 struct resource res_regs, res_ahb; 941 struct aspeed_spi_priv *priv = dev_get_priv(bus); 942 struct clk hclk; 943 int ret; 944 945 ret = dev_read_resource(bus, 0, &res_regs); 946 if (ret < 0) 947 return ret; 948 949 priv->regs = (void __iomem *)res_regs.start; 950 951 ret = dev_read_resource(bus, 1, &res_ahb); 952 if (ret < 0) 953 return ret; 954 955 priv->ahb_base = (void __iomem *)res_ahb.start; 956 priv->ahb_size = res_ahb.end - res_ahb.start; 957 958 ret = clk_get_by_index(bus, 0, &hclk); 959 if (ret < 0) { 960 pr_err("%s could not get clock: %d\n", bus->name, ret); 961 return ret; 962 } 963 964 priv->hclk_rate = clk_get_rate(&hclk); 965 clk_free(&hclk); 966 967 priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 968 100000000); 969 970 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 971 972 priv->flash_count = aspeed_spi_count_flash_devices(bus); 973 if (priv->flash_count > priv->num_cs) { 974 pr_err("%s has too many flash devices: %d\n", bus->name, 975 priv->flash_count); 976 return -EINVAL; 977 } 978 979 if (!priv->flash_count) { 980 pr_err("%s has no flash devices ?!\n", bus->name); 981 return -ENODEV; 982 } 983 984 if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 985 device_is_compatible(bus, "aspeed,ast2600-fmc")) { 986 priv->new_ver = 1; 987 } 988 989 /* 990 * There are some slight differences between the FMC and the 991 * SPI controllers 992 */ 993 priv->is_fmc = dev_get_driver_data(bus); 994 995 ret = aspeed_spi_controller_init(priv); 996 if (ret) 997 return ret; 998 999 debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", 1000 bus->name, priv->regs, priv->ahb_base, priv->max_hz, 1001 priv->flash_count, bus->seq); 1002 1003 return 0; 1004 } 1005 1006 static const struct dm_spi_ops aspeed_spi_ops = { 1007 .claim_bus = aspeed_spi_claim_bus, 1008 .release_bus = aspeed_spi_release_bus, 1009 .set_mode = aspeed_spi_set_mode, 1010 .set_speed = aspeed_spi_set_speed, 1011 .xfer = aspeed_spi_xfer, 1012 }; 1013 1014 static const struct udevice_id aspeed_spi_ids[] = { 1015 { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1016 { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1017 { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1018 { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1019 { } 1020 }; 1021 1022 U_BOOT_DRIVER(aspeed_spi) = { 1023 .name = "aspeed_spi", 1024 .id = UCLASS_SPI, 1025 .of_match = aspeed_spi_ids, 1026 .ops = &aspeed_spi_ops, 1027 .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1028 .child_pre_probe = aspeed_spi_child_pre_probe, 1029 .bind = aspeed_spi_bind, 1030 .probe = aspeed_spi_probe, 1031 }; 1032