1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ASPEED AST2500 FMC/SPI Controller driver 4 * 5 * Copyright (c) 2015-2018, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <asm/io.h> 16 #include <linux/ioport.h> 17 18 #define ASPEED_SPI_MAX_CS 3 19 #define FLASH_CALIBRATION_LEN 0x400 20 21 struct aspeed_spi_regs { 22 u32 conf; /* 0x00 CE Type Setting */ 23 u32 ctrl; /* 0x04 Control */ 24 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 25 u32 cmd_ctrl; /* 0x0c Command Control */ 26 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 27 u32 _reserved0[5]; /* .. */ 28 u32 segment_addr[ASPEED_SPI_MAX_CS]; 29 /* 0x30 .. 0x38 Segment Address */ 30 u32 _reserved1[5]; /* .. */ 31 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ 32 u32 _reserved2[11]; /* .. */ 33 u32 dma_ctrl; /* 0x80 DMA Control/Status */ 34 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 35 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 36 u32 dma_len; /* 0x8c DMA Length Register */ 37 u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 38 u32 timings; /* 0x94 Read Timing Compensation */ 39 40 /* not used */ 41 u32 soft_strap_status; /* 0x9c Software Strap Status */ 42 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 43 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 44 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 45 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 46 u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 47 }; 48 49 /* CE Type Setting Register */ 50 #define CONF_ENABLE_W2 BIT(18) 51 #define CONF_ENABLE_W1 BIT(17) 52 #define CONF_ENABLE_W0 BIT(16) 53 #define CONF_FLASH_TYPE2 4 54 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 55 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 56 #define CONF_FLASH_TYPE_NOR 0x0 57 #define CONF_FLASH_TYPE_SPI 0x2 58 59 /* CE Control Register */ 60 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 61 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 62 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 63 64 /* Interrupt Control and Status Register */ 65 #define INTR_CTRL_DMA_STATUS BIT(11) 66 #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 67 #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 68 #define INTR_CTRL_DMA_EN BIT(3) 69 #define INTR_CTRL_CMD_ABORT_EN BIT(2) 70 #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 71 72 /* CEx Control Register */ 73 #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 74 #define CE_CTRL_IO_QPI_DATA BIT(31) 75 #define CE_CTRL_IO_DUAL_DATA BIT(29) 76 #define CE_CTRL_IO_SINGLE 0 77 #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 78 #define CE_CTRL_IO_QUAD_DATA BIT(30) 79 #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 80 #define CE_CTRL_CMD_SHIFT 16 81 #define CE_CTRL_CMD_MASK 0xff 82 #define CE_CTRL_CMD(cmd) \ 83 (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 84 #define CE_CTRL_DUMMY_HIGH_SHIFT 14 85 #define CE_CTRL_DUMMY_HIGH_MASK 0x1 86 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 87 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 88 #define CE_CTRL_CLOCK_FREQ(div) \ 89 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 90 #define CE_G6_CTRL_CLOCK_FREQ(div) \ 91 ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20)) 92 #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 93 #define CE_CTRL_DUMMY_LOW_MASK 0x3 94 #define CE_CTRL_DUMMY(dummy) \ 95 (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 96 << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 97 (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 98 #define CE_CTRL_STOP_ACTIVE BIT(2) 99 #define CE_CTRL_MODE_MASK 0x3 100 #define CE_CTRL_READMODE 0x0 101 #define CE_CTRL_FREADMODE 0x1 102 #define CE_CTRL_WRITEMODE 0x2 103 #define CE_CTRL_USERMODE 0x3 104 105 #define SPI_READ_FROM_FLASH 0x00000001 106 #define SPI_WRITE_TO_FLASH 0x00000002 107 108 /* Auto Soft-Reset Command Control */ 109 #define SOFT_RST_CMD_EN GENMASK(1, 0) 110 111 /* 112 * The Segment Register uses a 8MB unit to encode the start address 113 * and the end address of the AHB window of a SPI flash device. 114 * Default segment addresses are : 115 * 116 * CE0 0x20000000 - 0x2fffffff 128MB 117 * CE1 0x28000000 - 0x29ffffff 32MB 118 * CE2 0x2a000000 - 0x2bffffff 32MB 119 * 120 * The full address space of the AHB window of the controller is 121 * covered and CE0 start address and CE2 end addresses are read-only. 122 */ 123 #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 124 #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 125 #define SEGMENT_ADDR_VALUE(start, end) \ 126 (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 127 128 #define G6_SEGMENT_ADDR_START(reg) (reg & 0xffff) 129 #define G6_SEGMENT_ADDR_END(reg) ((reg >> 16) & 0xffff) 130 #define G6_SEGMENT_ADDR_VALUE(start, end) \ 131 ((((start) >> 16) & 0xffff) | (((end) - 0x100000) & 0xffff0000)) 132 133 /* DMA Control/Status Register */ 134 #define DMA_CTRL_DELAY_SHIFT 8 135 #define DMA_CTRL_DELAY_MASK 0xf 136 #define G6_DMA_CTRL_DELAY_MASK 0xff 137 #define DMA_CTRL_FREQ_SHIFT 4 138 #define G6_DMA_CTRL_FREQ_SHIFT 16 139 140 #define DMA_CTRL_FREQ_MASK 0xf 141 #define TIMING_MASK(div, delay) \ 142 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 143 ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 144 #define G6_TIMING_MASK(div, delay) \ 145 (((delay & G6_DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 146 ((div & DMA_CTRL_FREQ_MASK) << G6_DMA_CTRL_FREQ_SHIFT)) 147 #define DMA_CTRL_CALIB BIT(3) 148 #define DMA_CTRL_CKSUM BIT(2) 149 #define DMA_CTRL_WRITE BIT(1) 150 #define DMA_CTRL_ENABLE BIT(0) 151 152 /* for ast2600 setting */ 153 #define SPI_3B_AUTO_CLR_REG 0x1e6e2510 154 #define SPI_3B_AUTO_CLR BIT(9) 155 156 157 /* 158 * flash related info 159 */ 160 struct aspeed_spi_flash { 161 u8 cs; 162 bool init; /* Initialized when the SPI bus is 163 * first claimed 164 */ 165 void __iomem *ahb_base; /* AHB Window for this device */ 166 u32 ahb_size; /* AHB Window segment size */ 167 u32 ce_ctrl_user; /* CE Control Register for USER mode */ 168 u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 169 u32 read_iomode; 170 u32 write_iomode; 171 172 struct spi_flash *spi; /* Associated SPI Flash device */ 173 }; 174 175 struct aspeed_spi_priv { 176 struct aspeed_spi_regs *regs; 177 void __iomem *ahb_base; /* AHB Window for all flash devices */ 178 int new_ver; 179 u32 ahb_size; /* AHB Window segments size */ 180 181 ulong hclk_rate; /* AHB clock rate */ 182 u32 max_hz; 183 u8 num_cs; 184 bool is_fmc; 185 186 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 187 u32 flash_count; 188 189 u8 cmd_buf[16]; /* SPI command in progress */ 190 size_t cmd_len; 191 }; 192 193 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 194 { 195 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 196 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 197 u8 cs = slave_plat->cs; 198 199 if (cs >= priv->flash_count) { 200 pr_err("invalid CS %u\n", cs); 201 return NULL; 202 } 203 204 return &priv->flashes[cs]; 205 } 206 207 static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 208 { 209 u32 hclk_rate = priv->hclk_rate; 210 /* HCLK/1 .. HCLK/16 */ 211 const u8 hclk_masks[] = { 212 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 213 }; 214 u8 base_div = 0; 215 int done = 0; 216 u32 i, j = 0; 217 u32 hclk_div_setting = 0; 218 219 for (j = 0; j < 0xf; i++) { 220 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 221 base_div = j * 16; 222 if (max_hz >= (hclk_rate / ((i + 1) + base_div))) { 223 224 done = 1; 225 break; 226 } 227 } 228 if (done) 229 break; 230 } 231 232 debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n", 233 hclk_rate, max_hz, j, i + 1, hclk_masks[i], hclk_rate / (i + 1 + base_div)); 234 235 hclk_div_setting = ((j << 4) | hclk_masks[i]); 236 237 return hclk_div_setting; 238 239 } 240 241 static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 242 { 243 u32 hclk_rate = priv->hclk_rate; 244 /* HCLK/1 .. HCLK/16 */ 245 const u8 hclk_masks[] = { 246 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 247 }; 248 u32 i; 249 u32 hclk_div_setting = 0; 250 251 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 252 if (max_hz >= (hclk_rate / (i + 1))) 253 break; 254 } 255 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 256 hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 257 258 hclk_div_setting = hclk_masks[i]; 259 260 return hclk_div_setting; 261 } 262 263 /* 264 * Use some address/size under the first flash device CE0 265 */ 266 static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, 267 u8 delay) 268 { 269 u32 flash_addr = (u32)priv->ahb_base + 0x10000; 270 u32 flash_len = FLASH_CALIBRATION_LEN; 271 u32 dma_ctrl; 272 u32 checksum; 273 274 writel(flash_addr, &priv->regs->dma_flash_addr); 275 writel(flash_len, &priv->regs->dma_len); 276 277 /* 278 * When doing calibration, the SPI clock rate in the CE0 279 * Control Register and the data input delay cycles in the 280 * Read Timing Compensation Register are replaced by bit[11:4]. 281 */ 282 if(priv->new_ver) 283 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 284 G6_TIMING_MASK(div, delay); 285 else 286 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 287 TIMING_MASK(div, delay); 288 writel(dma_ctrl, &priv->regs->dma_ctrl); 289 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 290 ; 291 292 writel(0x0, &priv->regs->intr_ctrl); 293 294 checksum = readl(&priv->regs->dma_checksum); 295 296 writel(0x0, &priv->regs->dma_ctrl); 297 return checksum; 298 } 299 300 static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, 301 u8 delay) 302 { 303 /* TODO(clg@kaod.org): the SPI controllers do not have the DMA 304 * registers. The algorithm is the same. 305 */ 306 if (!priv->is_fmc) { 307 pr_warn("No timing calibration support for SPI controllers"); 308 return 0xbadc0de; 309 } 310 311 return aspeed_spi_fmc_checksum(priv, div, delay); 312 } 313 314 #define TIMING_DELAY_DI_4NS BIT(3) 315 #define TIMING_DELAY_HCYCLE_MAX 5 316 317 static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) 318 { 319 /* HCLK/5 .. HCLK/1 */ 320 const u8 hclk_masks[] = {13, 6, 14, 7, 15}; 321 u32 timing_reg; 322 u32 checksum, gold_checksum; 323 int i, hcycle, delay_ns; 324 325 /* Use the ctrl setting in aspeed_spi_flash_init() to 326 * implement calibration process. 327 */ 328 timing_reg = readl(&priv->regs->timings); 329 if (timing_reg != 0) 330 return 0; 331 332 debug("Read timing calibration :\n"); 333 334 /* Compute reference checksum at lowest freq HCLK/16 */ 335 gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); 336 337 /* Increase HCLK freq */ 338 if (priv->new_ver) { 339 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 340 u32 hdiv = 5 - i; 341 u32 hshift = (hdiv - 2) * 8; 342 bool pass = false; 343 u8 delay; 344 u16 first_delay = 0; 345 u16 end_delay = 0; 346 u32 cal_tmp; 347 u32 max_window_sz = 0; 348 u32 cur_window_sz = 0; 349 u32 tmp_delay; 350 351 debug("hdiv %d, hshift %d\n", hdiv, hshift); 352 if (priv->hclk_rate / hdiv > priv->max_hz) { 353 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 354 continue; 355 } 356 357 /* Try without the 4ns DI delay */ 358 hcycle = delay = 0; 359 debug("** Dealy Disable **\n"); 360 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], delay); 361 pass = (checksum == gold_checksum); 362 debug("HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 363 hdiv, hcycle, pass ? "PASS" : "FAIL"); 364 365 /* All good for this freq */ 366 if (pass) 367 goto next_div; 368 369 /* Try each hcycle delay */ 370 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 371 /* Increase DI delay by the step of 0.5ns */ 372 debug("** Delay Enable : hcycle %x ** \n", hcycle); 373 for (delay_ns = 0; delay_ns < 0xf; delay_ns++) { 374 tmp_delay = TIMING_DELAY_DI_4NS | hcycle | (delay_ns << 4); 375 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 376 tmp_delay); 377 pass = (checksum == gold_checksum); 378 debug("HCLK/%d, DI delay, %d HCLK cycle, %d delay_ns : %s\n", 379 hdiv, hcycle, delay_ns, pass ? "PASS" : "FAIL"); 380 381 if (!pass) { 382 if (!first_delay) 383 continue; 384 else { 385 end_delay = (hcycle << 4) | (delay_ns); 386 end_delay = end_delay - 1; 387 /* Larger window size is found */ 388 if (cur_window_sz > max_window_sz) { 389 max_window_sz = cur_window_sz; 390 cal_tmp = (first_delay + end_delay) / 2; 391 delay = TIMING_DELAY_DI_4NS | 392 ((cal_tmp & 0xf) << 4) | 393 (cal_tmp >> 4); 394 } 395 debug("find end_delay %x %d %d\n", end_delay, 396 hcycle, delay_ns); 397 398 first_delay = 0; 399 end_delay = 0; 400 cur_window_sz = 0; 401 402 break; 403 } 404 } else { 405 if (!first_delay) { 406 first_delay = (hcycle << 4) | delay_ns; 407 debug("find first_delay %x %d %d\n", first_delay, hcycle, delay_ns); 408 } 409 /* Record current pass window size */ 410 cur_window_sz++; 411 } 412 } 413 } 414 415 if (pass) { 416 if (cur_window_sz > max_window_sz) { 417 max_window_sz = cur_window_sz; 418 end_delay = ((hcycle - 1) << 4) | (delay_ns - 1); 419 cal_tmp = (first_delay + end_delay) / 2; 420 delay = TIMING_DELAY_DI_4NS | 421 ((cal_tmp & 0xf) << 4) | 422 (cal_tmp >> 4); 423 } 424 } 425 next_div: 426 timing_reg &= ~(0xfu << hshift); 427 timing_reg |= delay << hshift; 428 debug("timing_reg %x, delay %x, hshift bit %d\n",timing_reg, delay, hshift); 429 } 430 } else { 431 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 432 u32 hdiv = 5 - i; 433 u32 hshift = (hdiv - 1) << 2; 434 bool pass = false; 435 u8 delay; 436 437 if (priv->hclk_rate / hdiv > priv->max_hz) { 438 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 439 continue; 440 } 441 442 /* Increase HCLK cycles until read succeeds */ 443 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 444 /* Try first with a 4ns DI delay */ 445 delay = TIMING_DELAY_DI_4NS | hcycle; 446 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 447 delay); 448 pass = (checksum == gold_checksum); 449 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 450 hdiv, hcycle, pass ? "PASS" : "FAIL"); 451 452 /* Try again with more HCLK cycles */ 453 if (!pass) 454 continue; 455 456 /* Try without the 4ns DI delay */ 457 delay = hcycle; 458 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 459 delay); 460 pass = (checksum == gold_checksum); 461 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 462 hdiv, hcycle, pass ? "PASS" : "FAIL"); 463 464 /* All good for this freq */ 465 if (pass) 466 break; 467 } 468 469 if (pass) { 470 timing_reg &= ~(0xfu << hshift); 471 timing_reg |= delay << hshift; 472 } 473 } 474 } 475 476 debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 477 writel(timing_reg, &priv->regs->timings); 478 479 return 0; 480 } 481 482 static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 483 { 484 int cs; 485 486 /* 487 * Enable write on all flash devices as USER command mode 488 * requires it. 489 */ 490 setbits_le32(&priv->regs->conf, 491 CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 492 493 /* 494 * Set safe default settings for each device. These will be 495 * tuned after the SPI flash devices are probed. 496 */ 497 if (priv->new_ver) { 498 for (cs = 0; cs < priv->flash_count; cs++) { 499 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 500 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 501 u32 addr_config = 0; 502 switch(cs) { 503 case 0: 504 flash->ahb_base = cs ? (void *)G6_SEGMENT_ADDR_START(seg_addr) : 505 priv->ahb_base; 506 debug("cs0 mem-map : %x \n", (u32)flash->ahb_base); 507 break; 508 case 1: 509 flash->ahb_base = priv->flashes[0].ahb_base + 0x8000000; //cs0 + 128Mb : use 64MB 510 debug("cs1 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 511 addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 512Mb 512 writel(addr_config, &priv->regs->segment_addr[cs]); 513 break; 514 case 2: 515 flash->ahb_base = priv->flashes[0].ahb_base + 0xc000000; //cs0 + 192Mb : use 64MB 516 debug("cs2 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 517 addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 512Mb 518 writel(addr_config, &priv->regs->segment_addr[cs]); 519 break; 520 } 521 flash->cs = cs; 522 flash->ce_ctrl_user = CE_CTRL_USERMODE; 523 flash->ce_ctrl_fread = CE_CTRL_READMODE; 524 } 525 } else { 526 for (cs = 0; cs < priv->flash_count; cs++) { 527 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 528 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 529 /* 530 * The start address of the AHB window of CE0 is 531 * read-only and is the same as the address of the 532 * overall AHB window of the controller for all flash 533 * devices. 534 */ 535 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 536 priv->ahb_base; 537 538 flash->cs = cs; 539 flash->ce_ctrl_user = CE_CTRL_USERMODE; 540 flash->ce_ctrl_fread = CE_CTRL_READMODE; 541 } 542 } 543 return 0; 544 } 545 546 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 547 size_t len) 548 { 549 size_t offset = 0; 550 551 if (!((uintptr_t)buf % 4)) { 552 readsl(ahb_base, buf, len >> 2); 553 offset = len & ~0x3; 554 len -= offset; 555 } 556 readsb(ahb_base, (u8 *)buf + offset, len); 557 558 return 0; 559 } 560 561 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 562 size_t len) 563 { 564 size_t offset = 0; 565 566 if (!((uintptr_t)buf % 4)) { 567 writesl(ahb_base, buf, len >> 2); 568 offset = len & ~0x3; 569 len -= offset; 570 } 571 writesb(ahb_base, (u8 *)buf + offset, len); 572 573 return 0; 574 } 575 576 static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 577 struct aspeed_spi_flash *flash) 578 { 579 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 580 581 /* Deselect CS and set USER command mode */ 582 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 583 584 /* Select CS */ 585 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 586 } 587 588 static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 589 struct aspeed_spi_flash *flash) 590 { 591 /* Deselect CS first */ 592 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 593 594 /* Restore default command mode */ 595 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 596 } 597 598 static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 599 struct aspeed_spi_flash *flash, 600 u8 opcode, u8 *read_buf, int len) 601 { 602 aspeed_spi_start_user(priv, flash); 603 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 604 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 605 aspeed_spi_stop_user(priv, flash); 606 607 return 0; 608 } 609 610 static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 611 struct aspeed_spi_flash *flash, 612 u8 opcode, const u8 *write_buf, int len) 613 { 614 aspeed_spi_start_user(priv, flash); 615 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 616 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 617 aspeed_spi_stop_user(priv, flash); 618 619 debug("=== write opcode [%x] ==== \n", opcode); 620 switch(opcode) { 621 case SPINOR_OP_EN4B: 622 /* For ast2600, if 2 chips ABR mode is enabled, 623 * turn on 3B mode auto clear in order to avoid 624 * the scenario where spi controller is at 4B mode 625 * and flash site is at 3B mode after 3rd switch. 626 */ 627 if (priv->new_ver == 1 && (readl(SPI_3B_AUTO_CLR_REG) & SPI_3B_AUTO_CLR)) 628 writel(readl(&priv->regs->soft_rst_cmd_ctrl) | SOFT_RST_CMD_EN, 629 &priv->regs->soft_rst_cmd_ctrl); 630 631 writel(readl(&priv->regs->ctrl) | (0x11 << flash->cs), &priv->regs->ctrl); 632 break; 633 case SPINOR_OP_EX4B: 634 writel(readl(&priv->regs->ctrl) & ~(0x11 << flash->cs), &priv->regs->ctrl); 635 break; 636 } 637 return 0; 638 } 639 640 static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 641 struct aspeed_spi_flash *flash, 642 const u8 *cmdbuf, unsigned int cmdlen, uint32_t flag) 643 { 644 int i; 645 u8 byte0 = 0x0; 646 u8 addrlen = cmdlen - 1; 647 648 /* First, send the opcode */ 649 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 650 651 if(flash->write_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_WRITE_TO_FLASH)) 652 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]); 653 else if(flash->read_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_READ_FROM_FLASH)) 654 writel(flash->ce_ctrl_user | flash->read_iomode, &priv->regs->ce_ctrl[flash->cs]); 655 656 /* 657 * The controller is configured for 4BYTE address mode. Fix 658 * the address width and send an extra byte if the SPI Flash 659 * layer uses 3 bytes addresses. 660 */ 661 if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) 662 aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); 663 664 /* Then the address */ 665 for (i = 1 ; i < cmdlen; i++) 666 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 667 } 668 669 static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 670 struct aspeed_spi_flash *flash, 671 unsigned int cmdlen, const u8 *cmdbuf, 672 unsigned int len, u8 *read_buf) 673 { 674 u8 dummy = 0xff; 675 int i; 676 677 aspeed_spi_start_user(priv, flash); 678 679 /* cmd buffer = cmd + addr + dummies */ 680 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 681 cmdlen - (flash->spi->read_dummy/8), SPI_READ_FROM_FLASH); 682 683 for (i = 0 ; i < (flash->spi->read_dummy/8); i++) 684 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 685 686 if (flash->read_iomode) { 687 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 688 CE_CTRL_IO_MODE_MASK); 689 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->read_iomode); 690 } 691 692 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 693 aspeed_spi_stop_user(priv, flash); 694 695 return 0; 696 } 697 698 static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 699 struct aspeed_spi_flash *flash, 700 unsigned int cmdlen, const u8 *cmdbuf, 701 unsigned int len, const u8 *write_buf) 702 { 703 aspeed_spi_start_user(priv, flash); 704 705 /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ 706 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen, SPI_WRITE_TO_FLASH); 707 708 /* data will use io mode */ 709 if(flash->write_iomode == CE_CTRL_IO_QUAD_DATA) 710 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]); 711 712 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 713 714 aspeed_spi_stop_user(priv, flash); 715 716 return 0; 717 } 718 719 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 720 const u8 *cmdbuf, unsigned int cmdlen) 721 { 722 u8 addrlen = cmdlen - 1; 723 u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 724 725 /* 726 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 727 * change one day 728 */ 729 if (addrlen == 4) 730 addr = (addr << 8) | cmdbuf[4]; 731 732 return addr; 733 } 734 735 /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 736 static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 737 struct aspeed_spi_flash *flash, 738 unsigned int cmdlen, const u8 *cmdbuf, 739 unsigned int len, u8 *read_buf) 740 { 741 /* cmd buffer = cmd + addr + dummies */ 742 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 743 cmdlen - (flash->spi->read_dummy/8)); 744 745 /* 746 * Switch to USER command mode: 747 * - if the AHB window configured for the device is 748 * too small for the read operation 749 * - if read offset is smaller than the decoded start address 750 * and the decoded range is not multiple of flash size 751 */ 752 if ((offset + len >= flash->ahb_size) || \ 753 (offset < ((int)flash->ahb_base & 0x0FFFFFFF) && \ 754 (((int)flash->ahb_base & 0x0FFFFFFF) % flash->spi->size) != 0)) { 755 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 756 len, read_buf); 757 } 758 759 memcpy_fromio(read_buf, flash->ahb_base + offset, len); 760 761 return 0; 762 } 763 764 static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 765 const void *dout, void *din, unsigned long flags) 766 { 767 struct udevice *bus = dev->parent; 768 struct aspeed_spi_priv *priv = dev_get_priv(bus); 769 struct aspeed_spi_flash *flash; 770 u8 *cmd_buf = priv->cmd_buf; 771 size_t data_bytes; 772 int err = 0; 773 774 flash = aspeed_spi_get_flash(dev); 775 if (!flash) 776 return -ENXIO; 777 778 if (flags & SPI_XFER_BEGIN) { 779 /* save command in progress */ 780 priv->cmd_len = bitlen / 8; 781 memcpy(cmd_buf, dout, priv->cmd_len); 782 } 783 784 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 785 /* if start and end bit are set, the data bytes is 0. */ 786 data_bytes = 0; 787 } else { 788 data_bytes = bitlen / 8; 789 } 790 791 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 792 din ? "read" : "write", priv->cmd_len, data_bytes); 793 794 if ((flags & SPI_XFER_END) || flags == 0) { 795 if (priv->cmd_len == 0) { 796 pr_err("No command is progress !\n"); 797 return -1; 798 } 799 800 if (din && data_bytes) { 801 if (priv->cmd_len == 1) 802 err = aspeed_spi_read_reg(priv, flash, 803 cmd_buf[0], 804 din, data_bytes); 805 else 806 err = aspeed_spi_read(priv, flash, 807 priv->cmd_len, 808 cmd_buf, data_bytes, 809 din); 810 } else if (dout) { 811 if (priv->cmd_len == 1) 812 err = aspeed_spi_write_reg(priv, flash, 813 cmd_buf[0], 814 dout, data_bytes); 815 else 816 err = aspeed_spi_write_user(priv, flash, 817 priv->cmd_len, 818 cmd_buf, data_bytes, 819 dout); 820 } 821 822 if (flags & SPI_XFER_END) { 823 /* clear command */ 824 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 825 priv->cmd_len = 0; 826 } 827 } 828 829 return err; 830 } 831 832 static int aspeed_spi_child_pre_probe(struct udevice *dev) 833 { 834 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 835 836 debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 837 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 838 839 if (!aspeed_spi_get_flash(dev)) 840 return -ENXIO; 841 842 return 0; 843 } 844 845 /* 846 * It is possible to automatically define a contiguous address space 847 * on top of all CEs in the AHB window of the controller but it would 848 * require much more work. Let's start with a simple mapping scheme 849 * which should work fine for a single flash device. 850 * 851 * More complex schemes should probably be defined with the device 852 * tree. 853 */ 854 static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 855 struct aspeed_spi_flash *flash) 856 { 857 u32 seg_addr; 858 859 /* could be configured through the device tree */ 860 flash->ahb_size = flash->spi->size; 861 862 if (priv->new_ver) { 863 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 864 (u32)flash->ahb_base + flash->ahb_size); 865 } else { 866 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 867 (u32)flash->ahb_base + flash->ahb_size); 868 } 869 writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 870 871 return 0; 872 } 873 874 static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 875 struct aspeed_spi_flash *flash, 876 struct udevice *dev) 877 { 878 int ret; 879 struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 880 struct spi_slave *slave = dev_get_parent_priv(dev); 881 struct udevice *bus = dev->parent; 882 u32 read_hclk; 883 884 flash->spi = spi_flash; 885 886 /* 887 * The flash device has not been probed yet. Initial transfers 888 * to read the JEDEC of the device will use the initial 889 * default settings of the registers. 890 */ 891 if (!spi_flash->name) 892 return 0; 893 894 /* 895 * The SPI flash device slave should not change, so initialize 896 * it only once. 897 */ 898 if (flash->init) 899 return 0; 900 901 debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " 902 "cmds [ erase:%x read=%x write:%x ] dummy:%d\n", 903 flash->cs, 904 spi_flash->name, spi_flash->flags, spi_flash->size, 905 spi_flash->page_size, spi_flash->sector_size, 906 spi_flash->erase_size, spi_flash->erase_opcode, 907 spi_flash->read_opcode, spi_flash->program_opcode, 908 spi_flash->read_dummy); 909 910 flash->ce_ctrl_user = CE_CTRL_USERMODE; 911 912 if(priv->new_ver) 913 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 914 else 915 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 916 917 switch(flash->spi->read_opcode) { 918 case SPINOR_OP_READ_1_1_2: 919 case SPINOR_OP_READ_1_1_2_4B: 920 flash->read_iomode = CE_CTRL_IO_DUAL_DATA; 921 break; 922 case SPINOR_OP_READ_1_1_4: 923 case SPINOR_OP_READ_1_1_4_4B: 924 flash->read_iomode = CE_CTRL_IO_QUAD_DATA; 925 break; 926 case SPINOR_OP_READ_1_4_4: 927 case SPINOR_OP_READ_1_4_4_4B: 928 flash->read_iomode = CE_CTRL_IO_QUAD_ADDR_DATA; 929 printf("need modify dummy for 3 bytes\n"); 930 break; 931 } 932 933 switch(flash->spi->program_opcode) { 934 case SPINOR_OP_PP: 935 case SPINOR_OP_PP_4B: 936 flash->write_iomode = CE_CTRL_IO_SINGLE; 937 break; 938 case SPINOR_OP_PP_1_1_4: 939 case SPINOR_OP_PP_1_1_4_4B: 940 flash->write_iomode = CE_CTRL_IO_QUAD_DATA; 941 break; 942 case SPINOR_OP_PP_1_4_4: 943 case SPINOR_OP_PP_1_4_4_4B: 944 flash->write_iomode = CE_CTRL_IO_QUAD_ADDR_DATA; 945 printf("need modify dummy for 3 bytes"); 946 break; 947 } 948 949 if(priv->new_ver) { 950 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 951 flash->read_iomode | 952 CE_CTRL_CMD(flash->spi->read_opcode) | 953 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 954 CE_CTRL_FREADMODE; 955 flash->ce_ctrl_user |= CE_G6_CTRL_CLOCK_FREQ(read_hclk); 956 } else { 957 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 958 flash->read_iomode | 959 CE_CTRL_CMD(flash->spi->read_opcode) | 960 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 961 CE_CTRL_FREADMODE; 962 } 963 964 if (flash->spi->addr_width == 4) 965 writel(readl(&priv->regs->ctrl) | 0x11 << flash->cs, &priv->regs->ctrl); 966 967 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 968 flash->ce_ctrl_user, flash->ce_ctrl_fread); 969 970 /* Set the CE Control Register default (FAST READ) */ 971 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 972 973 /* Set Address Segment Register for direct AHB accesses */ 974 aspeed_spi_flash_set_segment(priv, flash); 975 976 /* 977 * Set the Read Timing Compensation Register. This setting 978 * applies to all devices. 979 */ 980 if (!dev_read_bool(bus, "timing-calibration-disabled")) { 981 ret = aspeed_spi_timing_calibration(priv); 982 if (ret != 0) 983 return ret; 984 } 985 986 /* All done */ 987 flash->init = true; 988 989 return 0; 990 } 991 992 static int aspeed_spi_claim_bus(struct udevice *dev) 993 { 994 struct udevice *bus = dev->parent; 995 struct aspeed_spi_priv *priv = dev_get_priv(bus); 996 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 997 struct aspeed_spi_flash *flash; 998 999 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 1000 1001 flash = aspeed_spi_get_flash(dev); 1002 if (!flash) 1003 return -ENODEV; 1004 1005 return aspeed_spi_flash_init(priv, flash, dev); 1006 } 1007 1008 static int aspeed_spi_release_bus(struct udevice *dev) 1009 { 1010 struct udevice *bus = dev->parent; 1011 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 1012 1013 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 1014 1015 if (!aspeed_spi_get_flash(dev)) 1016 return -ENODEV; 1017 1018 return 0; 1019 } 1020 1021 static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 1022 { 1023 debug("%s: setting mode to %x\n", bus->name, mode); 1024 1025 if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 1026 #ifndef CONFIG_ASPEED_AST2600 1027 pr_err("%s invalid QUAD IO mode\n", bus->name); 1028 return -EINVAL; 1029 #endif 1030 } 1031 1032 /* The CE Control Register is set in claim_bus() */ 1033 return 0; 1034 } 1035 1036 static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 1037 { 1038 debug("%s: setting speed to %u\n", bus->name, hz); 1039 1040 /* The CE Control Register is set in claim_bus() */ 1041 return 0; 1042 } 1043 1044 static int aspeed_spi_count_flash_devices(struct udevice *bus) 1045 { 1046 ofnode node; 1047 int count = 0; 1048 1049 dev_for_each_subnode(node, bus) { 1050 if (ofnode_is_available(node) && 1051 ofnode_device_is_compatible(node, "spi-flash")) 1052 count++; 1053 } 1054 1055 return count; 1056 } 1057 1058 static int aspeed_spi_bind(struct udevice *bus) 1059 { 1060 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 1061 bus->seq); 1062 1063 return 0; 1064 } 1065 1066 static int aspeed_spi_probe(struct udevice *bus) 1067 { 1068 struct resource res_regs, res_ahb; 1069 struct aspeed_spi_priv *priv = dev_get_priv(bus); 1070 struct clk hclk; 1071 int ret; 1072 1073 ret = dev_read_resource(bus, 0, &res_regs); 1074 if (ret < 0) 1075 return ret; 1076 1077 priv->regs = (void __iomem *)res_regs.start; 1078 1079 ret = dev_read_resource(bus, 1, &res_ahb); 1080 if (ret < 0) 1081 return ret; 1082 1083 priv->ahb_base = (void __iomem *)res_ahb.start; 1084 priv->ahb_size = res_ahb.end - res_ahb.start; 1085 1086 ret = clk_get_by_index(bus, 0, &hclk); 1087 if (ret < 0) { 1088 pr_err("%s could not get clock: %d\n", bus->name, ret); 1089 return ret; 1090 } 1091 1092 priv->hclk_rate = clk_get_rate(&hclk); 1093 clk_free(&hclk); 1094 1095 priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1096 100000000); 1097 1098 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 1099 1100 priv->flash_count = aspeed_spi_count_flash_devices(bus); 1101 if (priv->flash_count > priv->num_cs) { 1102 pr_err("%s has too many flash devices: %d\n", bus->name, 1103 priv->flash_count); 1104 return -EINVAL; 1105 } 1106 1107 if (!priv->flash_count) { 1108 pr_err("%s has no flash devices ?!\n", bus->name); 1109 return -ENODEV; 1110 } 1111 1112 if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 1113 device_is_compatible(bus, "aspeed,ast2600-spi")) { 1114 priv->new_ver = 1; 1115 } 1116 1117 /* 1118 * There are some slight differences between the FMC and the 1119 * SPI controllers 1120 */ 1121 priv->is_fmc = dev_get_driver_data(bus); 1122 1123 ret = aspeed_spi_controller_init(priv); 1124 if (ret) 1125 return ret; 1126 1127 debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", 1128 bus->name, priv->regs, priv->ahb_base, priv->max_hz, 1129 priv->flash_count, bus->seq); 1130 1131 return 0; 1132 } 1133 1134 static const struct dm_spi_ops aspeed_spi_ops = { 1135 .claim_bus = aspeed_spi_claim_bus, 1136 .release_bus = aspeed_spi_release_bus, 1137 .set_mode = aspeed_spi_set_mode, 1138 .set_speed = aspeed_spi_set_speed, 1139 .xfer = aspeed_spi_xfer, 1140 }; 1141 1142 static const struct udevice_id aspeed_spi_ids[] = { 1143 { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1144 { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1145 { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1146 { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1147 { .compatible = "aspeed,ast2400-fmc", .data = 1 }, 1148 { } 1149 }; 1150 1151 U_BOOT_DRIVER(aspeed_spi) = { 1152 .name = "aspeed_spi", 1153 .id = UCLASS_SPI, 1154 .of_match = aspeed_spi_ids, 1155 .ops = &aspeed_spi_ops, 1156 .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1157 .child_pre_probe = aspeed_spi_child_pre_probe, 1158 .bind = aspeed_spi_bind, 1159 .probe = aspeed_spi_probe, 1160 }; 1161