1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ASPEED AST2500 FMC/SPI Controller driver 4 * 5 * Copyright (c) 2015-2018, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <asm/io.h> 16 #include <linux/ioport.h> 17 #include <malloc.h> 18 19 #define ASPEED_SPI_MAX_CS 3 20 #define FLASH_CALIBRATION_LEN 0x400 21 22 struct aspeed_spi_regs { 23 u32 conf; /* 0x00 CE Type Setting */ 24 u32 ctrl; /* 0x04 Control */ 25 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 26 u32 cmd_ctrl; /* 0x0c Command Control */ 27 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 28 u32 _reserved0[5]; /* .. */ 29 u32 segment_addr[ASPEED_SPI_MAX_CS]; 30 /* 0x30 .. 0x38 Segment Address */ 31 u32 _reserved1[5]; /* .. */ 32 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ 33 u32 _reserved2[11]; /* .. */ 34 u32 dma_ctrl; /* 0x80 DMA Control/Status */ 35 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 36 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 37 u32 dma_len; /* 0x8c DMA Length Register */ 38 u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 39 u32 timings; /* 0x94 Read Timing Compensation */ 40 41 /* not used */ 42 u32 soft_strap_status; /* 0x9c Software Strap Status */ 43 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 44 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 45 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 46 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 47 u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 48 }; 49 50 /* CE Type Setting Register */ 51 #define CONF_ENABLE_W2 BIT(18) 52 #define CONF_ENABLE_W1 BIT(17) 53 #define CONF_ENABLE_W0 BIT(16) 54 #define CONF_FLASH_TYPE2 4 55 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 56 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 57 #define CONF_FLASH_TYPE_NOR 0x0 58 #define CONF_FLASH_TYPE_SPI 0x2 59 60 /* CE Control Register */ 61 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 62 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 63 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 64 65 /* Interrupt Control and Status Register */ 66 #define INTR_CTRL_DMA_STATUS BIT(11) 67 #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 68 #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 69 #define INTR_CTRL_DMA_EN BIT(3) 70 #define INTR_CTRL_CMD_ABORT_EN BIT(2) 71 #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 72 73 /* CEx Control Register */ 74 #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 75 #define CE_CTRL_IO_QPI_DATA BIT(31) 76 #define CE_CTRL_IO_DUAL_DATA BIT(29) 77 #define CE_CTRL_IO_SINGLE 0 78 #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 79 #define CE_CTRL_IO_QUAD_DATA BIT(30) 80 #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 81 #define CE_CTRL_CMD_SHIFT 16 82 #define CE_CTRL_CMD_MASK 0xff 83 #define CE_CTRL_CMD(cmd) \ 84 (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 85 #define CE_CTRL_DUMMY_HIGH_SHIFT 14 86 #define CE_CTRL_DUMMY_HIGH_MASK 0x1 87 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 88 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 89 #define CE_CTRL_CLOCK_FREQ(div) \ 90 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 91 #define CE_G6_CTRL_CLOCK_FREQ(div) \ 92 ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 24)) 93 #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 94 #define CE_CTRL_DUMMY_LOW_MASK 0x3 95 #define CE_CTRL_DUMMY(dummy) \ 96 (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 97 << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 98 (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 99 #define CE_CTRL_STOP_ACTIVE BIT(2) 100 #define CE_CTRL_MODE_MASK 0x3 101 #define CE_CTRL_READMODE 0x0 102 #define CE_CTRL_FREADMODE 0x1 103 #define CE_CTRL_WRITEMODE 0x2 104 #define CE_CTRL_USERMODE 0x3 105 #define CE_CTRL_FREQ_MASK 0xf0fff0ff 106 107 #define SPI_READ_FROM_FLASH 0x00000001 108 #define SPI_WRITE_TO_FLASH 0x00000002 109 110 /* Auto Soft-Reset Command Control */ 111 #define SOFT_RST_CMD_EN GENMASK(1, 0) 112 113 /* 114 * The Segment Register uses a 8MB unit to encode the start address 115 * and the end address of the AHB window of a SPI flash device. 116 * Default segment addresses are : 117 * 118 * CE0 0x20000000 - 0x2fffffff 128MB 119 * CE1 0x28000000 - 0x29ffffff 32MB 120 * CE2 0x2a000000 - 0x2bffffff 32MB 121 * 122 * The full address space of the AHB window of the controller is 123 * covered and CE0 start address and CE2 end addresses are read-only. 124 */ 125 #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 126 #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 127 #define SEGMENT_ADDR_VALUE(start, end) \ 128 (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 129 130 #define G6_SEGMENT_ADDR_START(reg) (((reg) << 16) & 0x0ff00000) 131 #define G6_SEGMENT_ADDR_END(reg) (((reg) & 0x0ff00000) + 0x100000) 132 #define G6_SEGMENT_ADDR_VALUE(start, end) \ 133 ((((start) & 0x0ff00000) >> 16) | (((end) - 0x100000) & 0xffff0000)) 134 135 /* DMA Control/Status Register */ 136 #define DMA_CTRL_DELAY_SHIFT 8 137 #define DMA_CTRL_DELAY_MASK 0xf 138 #define G6_DMA_CTRL_DELAY_MASK 0xff 139 #define DMA_CTRL_FREQ_SHIFT 4 140 #define G6_DMA_CTRL_FREQ_SHIFT 16 141 142 #define DMA_CTRL_FREQ_MASK 0xf 143 #define TIMING_MASK(div, delay) \ 144 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 145 ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 146 #define G6_TIMING_MASK(div, delay) \ 147 (((delay & G6_DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 148 ((div & DMA_CTRL_FREQ_MASK) << G6_DMA_CTRL_FREQ_SHIFT)) 149 #define DAM_CTRL_REQUEST BIT(31) 150 #define DAM_CTRL_GRANT BIT(30) 151 #define DMA_CTRL_CALIB BIT(3) 152 #define DMA_CTRL_CKSUM BIT(2) 153 #define DMA_CTRL_WRITE BIT(1) 154 #define DMA_CTRL_ENABLE BIT(0) 155 156 #define DMA_GET_REQ_MAGIC 0xaeed0000 157 #define DMA_DISCARD_REQ_MAGIC 0xdeea0000 158 159 /* for ast2600 setting */ 160 #define SPI_3B_AUTO_CLR_REG 0x1e6e2510 161 #define SPI_3B_AUTO_CLR BIT(9) 162 163 164 /* 165 * flash related info 166 */ 167 struct aspeed_spi_flash { 168 u8 cs; 169 /* Initialized when the SPI bus is 170 * first claimed 171 */ 172 bool init; 173 void __iomem *ahb_base; /* AHB Window for this device */ 174 u32 ahb_size; /* AHB Window segment size */ 175 u32 ce_ctrl_user; /* CE Control Register for USER mode */ 176 u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 177 u32 read_iomode; 178 u32 write_iomode; 179 u32 max_freq; 180 struct spi_flash *spi; /* Associated SPI Flash device */ 181 }; 182 183 struct aspeed_spi_priv { 184 struct aspeed_spi_regs *regs; 185 void __iomem *ahb_base; /* AHB Window for all flash devices */ 186 int new_ver; 187 u32 ahb_size; /* AHB Window segments size */ 188 ulong hclk_rate; /* AHB clock rate */ 189 u8 num_cs; 190 bool is_fmc; 191 192 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 193 u32 flash_count; 194 195 u8 cmd_buf[16]; /* SPI command in progress */ 196 size_t cmd_len; 197 }; 198 199 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 200 { 201 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 202 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 203 u8 cs = slave_plat->cs; 204 205 if (cs >= priv->flash_count) { 206 pr_err("invalid CS %u\n", cs); 207 return NULL; 208 } 209 210 return &priv->flashes[cs]; 211 } 212 213 static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 214 { 215 u32 hclk_rate = priv->hclk_rate; 216 /* HCLK/1 .. HCLK/16 */ 217 const u8 hclk_masks[] = { 218 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 219 }; 220 u8 hclk_div = 0x4; /* default value */ 221 bool found = false; 222 u32 i, j = 0; 223 224 /* FMC/SPIR10[27:24] */ 225 for (j = 0; j < 0xf; i++) { 226 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 227 if (i == 0 && j == 0) 228 continue; 229 230 if ((hclk_rate / ((i + 1) + j * 16)) <= max_hz) { 231 found = 1; 232 break; 233 } 234 } 235 236 if (found) 237 break; 238 } 239 240 debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n", 241 hclk_rate, max_hz, j, i + 1, hclk_masks[i], hclk_rate / (i + 1 + j * 16)); 242 243 hclk_div = ((j << 4) | hclk_masks[i]); 244 245 return hclk_div; 246 } 247 248 static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 249 { 250 u32 hclk_rate = priv->hclk_rate; 251 /* HCLK/1 .. HCLK/16 */ 252 const u8 hclk_masks[] = { 253 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 254 }; 255 u32 i; 256 u32 hclk_div_setting = 0; 257 258 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 259 if (max_hz >= (hclk_rate / (i + 1))) 260 break; 261 } 262 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 263 hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 264 265 hclk_div_setting = hclk_masks[i]; 266 267 return hclk_div_setting; 268 } 269 270 /* 271 * Use some address/size under the first flash device CE0 272 */ 273 static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, 274 struct aspeed_spi_flash *flash, 275 u8 div, u8 delay) 276 { 277 u32 flash_addr = (u32)flash->ahb_base + 0x10000; 278 u32 dma_ctrl; 279 u32 checksum; 280 281 writel(flash_addr, &priv->regs->dma_flash_addr); 282 writel(FLASH_CALIBRATION_LEN, &priv->regs->dma_len); 283 284 /* 285 * When doing calibration, the SPI clock rate in the CE0 286 * Control Register and the data input delay cycles in the 287 * Read Timing Compensation Register are replaced by bit[11:4]. 288 */ 289 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 290 TIMING_MASK(div, delay); 291 292 writel(dma_ctrl, &priv->regs->dma_ctrl); 293 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 294 ; 295 296 writel(0x0, &priv->regs->intr_ctrl); 297 298 checksum = readl(&priv->regs->dma_checksum); 299 300 writel(0x0, &priv->regs->dma_ctrl); 301 return checksum; 302 } 303 304 /* 305 * Use some address/size under the first flash device CE0 306 */ 307 static u32 aspeed_g6_spi_fmc_checksum(struct aspeed_spi_priv *priv, 308 struct aspeed_spi_flash *flash, 309 u8 div, u8 delay) 310 { 311 u32 flash_addr = (u32)flash->ahb_base; 312 u32 dma_ctrl; 313 u32 checksum; 314 315 writel(DMA_GET_REQ_MAGIC, &priv->regs->dma_ctrl); 316 if (readl(&priv->regs->dma_ctrl) & DAM_CTRL_REQUEST) { 317 while (!(readl(&priv->regs->dma_ctrl) & DAM_CTRL_GRANT)) 318 ; 319 } 320 321 writel(flash_addr, &priv->regs->dma_flash_addr); 322 writel(FLASH_CALIBRATION_LEN, &priv->regs->dma_len); 323 324 /* 325 * When doing calibration, the SPI clock rate in the control 326 * register and the data input delay cycles in the 327 * read timing compensation register are replaced by bit[11:4]. 328 */ 329 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 330 G6_TIMING_MASK(div, delay); 331 332 writel(dma_ctrl, &priv->regs->dma_ctrl); 333 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 334 ; 335 336 checksum = readl(&priv->regs->dma_checksum); 337 338 writel(0x0, &priv->regs->intr_ctrl); 339 writel(0x0, &priv->regs->dma_ctrl); 340 writel(DMA_DISCARD_REQ_MAGIC, &priv->regs->dma_ctrl); 341 342 return checksum; 343 } 344 345 static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, 346 struct aspeed_spi_flash *flash, 347 u8 div, u8 delay) 348 { 349 if (priv->new_ver) 350 return aspeed_g6_spi_fmc_checksum(priv, flash, div, delay); 351 352 /* for AST2500, */ 353 if (!priv->is_fmc) { 354 pr_warn("No timing calibration support for SPI controllers"); 355 return 0xbadc0de; 356 } 357 358 return aspeed_spi_fmc_checksum(priv, flash, div, delay); 359 } 360 361 #define TIMING_DELAY_DI_4NS BIT(3) 362 #define TIMING_DELAY_HCYCLE_MAX 5 363 364 /* 365 * Check whether the data is not all 0 or 1 in order to 366 * avoid calibriate umount spi-flash. 367 */ 368 static bool aspeed_spi_calibriation_enable(const u8 *buf, u32 sz) 369 { 370 const u32 *buf_32 = (const u32 *)buf; 371 u32 i; 372 u32 valid_count = 0; 373 374 for (i = 0; i < (sz / 4); i++) { 375 if (buf_32[i] != 0 && buf_32[i] != 0xffffffff) 376 valid_count++; 377 if (valid_count > 100) 378 return true; 379 } 380 381 return false; 382 } 383 384 static int get_mid_point_of_longest_one(u8 *buf, u32 len) 385 { 386 int i; 387 int start = 0, mid_point = 0; 388 int max_cnt = 0, cnt = 0; 389 390 for (i = 0; i < len; i++) { 391 if (buf[i] == 1) { 392 cnt++; 393 } else { 394 cnt = 0; 395 start = i; 396 } 397 398 if (max_cnt < cnt) { 399 max_cnt = cnt; 400 mid_point = start + (cnt / 2); 401 } 402 } 403 404 /* 405 * In order to get a stable SPI read timing, 406 * abandon the result if the length of longest 407 * consecutive good points is too short. 408 */ 409 if (max_cnt < 4) 410 return -1; 411 412 return mid_point; 413 } 414 415 static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv, 416 struct aspeed_spi_flash *flash) 417 { 418 u32 cs = flash->cs; 419 /* HCLK/5 .. HCLK/1 */ 420 const u8 hclk_masks[] = {13, 6, 14, 7, 15}; 421 u32 timing_reg; 422 u32 checksum, gold_checksum; 423 int i; 424 u32 hcycle, delay_ns; 425 u32 final_delay = 0; 426 u32 hclk_div = 0; 427 u32 max_freq = flash->max_freq; 428 u32 reg_val; 429 u8 *tmp_buf = NULL; 430 u8 *calib_res = NULL; 431 int calib_point; 432 bool pass; 433 434 if (priv->new_ver) { 435 timing_reg = readl(&priv->regs->timings + cs); 436 if (timing_reg != 0) 437 return 0; 438 439 /* 440 * use the related low frequency to get check calibration data 441 * and get golden data. 442 */ 443 reg_val = flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK; 444 writel(reg_val, &priv->regs->ce_ctrl[cs]); 445 tmp_buf = (u8 *)malloc(FLASH_CALIBRATION_LEN); 446 if (!tmp_buf) 447 return -ENOMEM; 448 449 memcpy_fromio(tmp_buf, flash->ahb_base, FLASH_CALIBRATION_LEN); 450 if (!aspeed_spi_calibriation_enable(tmp_buf, FLASH_CALIBRATION_LEN)) { 451 debug("flash data is monotonous, skip calibration.\n"); 452 goto no_calib; 453 } 454 455 /* Compute reference checksum at lowest freq HCLK/16 */ 456 gold_checksum = aspeed_spi_read_checksum(priv, flash, 0, 0); 457 458 /* 459 * allocate a space to record calibration result for 460 * different timing compensation with fixed 461 * HCLK division. 462 */ 463 calib_res = (u8 *)malloc(6 * 17); 464 if (!calib_res) { 465 free(tmp_buf); 466 return -ENOMEM; 467 } 468 469 /* from HCLK/2 to HCLK/5 */ 470 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 471 if (priv->hclk_rate / (i + 2) > max_freq) { 472 debug("skipping freq %ld\n", priv->hclk_rate / (i + 2)); 473 continue; 474 } 475 476 max_freq = (u32)priv->hclk_rate / (i + 2); 477 478 memset(calib_res, 0x0, 6 * 17); 479 for (hcycle = 0; hcycle <= 5; hcycle++) { 480 /* increase DI delay by the step of 0.5ns */ 481 debug("Delay Enable : hcycle %x\n", hcycle); 482 for (delay_ns = 0; delay_ns <= 0xf; delay_ns++) { 483 checksum = aspeed_g6_spi_fmc_checksum(priv, flash, 484 hclk_masks[3 - i], 485 TIMING_DELAY_DI_4NS | hcycle | (delay_ns << 4)); 486 pass = (checksum == gold_checksum); 487 calib_res[hcycle * 17 + delay_ns] = pass; 488 debug("HCLK/%d, %d HCLK cycle, %d delay_ns : %s\n", 489 i + 2, hcycle, delay_ns, pass ? "PASS" : "FAIL"); 490 } 491 } 492 493 calib_point = get_mid_point_of_longest_one(calib_res, 6 * 17); 494 if (calib_point < 0) { 495 debug("cannot get good calibration point.\n"); 496 continue; 497 } 498 499 hcycle = calib_point / 17; 500 delay_ns = calib_point % 17; 501 debug("final hcycle: %d, delay_ns: %d\n", hcycle, delay_ns); 502 503 final_delay = (TIMING_DELAY_DI_4NS | hcycle | (delay_ns << 4)) << (i * 8); 504 writel(final_delay, &priv->regs->timings + cs); 505 break; 506 } 507 508 no_calib: 509 hclk_div = aspeed_g6_spi_hclk_divisor(priv, max_freq); 510 /* configure SPI clock frequency */ 511 reg_val = readl(&priv->regs->ce_ctrl[cs]); 512 reg_val = (reg_val & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); 513 writel(reg_val, &priv->regs->ce_ctrl[cs]); 514 515 /* add clock setting info for CE ctrl setting */ 516 flash->ce_ctrl_user = 517 (flash->ce_ctrl_user & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); 518 flash->ce_ctrl_fread = 519 (flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div); 520 521 debug("cs: %d, freq: %dMHz\n", cs, max_freq / 1000000); 522 523 if (tmp_buf) 524 free(tmp_buf); 525 if (calib_res) 526 free(calib_res); 527 } else { 528 /* Use the ctrl setting in aspeed_spi_flash_init() to 529 * implement calibration process. 530 */ 531 timing_reg = readl(&priv->regs->timings); 532 if (timing_reg != 0) 533 return 0; 534 535 /* Compute reference checksum at lowest freq HCLK/16 */ 536 gold_checksum = aspeed_spi_read_checksum(priv, flash, 0, 0); 537 538 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 539 u32 hdiv = 5 - i; 540 u32 hshift = (hdiv - 1) << 2; 541 bool pass = false; 542 u8 delay; 543 544 if (priv->hclk_rate / hdiv > flash->max_freq) { 545 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 546 continue; 547 } 548 549 /* Increase HCLK cycles until read succeeds */ 550 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 551 /* Try first with a 4ns DI delay */ 552 delay = TIMING_DELAY_DI_4NS | hcycle; 553 checksum = aspeed_spi_read_checksum(priv, flash, hclk_masks[i], 554 delay); 555 pass = (checksum == gold_checksum); 556 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 557 hdiv, hcycle, pass ? "PASS" : "FAIL"); 558 559 /* Try again with more HCLK cycles */ 560 if (!pass) 561 continue; 562 563 /* Try without the 4ns DI delay */ 564 delay = hcycle; 565 checksum = aspeed_spi_read_checksum(priv, flash, hclk_masks[i], 566 delay); 567 pass = (checksum == gold_checksum); 568 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 569 hdiv, hcycle, pass ? "PASS" : "FAIL"); 570 571 /* All good for this freq */ 572 if (pass) 573 break; 574 } 575 576 if (pass) { 577 timing_reg &= ~(0xfu << hshift); 578 timing_reg |= delay << hshift; 579 } 580 } 581 582 debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 583 writel(timing_reg, &priv->regs->timings); 584 } 585 586 return 0; 587 } 588 589 static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 590 { 591 int cs; 592 593 /* 594 * Enable write on all flash devices as USER command mode 595 * requires it. 596 */ 597 setbits_le32(&priv->regs->conf, 598 CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 599 600 /* 601 * Set safe default settings for each device. These will be 602 * tuned after the SPI flash devices are probed. 603 */ 604 if (priv->new_ver) { 605 for (cs = 0; cs < priv->flash_count; cs++) { 606 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 607 u32 addr_config = 0; 608 switch(cs) { 609 case 0: 610 flash->ahb_base = priv->ahb_base; 611 debug("cs0 mem-map : %x\n", (u32)flash->ahb_base); 612 break; 613 case 1: 614 flash->ahb_base = priv->flashes[0].ahb_base + 0x4000000; /* cs0 + 64MB */ 615 debug("cs1 mem-map : %x end %x\n", 616 (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 617 break; 618 case 2: 619 flash->ahb_base = priv->flashes[0].ahb_base + 0x4000000 * 2; /* cs0 + 128MB : use 64MB */ 620 debug("cs2 mem-map : %x end %x\n", 621 (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 622 break; 623 } 624 addr_config = 625 G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 626 writel(addr_config, &priv->regs->segment_addr[cs]); 627 flash->cs = cs; 628 flash->ce_ctrl_user = CE_CTRL_USERMODE; 629 flash->ce_ctrl_fread = CE_CTRL_READMODE; 630 } 631 } else { 632 for (cs = 0; cs < priv->flash_count; cs++) { 633 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 634 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 635 /* 636 * The start address of the AHB window of CE0 is 637 * read-only and is the same as the address of the 638 * overall AHB window of the controller for all flash 639 * devices. 640 */ 641 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 642 priv->ahb_base; 643 644 flash->cs = cs; 645 flash->ce_ctrl_user = CE_CTRL_USERMODE; 646 flash->ce_ctrl_fread = CE_CTRL_READMODE; 647 } 648 } 649 return 0; 650 } 651 652 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 653 size_t len) 654 { 655 size_t offset = 0; 656 657 if (!((uintptr_t)buf % 4)) { 658 readsl(ahb_base, buf, len >> 2); 659 offset = len & ~0x3; 660 len -= offset; 661 } 662 readsb(ahb_base, (u8 *)buf + offset, len); 663 664 return 0; 665 } 666 667 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 668 size_t len) 669 { 670 size_t offset = 0; 671 672 if (!((uintptr_t)buf % 4)) { 673 writesl(ahb_base, buf, len >> 2); 674 offset = len & ~0x3; 675 len -= offset; 676 } 677 writesb(ahb_base, (u8 *)buf + offset, len); 678 679 return 0; 680 } 681 682 static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 683 struct aspeed_spi_flash *flash) 684 { 685 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 686 687 /* Deselect CS and set USER command mode */ 688 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 689 690 /* Select CS */ 691 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 692 } 693 694 static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 695 struct aspeed_spi_flash *flash) 696 { 697 /* Deselect CS first */ 698 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 699 700 /* Restore default command mode */ 701 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 702 } 703 704 static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 705 struct aspeed_spi_flash *flash, 706 u8 opcode, u8 *read_buf, int len) 707 { 708 aspeed_spi_start_user(priv, flash); 709 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 710 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 711 aspeed_spi_stop_user(priv, flash); 712 713 return 0; 714 } 715 716 static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 717 struct aspeed_spi_flash *flash, 718 u8 opcode, const u8 *write_buf, int len) 719 { 720 aspeed_spi_start_user(priv, flash); 721 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 722 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 723 aspeed_spi_stop_user(priv, flash); 724 725 debug("=== write opcode [%x] ==== \n", opcode); 726 switch(opcode) { 727 case SPINOR_OP_EN4B: 728 /* For ast2600, if 2 chips ABR mode is enabled, 729 * turn on 3B mode auto clear in order to avoid 730 * the scenario where spi controller is at 4B mode 731 * and flash site is at 3B mode after 3rd switch. 732 */ 733 if (priv->new_ver == 1 && (readl(SPI_3B_AUTO_CLR_REG) & SPI_3B_AUTO_CLR)) 734 writel(readl(&priv->regs->soft_rst_cmd_ctrl) | SOFT_RST_CMD_EN, 735 &priv->regs->soft_rst_cmd_ctrl); 736 737 writel(readl(&priv->regs->ctrl) | (0x11 << flash->cs), &priv->regs->ctrl); 738 break; 739 case SPINOR_OP_EX4B: 740 writel(readl(&priv->regs->ctrl) & ~(0x11 << flash->cs), &priv->regs->ctrl); 741 break; 742 } 743 return 0; 744 } 745 746 static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 747 struct aspeed_spi_flash *flash, 748 const u8 *cmdbuf, unsigned int cmdlen, uint32_t flag) 749 { 750 int i; 751 752 /* First, send the opcode */ 753 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 754 755 if(flash->write_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_WRITE_TO_FLASH)) 756 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]); 757 else if(flash->read_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_READ_FROM_FLASH)) 758 writel(flash->ce_ctrl_user | flash->read_iomode, &priv->regs->ce_ctrl[flash->cs]); 759 760 /* Then the address */ 761 for (i = 1 ; i < cmdlen; i++) 762 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 763 } 764 765 static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 766 struct aspeed_spi_flash *flash, 767 unsigned int cmdlen, const u8 *cmdbuf, 768 unsigned int len, u8 *read_buf) 769 { 770 u8 dummy = 0x00; 771 int i; 772 773 aspeed_spi_start_user(priv, flash); 774 775 /* cmd buffer = cmd + addr + dummies */ 776 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 777 cmdlen - (flash->spi->read_dummy / 8), SPI_READ_FROM_FLASH); 778 779 for (i = 0; i < (flash->spi->read_dummy / 8); i++) 780 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 781 782 if (flash->read_iomode) { 783 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 784 CE_CTRL_IO_MODE_MASK); 785 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->read_iomode); 786 } 787 788 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 789 aspeed_spi_stop_user(priv, flash); 790 791 return 0; 792 } 793 794 static ssize_t aspeed_spi_read_sfdp(struct aspeed_spi_priv *priv, 795 struct aspeed_spi_flash *flash, 796 unsigned int cmdlen, const u8 *cmdbuf, 797 unsigned int len, u8 *read_buf) 798 { 799 u8 dummy = 0x00; 800 int i; 801 802 /* only 1-1-1 mode is used to read SFDP */ 803 aspeed_spi_start_user(priv, flash); 804 805 /* cmd buffer = cmd + addr + dummies */ 806 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 807 cmdlen - (flash->spi->read_dummy / 8), 0); 808 809 for (i = 0; i < (flash->spi->read_dummy / 8); i++) 810 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 811 812 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 813 aspeed_spi_stop_user(priv, flash); 814 815 return 0; 816 } 817 818 static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 819 struct aspeed_spi_flash *flash, 820 unsigned int cmdlen, const u8 *cmdbuf, 821 unsigned int len, const u8 *write_buf) 822 { 823 aspeed_spi_start_user(priv, flash); 824 825 /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ 826 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen, SPI_WRITE_TO_FLASH); 827 828 /* data will use io mode */ 829 if(flash->write_iomode == CE_CTRL_IO_QUAD_DATA) 830 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]); 831 832 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 833 834 aspeed_spi_stop_user(priv, flash); 835 836 return 0; 837 } 838 839 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 840 const u8 *cmdbuf, unsigned int cmdlen) 841 { 842 u8 addrlen = cmdlen - 1; 843 u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 844 845 /* 846 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 847 * change one day 848 */ 849 if (addrlen == 4) 850 addr = (addr << 8) | cmdbuf[4]; 851 852 return addr; 853 } 854 855 /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 856 static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 857 struct aspeed_spi_flash *flash, 858 unsigned int cmdlen, const u8 *cmdbuf, 859 unsigned int len, u8 *read_buf) 860 { 861 /* cmd buffer = cmd + addr + dummies */ 862 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 863 cmdlen - (flash->spi->read_dummy/8)); 864 865 /* 866 * Switch to USER command mode: 867 * - if read SFDP content. 868 * - if the AHB window configured for the device is 869 * too small for the read operation 870 * - if read offset is smaller than the decoded start address 871 * and the decoded range is not multiple of flash size. 872 */ 873 if ((offset + len >= flash->ahb_size) || \ 874 (offset < ((int)flash->ahb_base & 0x0FFFFFFF) && \ 875 (((int)flash->ahb_base & 0x0FFFFFFF) % flash->spi->size) != 0)) { 876 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 877 len, read_buf); 878 } 879 880 memcpy_fromio(read_buf, flash->ahb_base + offset, len); 881 882 return 0; 883 } 884 885 static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 886 const void *dout, void *din, unsigned long flags) 887 { 888 struct udevice *bus = dev->parent; 889 struct aspeed_spi_priv *priv = dev_get_priv(bus); 890 struct aspeed_spi_flash *flash; 891 u8 *cmd_buf = priv->cmd_buf; 892 size_t data_bytes; 893 int err = 0; 894 u32 iomode; 895 896 flash = aspeed_spi_get_flash(dev); 897 if (!flash) 898 return -ENXIO; 899 900 if (flags & SPI_XFER_BEGIN) { 901 /* save command in progress */ 902 priv->cmd_len = bitlen / 8; 903 memcpy(cmd_buf, dout, priv->cmd_len); 904 } 905 906 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 907 /* if start and end bit are set, the data bytes is 0. */ 908 data_bytes = 0; 909 } else { 910 data_bytes = bitlen / 8; 911 } 912 913 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 914 din ? "read" : "write", priv->cmd_len, data_bytes); 915 916 if ((flags & SPI_XFER_END) || flags == 0) { 917 if (priv->cmd_len == 0) { 918 pr_err("No command is progress !\n"); 919 return -1; 920 } 921 922 if (din && data_bytes) { 923 if (priv->cmd_len == 1) { 924 err = aspeed_spi_read_reg(priv, flash, 925 cmd_buf[0], 926 din, data_bytes); 927 } else if (cmd_buf[0] == SPINOR_OP_RDSFDP) { 928 err = aspeed_spi_read_sfdp(priv, flash, 929 priv->cmd_len, 930 cmd_buf, data_bytes, 931 din); 932 } else if (cmd_buf[0] == SPINOR_OP_RDAR) { 933 /* only for Cypress flash */ 934 iomode = flash->read_iomode; 935 flash->read_iomode = 0; 936 err = aspeed_spi_read_user(priv, flash, 937 priv->cmd_len, 938 cmd_buf, data_bytes, 939 din); 940 flash->read_iomode = iomode; 941 } else { 942 err = aspeed_spi_read(priv, flash, 943 priv->cmd_len, 944 cmd_buf, data_bytes, 945 din); 946 } 947 } else if (dout) { 948 if (priv->cmd_len == 1) { 949 err = aspeed_spi_write_reg(priv, flash, 950 cmd_buf[0], 951 dout, data_bytes); 952 } else { 953 err = aspeed_spi_write_user(priv, flash, 954 priv->cmd_len, 955 cmd_buf, data_bytes, 956 dout); 957 } 958 } 959 960 if (flags & SPI_XFER_END) { 961 /* clear command */ 962 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 963 priv->cmd_len = 0; 964 } 965 } 966 967 return err; 968 } 969 970 static int aspeed_spi_child_pre_probe(struct udevice *dev) 971 { 972 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 973 974 debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 975 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 976 977 if (!aspeed_spi_get_flash(dev)) 978 return -ENXIO; 979 980 return 0; 981 } 982 983 /* 984 * AST2600 SPI memory controllers support multiple chip selects. 985 * The start address of a decode range should be multiple 986 * of its related flash size. Namely, the total decoded size 987 * from flash 0 to flash N should be multiple of (N + 1) flash size. 988 */ 989 void aspeed_g6_adjust_decode_sz(u32 decode_sz_arr[], int len) 990 { 991 int cs, j; 992 u32 sz; 993 994 for (cs = len - 1; cs >= 0; cs--) { 995 sz = 0; 996 for (j = 0; j < cs; j++) 997 sz += decode_sz_arr[j]; 998 999 if (sz % decode_sz_arr[cs] != 0) 1000 decode_sz_arr[0] += (sz % decode_sz_arr[cs]); 1001 } 1002 } 1003 1004 /* 1005 * It is possible to automatically define a contiguous address space 1006 * on top of all CEs in the AHB window of the controller but it would 1007 * require much more work. Let's start with a simple mapping scheme 1008 * which should work fine for a single flash device. 1009 * 1010 * More complex schemes should probably be defined with the device 1011 * tree. 1012 */ 1013 static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 1014 struct aspeed_spi_flash *flash) 1015 { 1016 u32 seg_addr; 1017 u32 decode_sz_arr[ASPEED_SPI_MAX_CS]; 1018 u32 reg_val; 1019 u32 cs; 1020 u32 total_decode_sz = 0; 1021 u32 cur_offset = 0; 1022 1023 /* could be configured through the device tree */ 1024 flash->ahb_size = flash->spi->size; 1025 1026 if (priv->new_ver) { 1027 for (cs = 0; cs < ASPEED_SPI_MAX_CS; cs++) { 1028 reg_val = readl(&priv->regs->segment_addr[cs]); 1029 if (reg_val != 0 && 1030 G6_SEGMENT_ADDR_END(reg_val) > G6_SEGMENT_ADDR_START(reg_val)) { 1031 decode_sz_arr[cs] = 1032 G6_SEGMENT_ADDR_END(reg_val) - G6_SEGMENT_ADDR_START(reg_val); 1033 } else { 1034 decode_sz_arr[cs] = 0; 1035 } 1036 } 1037 1038 decode_sz_arr[flash->cs] = flash->ahb_size; 1039 aspeed_g6_adjust_decode_sz(decode_sz_arr, flash->cs + 1); 1040 1041 for (cs = 0; cs < ASPEED_SPI_MAX_CS; cs++) 1042 total_decode_sz += decode_sz_arr[cs]; 1043 1044 if (total_decode_sz > priv->ahb_size) { 1045 printf("err: Total decoded size, 0x%x, is too large.\n", total_decode_sz); 1046 return -ENOMEM; 1047 } 1048 1049 for (cs = 0; cs < ASPEED_SPI_MAX_CS; cs++) { 1050 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 1051 1052 flash->ahb_base = (void __iomem *)((u32)priv->ahb_base + cur_offset); 1053 1054 if (decode_sz_arr[cs] != 0) { 1055 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 1056 (u32)flash->ahb_base + decode_sz_arr[cs]); 1057 } else { 1058 seg_addr = 0; 1059 } 1060 1061 writel(seg_addr, &priv->regs->segment_addr[cs]); 1062 flash->ahb_size = decode_sz_arr[cs]; 1063 cur_offset += decode_sz_arr[cs]; 1064 } 1065 } else { 1066 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 1067 (u32)flash->ahb_base + flash->ahb_size); 1068 writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 1069 } 1070 1071 return 0; 1072 } 1073 1074 static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 1075 struct aspeed_spi_flash *flash, 1076 struct udevice *dev) 1077 { 1078 int ret; 1079 struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 1080 struct spi_slave *slave = dev_get_parent_priv(dev); 1081 struct udevice *bus = dev->parent; 1082 u32 read_hclk; 1083 1084 flash->spi = spi_flash; 1085 1086 /* 1087 * The flash device has not been probed yet. Initial transfers 1088 * to read the JEDEC of the device will use the initial 1089 * default settings of the registers. 1090 */ 1091 if (!spi_flash->name) 1092 return 0; 1093 1094 /* 1095 * The SPI flash device slave should not change, so initialize 1096 * it only once. 1097 */ 1098 if (flash->init) 1099 return 0; 1100 1101 debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d", 1102 flash->cs, 1103 spi_flash->name, spi_flash->flags, spi_flash->size, 1104 spi_flash->page_size, spi_flash->sector_size, 1105 spi_flash->erase_size); 1106 debug(" cmds [ erase:%x read=%x write:%x ] dummy:%d, speed:%d\n", 1107 spi_flash->erase_opcode, 1108 spi_flash->read_opcode, spi_flash->program_opcode, 1109 spi_flash->read_dummy, slave->speed); 1110 1111 flash->ce_ctrl_user = CE_CTRL_USERMODE; 1112 flash->max_freq = slave->speed; 1113 1114 if(priv->new_ver) 1115 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 1116 else 1117 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 1118 1119 switch(flash->spi->read_opcode) { 1120 case SPINOR_OP_READ_1_1_2: 1121 case SPINOR_OP_READ_1_1_2_4B: 1122 flash->read_iomode = CE_CTRL_IO_DUAL_DATA; 1123 break; 1124 case SPINOR_OP_READ_1_1_4: 1125 case SPINOR_OP_READ_1_1_4_4B: 1126 flash->read_iomode = CE_CTRL_IO_QUAD_DATA; 1127 break; 1128 case SPINOR_OP_READ_1_4_4: 1129 case SPINOR_OP_READ_1_4_4_4B: 1130 flash->read_iomode = CE_CTRL_IO_QUAD_ADDR_DATA; 1131 printf("need modify dummy for 3 bytes\n"); 1132 break; 1133 } 1134 1135 switch(flash->spi->program_opcode) { 1136 case SPINOR_OP_PP: 1137 case SPINOR_OP_PP_4B: 1138 flash->write_iomode = CE_CTRL_IO_SINGLE; 1139 break; 1140 case SPINOR_OP_PP_1_1_4: 1141 case SPINOR_OP_PP_1_1_4_4B: 1142 flash->write_iomode = CE_CTRL_IO_QUAD_DATA; 1143 break; 1144 case SPINOR_OP_PP_1_4_4: 1145 case SPINOR_OP_PP_1_4_4_4B: 1146 flash->write_iomode = CE_CTRL_IO_QUAD_ADDR_DATA; 1147 printf("need modify dummy for 3 bytes"); 1148 break; 1149 } 1150 1151 if(priv->new_ver) { 1152 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 1153 flash->read_iomode | 1154 CE_CTRL_CMD(flash->spi->read_opcode) | 1155 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 1156 CE_CTRL_FREADMODE; 1157 flash->ce_ctrl_user |= CE_G6_CTRL_CLOCK_FREQ(read_hclk); 1158 } else { 1159 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 1160 flash->read_iomode | 1161 CE_CTRL_CMD(flash->spi->read_opcode) | 1162 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 1163 CE_CTRL_FREADMODE; 1164 } 1165 1166 if (flash->spi->addr_width == 4) 1167 writel(readl(&priv->regs->ctrl) | 0x11 << flash->cs, &priv->regs->ctrl); 1168 1169 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 1170 flash->ce_ctrl_user, flash->ce_ctrl_fread); 1171 1172 /* Set the CE Control Register default (FAST READ) */ 1173 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 1174 1175 /* Set Address Segment Register for direct AHB accesses */ 1176 ret = aspeed_spi_flash_set_segment(priv, flash); 1177 if (ret != 0) 1178 return ret; 1179 1180 /* 1181 * Set the Read Timing Compensation Register. This setting 1182 * applies to all devices. 1183 */ 1184 if (!dev_read_bool(bus, "timing-calibration-disabled")) { 1185 ret = aspeed_spi_timing_calibration(priv, flash); 1186 if (ret != 0) 1187 return ret; 1188 } 1189 1190 /* All done */ 1191 flash->init = true; 1192 1193 return 0; 1194 } 1195 1196 static int aspeed_spi_claim_bus(struct udevice *dev) 1197 { 1198 struct udevice *bus = dev->parent; 1199 struct aspeed_spi_priv *priv = dev_get_priv(bus); 1200 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 1201 struct aspeed_spi_flash *flash; 1202 1203 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 1204 1205 flash = aspeed_spi_get_flash(dev); 1206 if (!flash) 1207 return -ENODEV; 1208 1209 return aspeed_spi_flash_init(priv, flash, dev); 1210 } 1211 1212 static int aspeed_spi_release_bus(struct udevice *dev) 1213 { 1214 struct udevice *bus = dev->parent; 1215 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 1216 1217 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 1218 1219 if (!aspeed_spi_get_flash(dev)) 1220 return -ENODEV; 1221 1222 return 0; 1223 } 1224 1225 static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 1226 { 1227 debug("%s: setting mode to %x\n", bus->name, mode); 1228 1229 if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 1230 #ifndef CONFIG_ASPEED_AST2600 1231 pr_err("%s invalid QUAD IO mode\n", bus->name); 1232 return -EINVAL; 1233 #endif 1234 } 1235 1236 /* The CE Control Register is set in claim_bus() */ 1237 return 0; 1238 } 1239 1240 static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 1241 { 1242 debug("%s: setting speed to %u\n", bus->name, hz); 1243 1244 /* The CE Control Register is set in claim_bus() */ 1245 return 0; 1246 } 1247 1248 static int aspeed_spi_count_flash_devices(struct udevice *bus) 1249 { 1250 ofnode node; 1251 int count = 0; 1252 1253 dev_for_each_subnode(node, bus) { 1254 if (ofnode_is_available(node) && 1255 (ofnode_device_is_compatible(node, "spi-flash") || 1256 ofnode_device_is_compatible(node, "jedec,spi-nor"))) 1257 count++; 1258 } 1259 1260 return count; 1261 } 1262 1263 static int aspeed_spi_bind(struct udevice *bus) 1264 { 1265 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 1266 bus->seq); 1267 1268 return 0; 1269 } 1270 1271 static int aspeed_spi_probe(struct udevice *bus) 1272 { 1273 struct resource res_regs, res_ahb; 1274 struct aspeed_spi_priv *priv = dev_get_priv(bus); 1275 struct clk hclk; 1276 int ret; 1277 1278 ret = dev_read_resource(bus, 0, &res_regs); 1279 if (ret < 0) 1280 return ret; 1281 1282 priv->regs = (void __iomem *)res_regs.start; 1283 1284 ret = dev_read_resource(bus, 1, &res_ahb); 1285 if (ret < 0) 1286 return ret; 1287 1288 priv->ahb_base = (void __iomem *)res_ahb.start; 1289 priv->ahb_size = res_ahb.end - res_ahb.start + 1; 1290 1291 ret = clk_get_by_index(bus, 0, &hclk); 1292 if (ret < 0) { 1293 pr_err("%s could not get clock: %d\n", bus->name, ret); 1294 return ret; 1295 } 1296 1297 priv->hclk_rate = clk_get_rate(&hclk); 1298 clk_free(&hclk); 1299 1300 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 1301 1302 priv->flash_count = aspeed_spi_count_flash_devices(bus); 1303 if (priv->flash_count > priv->num_cs) { 1304 pr_err("%s has too many flash devices: %d\n", bus->name, 1305 priv->flash_count); 1306 return -EINVAL; 1307 } 1308 1309 if (!priv->flash_count) { 1310 pr_err("%s has no flash devices ?!\n", bus->name); 1311 return -ENODEV; 1312 } 1313 1314 if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 1315 device_is_compatible(bus, "aspeed,ast2600-spi")) { 1316 priv->new_ver = 1; 1317 } 1318 1319 /* 1320 * There are some slight differences between the FMC and the 1321 * SPI controllers 1322 */ 1323 priv->is_fmc = dev_get_driver_data(bus); 1324 1325 ret = aspeed_spi_controller_init(priv); 1326 if (ret) 1327 return ret; 1328 1329 debug("%s probed regs=%p ahb_base=%p cs_num=%d seq=%d\n", 1330 bus->name, priv->regs, priv->ahb_base, priv->flash_count, bus->seq); 1331 1332 return 0; 1333 } 1334 1335 static const struct dm_spi_ops aspeed_spi_ops = { 1336 .claim_bus = aspeed_spi_claim_bus, 1337 .release_bus = aspeed_spi_release_bus, 1338 .set_mode = aspeed_spi_set_mode, 1339 .set_speed = aspeed_spi_set_speed, 1340 .xfer = aspeed_spi_xfer, 1341 }; 1342 1343 static const struct udevice_id aspeed_spi_ids[] = { 1344 { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1345 { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1346 { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1347 { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1348 { .compatible = "aspeed,ast2400-fmc", .data = 1 }, 1349 { } 1350 }; 1351 1352 U_BOOT_DRIVER(aspeed_spi) = { 1353 .name = "aspeed_spi", 1354 .id = UCLASS_SPI, 1355 .of_match = aspeed_spi_ids, 1356 .ops = &aspeed_spi_ops, 1357 .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1358 .child_pre_probe = aspeed_spi_child_pre_probe, 1359 .bind = aspeed_spi_bind, 1360 .probe = aspeed_spi_probe, 1361 }; 1362