1499853d6Sryan_chen // SPDX-License-Identifier: GPL-2.0+ 2499853d6Sryan_chen /* 3499853d6Sryan_chen * ASPEED AST2500 FMC/SPI Controller driver 4499853d6Sryan_chen * 5499853d6Sryan_chen * Copyright (c) 2015-2018, IBM Corporation. 6499853d6Sryan_chen */ 7499853d6Sryan_chen 8499853d6Sryan_chen #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9499853d6Sryan_chen 10499853d6Sryan_chen #include <common.h> 11499853d6Sryan_chen #include <clk.h> 12499853d6Sryan_chen #include <dm.h> 13499853d6Sryan_chen #include <spi.h> 14499853d6Sryan_chen #include <spi_flash.h> 15499853d6Sryan_chen #include <asm/io.h> 16499853d6Sryan_chen #include <linux/ioport.h> 17499853d6Sryan_chen 18499853d6Sryan_chen #define ASPEED_SPI_MAX_CS 3 19*beec505fSChin-Ting Kuo #define FLASH_CALIBRATION_LEN 0x400 20499853d6Sryan_chen 21499853d6Sryan_chen struct aspeed_spi_regs { 22499853d6Sryan_chen u32 conf; /* 0x00 CE Type Setting */ 23499853d6Sryan_chen u32 ctrl; /* 0x04 Control */ 24499853d6Sryan_chen u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 25499853d6Sryan_chen u32 cmd_ctrl; /* 0x0c Command Control */ 26499853d6Sryan_chen u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 27499853d6Sryan_chen u32 _reserved0[5]; /* .. */ 28499853d6Sryan_chen u32 segment_addr[ASPEED_SPI_MAX_CS]; 29499853d6Sryan_chen /* 0x30 .. 0x38 Segment Address */ 300a73b911SChin-Ting Kuo u32 _reserved1[5]; /* .. */ 310a73b911SChin-Ting Kuo u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ 320a73b911SChin-Ting Kuo u32 _reserved2[11]; /* .. */ 33499853d6Sryan_chen u32 dma_ctrl; /* 0x80 DMA Control/Status */ 34499853d6Sryan_chen u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 35499853d6Sryan_chen u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 36499853d6Sryan_chen u32 dma_len; /* 0x8c DMA Length Register */ 37499853d6Sryan_chen u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 38499853d6Sryan_chen u32 timings; /* 0x94 Read Timing Compensation */ 39499853d6Sryan_chen 40499853d6Sryan_chen /* not used */ 41499853d6Sryan_chen u32 soft_strap_status; /* 0x9c Software Strap Status */ 42499853d6Sryan_chen u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 43499853d6Sryan_chen u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 44499853d6Sryan_chen u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 45499853d6Sryan_chen u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 46499853d6Sryan_chen u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 47499853d6Sryan_chen }; 48499853d6Sryan_chen 49499853d6Sryan_chen /* CE Type Setting Register */ 50499853d6Sryan_chen #define CONF_ENABLE_W2 BIT(18) 51499853d6Sryan_chen #define CONF_ENABLE_W1 BIT(17) 52499853d6Sryan_chen #define CONF_ENABLE_W0 BIT(16) 53499853d6Sryan_chen #define CONF_FLASH_TYPE2 4 54499853d6Sryan_chen #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 55499853d6Sryan_chen #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 56499853d6Sryan_chen #define CONF_FLASH_TYPE_NOR 0x0 57499853d6Sryan_chen #define CONF_FLASH_TYPE_SPI 0x2 58499853d6Sryan_chen 59499853d6Sryan_chen /* CE Control Register */ 60499853d6Sryan_chen #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 61499853d6Sryan_chen #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 62499853d6Sryan_chen #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 63499853d6Sryan_chen 64499853d6Sryan_chen /* Interrupt Control and Status Register */ 65499853d6Sryan_chen #define INTR_CTRL_DMA_STATUS BIT(11) 66499853d6Sryan_chen #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 67499853d6Sryan_chen #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 68499853d6Sryan_chen #define INTR_CTRL_DMA_EN BIT(3) 69499853d6Sryan_chen #define INTR_CTRL_CMD_ABORT_EN BIT(2) 70499853d6Sryan_chen #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 71499853d6Sryan_chen 72499853d6Sryan_chen /* CEx Control Register */ 73499853d6Sryan_chen #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 7476e3c7a9Sryan_chen #define CE_CTRL_IO_QPI_DATA BIT(31) 75499853d6Sryan_chen #define CE_CTRL_IO_DUAL_DATA BIT(29) 76499853d6Sryan_chen #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 77499853d6Sryan_chen #define CE_CTRL_IO_QUAD_DATA BIT(30) 78499853d6Sryan_chen #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 79499853d6Sryan_chen #define CE_CTRL_CMD_SHIFT 16 80499853d6Sryan_chen #define CE_CTRL_CMD_MASK 0xff 81499853d6Sryan_chen #define CE_CTRL_CMD(cmd) \ 82499853d6Sryan_chen (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 83499853d6Sryan_chen #define CE_CTRL_DUMMY_HIGH_SHIFT 14 84499853d6Sryan_chen #define CE_CTRL_DUMMY_HIGH_MASK 0x1 85499853d6Sryan_chen #define CE_CTRL_CLOCK_FREQ_SHIFT 8 86499853d6Sryan_chen #define CE_CTRL_CLOCK_FREQ_MASK 0xf 87499853d6Sryan_chen #define CE_CTRL_CLOCK_FREQ(div) \ 88499853d6Sryan_chen (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 897d182336Sryan_chen #define CE_G6_CTRL_CLOCK_FREQ(div) \ 907d182336Sryan_chen ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20)) 91499853d6Sryan_chen #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 92499853d6Sryan_chen #define CE_CTRL_DUMMY_LOW_MASK 0x3 93499853d6Sryan_chen #define CE_CTRL_DUMMY(dummy) \ 94499853d6Sryan_chen (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 95499853d6Sryan_chen << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 96499853d6Sryan_chen (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 97499853d6Sryan_chen #define CE_CTRL_STOP_ACTIVE BIT(2) 98499853d6Sryan_chen #define CE_CTRL_MODE_MASK 0x3 99499853d6Sryan_chen #define CE_CTRL_READMODE 0x0 100499853d6Sryan_chen #define CE_CTRL_FREADMODE 0x1 101499853d6Sryan_chen #define CE_CTRL_WRITEMODE 0x2 102499853d6Sryan_chen #define CE_CTRL_USERMODE 0x3 103499853d6Sryan_chen 1040a73b911SChin-Ting Kuo /* Auto Soft-Reset Command Control */ 1050a73b911SChin-Ting Kuo #define SOFT_RST_CMD_EN GENMASK(1, 0) 1060a73b911SChin-Ting Kuo 107499853d6Sryan_chen /* 108499853d6Sryan_chen * The Segment Register uses a 8MB unit to encode the start address 109499853d6Sryan_chen * and the end address of the AHB window of a SPI flash device. 110499853d6Sryan_chen * Default segment addresses are : 111499853d6Sryan_chen * 112499853d6Sryan_chen * CE0 0x20000000 - 0x2fffffff 128MB 113499853d6Sryan_chen * CE1 0x28000000 - 0x29ffffff 32MB 114499853d6Sryan_chen * CE2 0x2a000000 - 0x2bffffff 32MB 115499853d6Sryan_chen * 116499853d6Sryan_chen * The full address space of the AHB window of the controller is 117499853d6Sryan_chen * covered and CE0 start address and CE2 end addresses are read-only. 118499853d6Sryan_chen */ 119499853d6Sryan_chen #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 120499853d6Sryan_chen #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 121499853d6Sryan_chen #define SEGMENT_ADDR_VALUE(start, end) \ 122499853d6Sryan_chen (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 123499853d6Sryan_chen 124da83dd7eSryan_chen #define G6_SEGMENT_ADDR_START(reg) (reg & 0xffff) 125da83dd7eSryan_chen #define G6_SEGMENT_ADDR_END(reg) ((reg >> 16) & 0xffff) 126da83dd7eSryan_chen #define G6_SEGMENT_ADDR_VALUE(start, end) \ 1276167da3dSryan_chen ((((start) >> 16) & 0xffff) | (((end) - 0x100000) & 0xffff0000)) 128da83dd7eSryan_chen 129499853d6Sryan_chen /* DMA Control/Status Register */ 130499853d6Sryan_chen #define DMA_CTRL_DELAY_SHIFT 8 131499853d6Sryan_chen #define DMA_CTRL_DELAY_MASK 0xf 132*beec505fSChin-Ting Kuo #define G6_DMA_CTRL_DELAY_MASK 0xff 133499853d6Sryan_chen #define DMA_CTRL_FREQ_SHIFT 4 134f87fadc3Sryan_chen #define G6_DMA_CTRL_FREQ_SHIFT 16 135f87fadc3Sryan_chen 136499853d6Sryan_chen #define DMA_CTRL_FREQ_MASK 0xf 137499853d6Sryan_chen #define TIMING_MASK(div, delay) \ 138499853d6Sryan_chen (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 139499853d6Sryan_chen ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 140f87fadc3Sryan_chen #define G6_TIMING_MASK(div, delay) \ 141*beec505fSChin-Ting Kuo (((delay & G6_DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 142f87fadc3Sryan_chen ((div & DMA_CTRL_FREQ_MASK) << G6_DMA_CTRL_FREQ_SHIFT)) 143499853d6Sryan_chen #define DMA_CTRL_CALIB BIT(3) 144499853d6Sryan_chen #define DMA_CTRL_CKSUM BIT(2) 145499853d6Sryan_chen #define DMA_CTRL_WRITE BIT(1) 146499853d6Sryan_chen #define DMA_CTRL_ENABLE BIT(0) 147499853d6Sryan_chen 1480a73b911SChin-Ting Kuo /* for ast2600 setting */ 1490a73b911SChin-Ting Kuo #define SPI_3B_AUTO_CLR_REG 0x1e6e2510 1500a73b911SChin-Ting Kuo #define SPI_3B_AUTO_CLR BIT(9) 1510a73b911SChin-Ting Kuo 1520a73b911SChin-Ting Kuo 153499853d6Sryan_chen /* 1540a73b911SChin-Ting Kuo * flash related info 155499853d6Sryan_chen */ 156499853d6Sryan_chen struct aspeed_spi_flash { 157499853d6Sryan_chen u8 cs; 158499853d6Sryan_chen bool init; /* Initialized when the SPI bus is 159499853d6Sryan_chen * first claimed 160499853d6Sryan_chen */ 161499853d6Sryan_chen void __iomem *ahb_base; /* AHB Window for this device */ 162499853d6Sryan_chen u32 ahb_size; /* AHB Window segment size */ 163499853d6Sryan_chen u32 ce_ctrl_user; /* CE Control Register for USER mode */ 164499853d6Sryan_chen u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 165499853d6Sryan_chen u32 iomode; 166499853d6Sryan_chen 167499853d6Sryan_chen struct spi_flash *spi; /* Associated SPI Flash device */ 168499853d6Sryan_chen }; 169499853d6Sryan_chen 170499853d6Sryan_chen struct aspeed_spi_priv { 171499853d6Sryan_chen struct aspeed_spi_regs *regs; 172499853d6Sryan_chen void __iomem *ahb_base; /* AHB Window for all flash devices */ 173499853d6Sryan_chen int new_ver; 174499853d6Sryan_chen u32 ahb_size; /* AHB Window segments size */ 175499853d6Sryan_chen 176499853d6Sryan_chen ulong hclk_rate; /* AHB clock rate */ 177499853d6Sryan_chen u32 max_hz; 178499853d6Sryan_chen u8 num_cs; 179499853d6Sryan_chen bool is_fmc; 180499853d6Sryan_chen 181499853d6Sryan_chen struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 182499853d6Sryan_chen u32 flash_count; 183499853d6Sryan_chen 184499853d6Sryan_chen u8 cmd_buf[16]; /* SPI command in progress */ 185499853d6Sryan_chen size_t cmd_len; 186499853d6Sryan_chen }; 187499853d6Sryan_chen 188499853d6Sryan_chen static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 189499853d6Sryan_chen { 190499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 191499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 192499853d6Sryan_chen u8 cs = slave_plat->cs; 193499853d6Sryan_chen 194499853d6Sryan_chen if (cs >= priv->flash_count) { 195499853d6Sryan_chen pr_err("invalid CS %u\n", cs); 196499853d6Sryan_chen return NULL; 197499853d6Sryan_chen } 198499853d6Sryan_chen 199499853d6Sryan_chen return &priv->flashes[cs]; 200499853d6Sryan_chen } 201499853d6Sryan_chen 202ac86fa8bSryan_chen static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 203499853d6Sryan_chen { 2047d182336Sryan_chen u32 hclk_rate = priv->hclk_rate; 205499853d6Sryan_chen /* HCLK/1 .. HCLK/16 */ 206499853d6Sryan_chen const u8 hclk_masks[] = { 207499853d6Sryan_chen 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 208499853d6Sryan_chen }; 2097d182336Sryan_chen u8 base_div = 0; 210f87fadc3Sryan_chen int done = 0; 211f87fadc3Sryan_chen u32 i, j = 0; 2127d182336Sryan_chen u32 hclk_div_setting = 0; 213499853d6Sryan_chen 214f87fadc3Sryan_chen for (j = 0; j < 0xf; i++) { 2157d182336Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 2167d182336Sryan_chen base_div = j * 16; 217f87fadc3Sryan_chen if (max_hz >= (hclk_rate / ((i + 1) + base_div))) { 218f87fadc3Sryan_chen 219f87fadc3Sryan_chen done = 1; 2207d182336Sryan_chen break; 2217d182336Sryan_chen } 2227d182336Sryan_chen } 223f87fadc3Sryan_chen if (done) 224f87fadc3Sryan_chen break; 2257d182336Sryan_chen } 226499853d6Sryan_chen 227f87fadc3Sryan_chen debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n", 228f87fadc3Sryan_chen hclk_rate, max_hz, j, i + 1, hclk_masks[i], hclk_rate / (i + 1 + base_div)); 2297d182336Sryan_chen 2307d182336Sryan_chen hclk_div_setting = ((j << 4) | hclk_masks[i]); 2317d182336Sryan_chen 232ac86fa8bSryan_chen return hclk_div_setting; 233ac86fa8bSryan_chen 234ac86fa8bSryan_chen } 235ac86fa8bSryan_chen 236ac86fa8bSryan_chen static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 237ac86fa8bSryan_chen { 238ac86fa8bSryan_chen u32 hclk_rate = priv->hclk_rate; 239ac86fa8bSryan_chen /* HCLK/1 .. HCLK/16 */ 240ac86fa8bSryan_chen const u8 hclk_masks[] = { 241ac86fa8bSryan_chen 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 242ac86fa8bSryan_chen }; 243d32338fdSryan_chen u32 i; 244ac86fa8bSryan_chen u32 hclk_div_setting = 0; 245ac86fa8bSryan_chen 246499853d6Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 247499853d6Sryan_chen if (max_hz >= (hclk_rate / (i + 1))) 248499853d6Sryan_chen break; 249499853d6Sryan_chen } 250499853d6Sryan_chen debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 251499853d6Sryan_chen hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 252499853d6Sryan_chen 2537d182336Sryan_chen hclk_div_setting = hclk_masks[i]; 2547d182336Sryan_chen 2557d182336Sryan_chen return hclk_div_setting; 256499853d6Sryan_chen } 257499853d6Sryan_chen 258499853d6Sryan_chen /* 259499853d6Sryan_chen * Use some address/size under the first flash device CE0 260499853d6Sryan_chen */ 261499853d6Sryan_chen static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, 262499853d6Sryan_chen u8 delay) 263499853d6Sryan_chen { 264499853d6Sryan_chen u32 flash_addr = (u32)priv->ahb_base + 0x10000; 265*beec505fSChin-Ting Kuo u32 flash_len = FLASH_CALIBRATION_LEN; 266499853d6Sryan_chen u32 dma_ctrl; 267499853d6Sryan_chen u32 checksum; 268499853d6Sryan_chen 269499853d6Sryan_chen writel(flash_addr, &priv->regs->dma_flash_addr); 270499853d6Sryan_chen writel(flash_len, &priv->regs->dma_len); 271499853d6Sryan_chen 272499853d6Sryan_chen /* 273499853d6Sryan_chen * When doing calibration, the SPI clock rate in the CE0 274499853d6Sryan_chen * Control Register and the data input delay cycles in the 275499853d6Sryan_chen * Read Timing Compensation Register are replaced by bit[11:4]. 276499853d6Sryan_chen */ 277f87fadc3Sryan_chen if(priv->new_ver) 278f87fadc3Sryan_chen dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 279f87fadc3Sryan_chen G6_TIMING_MASK(div, delay); 280f87fadc3Sryan_chen else 281499853d6Sryan_chen dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 282499853d6Sryan_chen TIMING_MASK(div, delay); 283499853d6Sryan_chen writel(dma_ctrl, &priv->regs->dma_ctrl); 284499853d6Sryan_chen while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 285499853d6Sryan_chen ; 286499853d6Sryan_chen 287499853d6Sryan_chen writel(0x0, &priv->regs->intr_ctrl); 288499853d6Sryan_chen 289499853d6Sryan_chen checksum = readl(&priv->regs->dma_checksum); 290499853d6Sryan_chen 291499853d6Sryan_chen writel(0x0, &priv->regs->dma_ctrl); 292499853d6Sryan_chen return checksum; 293499853d6Sryan_chen } 294499853d6Sryan_chen 295499853d6Sryan_chen static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, 296499853d6Sryan_chen u8 delay) 297499853d6Sryan_chen { 298499853d6Sryan_chen /* TODO(clg@kaod.org): the SPI controllers do not have the DMA 299499853d6Sryan_chen * registers. The algorithm is the same. 300499853d6Sryan_chen */ 301499853d6Sryan_chen if (!priv->is_fmc) { 302499853d6Sryan_chen pr_warn("No timing calibration support for SPI controllers"); 303499853d6Sryan_chen return 0xbadc0de; 304499853d6Sryan_chen } 305499853d6Sryan_chen 306499853d6Sryan_chen return aspeed_spi_fmc_checksum(priv, div, delay); 307499853d6Sryan_chen } 308499853d6Sryan_chen 309499853d6Sryan_chen #define TIMING_DELAY_DI_4NS BIT(3) 310499853d6Sryan_chen #define TIMING_DELAY_HCYCLE_MAX 5 311499853d6Sryan_chen 312499853d6Sryan_chen static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) 313499853d6Sryan_chen { 314499853d6Sryan_chen /* HCLK/5 .. HCLK/1 */ 315499853d6Sryan_chen const u8 hclk_masks[] = {13, 6, 14, 7, 15}; 316*beec505fSChin-Ting Kuo u32 timing_reg; 317499853d6Sryan_chen u32 checksum, gold_checksum; 318f87fadc3Sryan_chen int i, hcycle, delay_ns; 319*beec505fSChin-Ting Kuo u32 time; 320*beec505fSChin-Ting Kuo 321*beec505fSChin-Ting Kuo /* Use the ctrl setting in aspeed_spi_flash_init() to 322*beec505fSChin-Ting Kuo * implement calibration process. 323*beec505fSChin-Ting Kuo */ 324*beec505fSChin-Ting Kuo timing_reg = readl(&priv->regs->timings); 325*beec505fSChin-Ting Kuo if (timing_reg != 0) 326*beec505fSChin-Ting Kuo return 0; 327499853d6Sryan_chen 328499853d6Sryan_chen debug("Read timing calibration :\n"); 329499853d6Sryan_chen 330499853d6Sryan_chen /* Compute reference checksum at lowest freq HCLK/16 */ 331499853d6Sryan_chen gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); 332499853d6Sryan_chen 333499853d6Sryan_chen /* Increase HCLK freq */ 3347d182336Sryan_chen if (priv->new_ver) { 3357d182336Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 3367d182336Sryan_chen u32 hdiv = 5 - i; 337f87fadc3Sryan_chen u32 hshift = (hdiv - 2) * 8; 3387d182336Sryan_chen bool pass = false; 3397d182336Sryan_chen u8 delay; 340f87fadc3Sryan_chen u16 first_delay = 0; 341f87fadc3Sryan_chen u16 end_delay = 0; 342f87fadc3Sryan_chen u32 cal_tmp; 343*beec505fSChin-Ting Kuo u32 max_window_sz = 0; 344*beec505fSChin-Ting Kuo u32 cur_window_sz = 0; 345*beec505fSChin-Ting Kuo u32 tmp_delay; 346*beec505fSChin-Ting Kuo 347f87fadc3Sryan_chen debug("hdiv %d, hshift %d\n", hdiv, hshift); 3487d182336Sryan_chen if (priv->hclk_rate / hdiv > priv->max_hz) { 3497d182336Sryan_chen debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 3507d182336Sryan_chen continue; 3517d182336Sryan_chen } 3527d182336Sryan_chen 3537d182336Sryan_chen /* Try without the 4ns DI delay */ 354f87fadc3Sryan_chen hcycle = delay = 0; 355f87fadc3Sryan_chen debug("** Dealy Disable **\n"); 356f87fadc3Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], delay); 3577d182336Sryan_chen pass = (checksum == gold_checksum); 358d32338fdSryan_chen debug("HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 3597d182336Sryan_chen hdiv, hcycle, pass ? "PASS" : "FAIL"); 3607d182336Sryan_chen 3617d182336Sryan_chen /* All good for this freq */ 3627d182336Sryan_chen if (pass) 363f87fadc3Sryan_chen goto next_div; 364f87fadc3Sryan_chen 365*beec505fSChin-Ting Kuo /* Try each hcycle delay */ 366f87fadc3Sryan_chen for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 367*beec505fSChin-Ting Kuo /* Increase DI delay by the step of 0.5ns */ 368f87fadc3Sryan_chen debug("** Delay Enable : hcycle %x ** \n", hcycle); 369f87fadc3Sryan_chen for (delay_ns = 0; delay_ns < 0xf; delay_ns++) { 370*beec505fSChin-Ting Kuo tmp_delay = TIMING_DELAY_DI_4NS | hcycle | (delay_ns << 4); 371f87fadc3Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 372*beec505fSChin-Ting Kuo tmp_delay); 373f87fadc3Sryan_chen pass = (checksum == gold_checksum); 374*beec505fSChin-Ting Kuo debug("HCLK/%d, DI delay, %d HCLK cycle, %d delay_ns : %s\n", 375f87fadc3Sryan_chen hdiv, hcycle, delay_ns, pass ? "PASS" : "FAIL"); 376f87fadc3Sryan_chen 377f87fadc3Sryan_chen if (!pass) { 378f87fadc3Sryan_chen if (!first_delay) 379f87fadc3Sryan_chen continue; 380f87fadc3Sryan_chen else { 381f87fadc3Sryan_chen end_delay = (hcycle << 4) | (delay_ns); 382f87fadc3Sryan_chen end_delay = end_delay - 1; 383*beec505fSChin-Ting Kuo /* Larger window size is found */ 384*beec505fSChin-Ting Kuo if (cur_window_sz > max_window_sz) { 385*beec505fSChin-Ting Kuo max_window_sz = cur_window_sz; 386*beec505fSChin-Ting Kuo cal_tmp = (first_delay + end_delay) / 2; 387*beec505fSChin-Ting Kuo delay = TIMING_DELAY_DI_4NS | 388*beec505fSChin-Ting Kuo ((cal_tmp & 0xf) << 4) | 389*beec505fSChin-Ting Kuo (cal_tmp >> 4); 390*beec505fSChin-Ting Kuo } 391*beec505fSChin-Ting Kuo debug("find end_delay %x %d %d\n", end_delay, 392*beec505fSChin-Ting Kuo hcycle, delay_ns); 393*beec505fSChin-Ting Kuo 394*beec505fSChin-Ting Kuo first_delay = 0; 395*beec505fSChin-Ting Kuo end_delay = 0; 396*beec505fSChin-Ting Kuo cur_window_sz = 0; 397*beec505fSChin-Ting Kuo 3987d182336Sryan_chen break; 3997d182336Sryan_chen } 400f87fadc3Sryan_chen } else { 401f87fadc3Sryan_chen if (!first_delay) { 402f87fadc3Sryan_chen first_delay = (hcycle << 4) | delay_ns; 403f87fadc3Sryan_chen debug("find first_delay %x %d %d\n", first_delay, hcycle, delay_ns); 404f87fadc3Sryan_chen } 405*beec505fSChin-Ting Kuo /* Record current pass window size */ 406*beec505fSChin-Ting Kuo cur_window_sz++; 407*beec505fSChin-Ting Kuo } 408f87fadc3Sryan_chen } 409f87fadc3Sryan_chen } 4107d182336Sryan_chen 4117d182336Sryan_chen if (pass) { 412*beec505fSChin-Ting Kuo if (cur_window_sz > max_window_sz) { 413*beec505fSChin-Ting Kuo max_window_sz = cur_window_sz; 414*beec505fSChin-Ting Kuo end_delay = ((hcycle - 1) << 4) | (delay_ns - 1); 415f87fadc3Sryan_chen cal_tmp = (first_delay + end_delay) / 2; 416*beec505fSChin-Ting Kuo delay = TIMING_DELAY_DI_4NS | 417*beec505fSChin-Ting Kuo ((cal_tmp & 0xf) << 4) | 418*beec505fSChin-Ting Kuo (cal_tmp >> 4); 419f87fadc3Sryan_chen } 420f87fadc3Sryan_chen } 421f87fadc3Sryan_chen next_div: 4227d182336Sryan_chen timing_reg &= ~(0xfu << hshift); 4237d182336Sryan_chen timing_reg |= delay << hshift; 424f87fadc3Sryan_chen debug("timing_reg %x, delay %x, hshift bit %d\n",timing_reg, delay, hshift); 4257d182336Sryan_chen } 4267d182336Sryan_chen } else { 427499853d6Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 428499853d6Sryan_chen u32 hdiv = 5 - i; 429499853d6Sryan_chen u32 hshift = (hdiv - 1) << 2; 430499853d6Sryan_chen bool pass = false; 431499853d6Sryan_chen u8 delay; 432499853d6Sryan_chen 433499853d6Sryan_chen if (priv->hclk_rate / hdiv > priv->max_hz) { 434499853d6Sryan_chen debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 435499853d6Sryan_chen continue; 436499853d6Sryan_chen } 437499853d6Sryan_chen 438499853d6Sryan_chen /* Increase HCLK cycles until read succeeds */ 439499853d6Sryan_chen for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 440499853d6Sryan_chen /* Try first with a 4ns DI delay */ 441499853d6Sryan_chen delay = TIMING_DELAY_DI_4NS | hcycle; 442499853d6Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 443499853d6Sryan_chen delay); 444499853d6Sryan_chen pass = (checksum == gold_checksum); 445499853d6Sryan_chen debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 446499853d6Sryan_chen hdiv, hcycle, pass ? "PASS" : "FAIL"); 447499853d6Sryan_chen 448499853d6Sryan_chen /* Try again with more HCLK cycles */ 449499853d6Sryan_chen if (!pass) 450499853d6Sryan_chen continue; 451499853d6Sryan_chen 452499853d6Sryan_chen /* Try without the 4ns DI delay */ 453499853d6Sryan_chen delay = hcycle; 454499853d6Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 455499853d6Sryan_chen delay); 456499853d6Sryan_chen pass = (checksum == gold_checksum); 457499853d6Sryan_chen debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 458499853d6Sryan_chen hdiv, hcycle, pass ? "PASS" : "FAIL"); 459499853d6Sryan_chen 460499853d6Sryan_chen /* All good for this freq */ 461499853d6Sryan_chen if (pass) 462499853d6Sryan_chen break; 463499853d6Sryan_chen } 464499853d6Sryan_chen 465499853d6Sryan_chen if (pass) { 466499853d6Sryan_chen timing_reg &= ~(0xfu << hshift); 467499853d6Sryan_chen timing_reg |= delay << hshift; 468499853d6Sryan_chen } 469499853d6Sryan_chen } 4707d182336Sryan_chen } 471*beec505fSChin-Ting Kuo 472499853d6Sryan_chen debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 473499853d6Sryan_chen writel(timing_reg, &priv->regs->timings); 474499853d6Sryan_chen 475499853d6Sryan_chen return 0; 476499853d6Sryan_chen } 477499853d6Sryan_chen 478499853d6Sryan_chen static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 479499853d6Sryan_chen { 480*beec505fSChin-Ting Kuo int cs; 481499853d6Sryan_chen 482499853d6Sryan_chen /* 483499853d6Sryan_chen * Enable write on all flash devices as USER command mode 484499853d6Sryan_chen * requires it. 485499853d6Sryan_chen */ 486499853d6Sryan_chen setbits_le32(&priv->regs->conf, 487499853d6Sryan_chen CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 488499853d6Sryan_chen 489499853d6Sryan_chen /* 490499853d6Sryan_chen * Set safe default settings for each device. These will be 491499853d6Sryan_chen * tuned after the SPI flash devices are probed. 492499853d6Sryan_chen */ 493da83dd7eSryan_chen if (priv->new_ver) { 494499853d6Sryan_chen for (cs = 0; cs < priv->flash_count; cs++) { 495499853d6Sryan_chen struct aspeed_spi_flash *flash = &priv->flashes[cs]; 496499853d6Sryan_chen u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 497d32338fdSryan_chen u32 addr_config = 0; 498499853d6Sryan_chen switch(cs) { 499da83dd7eSryan_chen case 0: 500da83dd7eSryan_chen flash->ahb_base = cs ? (void *)G6_SEGMENT_ADDR_START(seg_addr) : 501da83dd7eSryan_chen priv->ahb_base; 502d32338fdSryan_chen debug("cs0 mem-map : %x \n", (u32)flash->ahb_base); 503da83dd7eSryan_chen break; 504499853d6Sryan_chen case 1: 5056167da3dSryan_chen flash->ahb_base = priv->flashes[0].ahb_base + 0x8000000; //cs0 + 128Mb : use 64MB 5066167da3dSryan_chen debug("cs1 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 5076167da3dSryan_chen addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 128Mb 508d32338fdSryan_chen writel(addr_config, &priv->regs->segment_addr[cs]); 509499853d6Sryan_chen break; 510499853d6Sryan_chen case 2: 5116167da3dSryan_chen flash->ahb_base = priv->flashes[0].ahb_base + 0xc000000; //cs0 + 192Mb : use 64MB 5126167da3dSryan_chen debug("cs2 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 5136167da3dSryan_chen addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 128Mb 5146167da3dSryan_chen writel(addr_config, &priv->regs->segment_addr[cs]); 515499853d6Sryan_chen break; 516499853d6Sryan_chen } 517da83dd7eSryan_chen flash->cs = cs; 518da83dd7eSryan_chen flash->ce_ctrl_user = CE_CTRL_USERMODE; 519da83dd7eSryan_chen flash->ce_ctrl_fread = CE_CTRL_READMODE; 520499853d6Sryan_chen } 521da83dd7eSryan_chen } else { 522da83dd7eSryan_chen for (cs = 0; cs < priv->flash_count; cs++) { 523da83dd7eSryan_chen struct aspeed_spi_flash *flash = &priv->flashes[cs]; 524da83dd7eSryan_chen u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 525499853d6Sryan_chen /* 526499853d6Sryan_chen * The start address of the AHB window of CE0 is 527499853d6Sryan_chen * read-only and is the same as the address of the 528499853d6Sryan_chen * overall AHB window of the controller for all flash 529499853d6Sryan_chen * devices. 530499853d6Sryan_chen */ 531499853d6Sryan_chen flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 532499853d6Sryan_chen priv->ahb_base; 533499853d6Sryan_chen 534499853d6Sryan_chen flash->cs = cs; 535499853d6Sryan_chen flash->ce_ctrl_user = CE_CTRL_USERMODE; 536499853d6Sryan_chen flash->ce_ctrl_fread = CE_CTRL_READMODE; 537499853d6Sryan_chen } 538da83dd7eSryan_chen } 539499853d6Sryan_chen return 0; 540499853d6Sryan_chen } 541499853d6Sryan_chen 542499853d6Sryan_chen static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 543499853d6Sryan_chen size_t len) 544499853d6Sryan_chen { 545499853d6Sryan_chen size_t offset = 0; 546499853d6Sryan_chen 547499853d6Sryan_chen if (!((uintptr_t)buf % 4)) { 548499853d6Sryan_chen readsl(ahb_base, buf, len >> 2); 549499853d6Sryan_chen offset = len & ~0x3; 550499853d6Sryan_chen len -= offset; 551499853d6Sryan_chen } 552499853d6Sryan_chen readsb(ahb_base, (u8 *)buf + offset, len); 553499853d6Sryan_chen 554499853d6Sryan_chen return 0; 555499853d6Sryan_chen } 556499853d6Sryan_chen 557499853d6Sryan_chen static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 558499853d6Sryan_chen size_t len) 559499853d6Sryan_chen { 560499853d6Sryan_chen size_t offset = 0; 561499853d6Sryan_chen 562499853d6Sryan_chen if (!((uintptr_t)buf % 4)) { 563499853d6Sryan_chen writesl(ahb_base, buf, len >> 2); 564499853d6Sryan_chen offset = len & ~0x3; 565499853d6Sryan_chen len -= offset; 566499853d6Sryan_chen } 567499853d6Sryan_chen writesb(ahb_base, (u8 *)buf + offset, len); 568499853d6Sryan_chen 569499853d6Sryan_chen return 0; 570499853d6Sryan_chen } 571499853d6Sryan_chen 572499853d6Sryan_chen static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 573499853d6Sryan_chen struct aspeed_spi_flash *flash) 574499853d6Sryan_chen { 575499853d6Sryan_chen u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 576499853d6Sryan_chen 577499853d6Sryan_chen /* Deselect CS and set USER command mode */ 578499853d6Sryan_chen writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 579499853d6Sryan_chen 580499853d6Sryan_chen /* Select CS */ 581499853d6Sryan_chen clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 582499853d6Sryan_chen } 583499853d6Sryan_chen 584499853d6Sryan_chen static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 585499853d6Sryan_chen struct aspeed_spi_flash *flash) 586499853d6Sryan_chen { 587499853d6Sryan_chen /* Deselect CS first */ 588499853d6Sryan_chen setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 589499853d6Sryan_chen 590499853d6Sryan_chen /* Restore default command mode */ 591499853d6Sryan_chen writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 592499853d6Sryan_chen } 593499853d6Sryan_chen 594499853d6Sryan_chen static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 595499853d6Sryan_chen struct aspeed_spi_flash *flash, 596499853d6Sryan_chen u8 opcode, u8 *read_buf, int len) 597499853d6Sryan_chen { 598499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 599499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 600499853d6Sryan_chen aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 601499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 602499853d6Sryan_chen 603499853d6Sryan_chen return 0; 604499853d6Sryan_chen } 605499853d6Sryan_chen 606499853d6Sryan_chen static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 607499853d6Sryan_chen struct aspeed_spi_flash *flash, 608499853d6Sryan_chen u8 opcode, const u8 *write_buf, int len) 609499853d6Sryan_chen { 610499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 611499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 612499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 613499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 614499853d6Sryan_chen 615528cd552Sryan_chen debug("=== write opcode [%x] ==== \n", opcode); 616499853d6Sryan_chen switch(opcode) { 617499853d6Sryan_chen case SPINOR_OP_EN4B: 6180a73b911SChin-Ting Kuo /* For ast2600, if 2 chips ABR mode is enabled, 6190a73b911SChin-Ting Kuo * turn on 3B mode auto clear in order to avoid 6200a73b911SChin-Ting Kuo * the scenario where spi controller is at 4B mode 6210a73b911SChin-Ting Kuo * and flash site is at 3B mode after 3rd switch. 6220a73b911SChin-Ting Kuo */ 6230a73b911SChin-Ting Kuo if (priv->new_ver == 1 && (readl(SPI_3B_AUTO_CLR_REG) & SPI_3B_AUTO_CLR)) 6240a73b911SChin-Ting Kuo writel(readl(&priv->regs->soft_rst_cmd_ctrl) | SOFT_RST_CMD_EN, 6250a73b911SChin-Ting Kuo &priv->regs->soft_rst_cmd_ctrl); 6260a73b911SChin-Ting Kuo 627499853d6Sryan_chen writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); 628499853d6Sryan_chen break; 629499853d6Sryan_chen case SPINOR_OP_EX4B: 630499853d6Sryan_chen writel(readl(&priv->regs->ctrl) & ~BIT(flash->cs), &priv->regs->ctrl); 631499853d6Sryan_chen break; 632499853d6Sryan_chen } 633499853d6Sryan_chen return 0; 634499853d6Sryan_chen } 635499853d6Sryan_chen 636499853d6Sryan_chen static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 637499853d6Sryan_chen struct aspeed_spi_flash *flash, 638499853d6Sryan_chen const u8 *cmdbuf, unsigned int cmdlen) 639499853d6Sryan_chen { 640499853d6Sryan_chen int i; 641499853d6Sryan_chen u8 byte0 = 0x0; 642499853d6Sryan_chen u8 addrlen = cmdlen - 1; 643499853d6Sryan_chen 644499853d6Sryan_chen /* First, send the opcode */ 645499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 646499853d6Sryan_chen 647528cd552Sryan_chen if(flash->iomode == CE_CTRL_IO_QUAD_ADDR_DATA) 648528cd552Sryan_chen writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); 649528cd552Sryan_chen 650499853d6Sryan_chen /* 651499853d6Sryan_chen * The controller is configured for 4BYTE address mode. Fix 652499853d6Sryan_chen * the address width and send an extra byte if the SPI Flash 653499853d6Sryan_chen * layer uses 3 bytes addresses. 654499853d6Sryan_chen */ 655499853d6Sryan_chen if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) 656499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); 657499853d6Sryan_chen 658499853d6Sryan_chen /* Then the address */ 659499853d6Sryan_chen for (i = 1 ; i < cmdlen; i++) 660499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 661499853d6Sryan_chen } 662499853d6Sryan_chen 663499853d6Sryan_chen static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 664499853d6Sryan_chen struct aspeed_spi_flash *flash, 665499853d6Sryan_chen unsigned int cmdlen, const u8 *cmdbuf, 666499853d6Sryan_chen unsigned int len, u8 *read_buf) 667499853d6Sryan_chen { 668499853d6Sryan_chen u8 dummy = 0xff; 669499853d6Sryan_chen int i; 670499853d6Sryan_chen 671499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 672499853d6Sryan_chen 673499853d6Sryan_chen /* cmd buffer = cmd + addr + dummies */ 674499853d6Sryan_chen aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 675499853d6Sryan_chen cmdlen - (flash->spi->read_dummy/8)); 676499853d6Sryan_chen 677499853d6Sryan_chen for (i = 0 ; i < (flash->spi->read_dummy/8); i++) 678499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 679499853d6Sryan_chen 680499853d6Sryan_chen if (flash->iomode) { 681499853d6Sryan_chen clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 682499853d6Sryan_chen CE_CTRL_IO_MODE_MASK); 683499853d6Sryan_chen setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->iomode); 684499853d6Sryan_chen } 685499853d6Sryan_chen 686499853d6Sryan_chen aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 687499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 688499853d6Sryan_chen 689499853d6Sryan_chen return 0; 690499853d6Sryan_chen } 691499853d6Sryan_chen 692499853d6Sryan_chen static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 693499853d6Sryan_chen struct aspeed_spi_flash *flash, 694499853d6Sryan_chen unsigned int cmdlen, const u8 *cmdbuf, 695499853d6Sryan_chen unsigned int len, const u8 *write_buf) 696499853d6Sryan_chen { 697499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 698499853d6Sryan_chen 69976e3c7a9Sryan_chen /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ 700499853d6Sryan_chen aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); 70176e3c7a9Sryan_chen 70276e3c7a9Sryan_chen /* data will use io mode */ 70376e3c7a9Sryan_chen if(flash->iomode == CE_CTRL_IO_QUAD_DATA) 70476e3c7a9Sryan_chen writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); 70576e3c7a9Sryan_chen 706499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 707499853d6Sryan_chen 708499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 709499853d6Sryan_chen 710499853d6Sryan_chen return 0; 711499853d6Sryan_chen } 712499853d6Sryan_chen 713499853d6Sryan_chen static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 714499853d6Sryan_chen const u8 *cmdbuf, unsigned int cmdlen) 715499853d6Sryan_chen { 716499853d6Sryan_chen u8 addrlen = cmdlen - 1; 717499853d6Sryan_chen u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 718499853d6Sryan_chen 719499853d6Sryan_chen /* 720499853d6Sryan_chen * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 721499853d6Sryan_chen * change one day 722499853d6Sryan_chen */ 723499853d6Sryan_chen if (addrlen == 4) 724499853d6Sryan_chen addr = (addr << 8) | cmdbuf[4]; 725499853d6Sryan_chen 726499853d6Sryan_chen return addr; 727499853d6Sryan_chen } 728499853d6Sryan_chen 729499853d6Sryan_chen /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 730499853d6Sryan_chen static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 731499853d6Sryan_chen struct aspeed_spi_flash *flash, 732499853d6Sryan_chen unsigned int cmdlen, const u8 *cmdbuf, 733499853d6Sryan_chen unsigned int len, u8 *read_buf) 734499853d6Sryan_chen { 735499853d6Sryan_chen /* cmd buffer = cmd + addr + dummies */ 736499853d6Sryan_chen u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 737499853d6Sryan_chen cmdlen - (flash->spi->read_dummy/8)); 738499853d6Sryan_chen 739499853d6Sryan_chen /* 740499853d6Sryan_chen * Switch to USER command mode if the AHB window configured 741499853d6Sryan_chen * for the device is too small for the read operation 742499853d6Sryan_chen */ 743499853d6Sryan_chen if (offset + len >= flash->ahb_size) { 744499853d6Sryan_chen return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 745499853d6Sryan_chen len, read_buf); 746499853d6Sryan_chen } 747499853d6Sryan_chen 748499853d6Sryan_chen memcpy_fromio(read_buf, flash->ahb_base + offset, len); 749499853d6Sryan_chen 750499853d6Sryan_chen return 0; 751499853d6Sryan_chen } 752499853d6Sryan_chen 753499853d6Sryan_chen static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 754499853d6Sryan_chen const void *dout, void *din, unsigned long flags) 755499853d6Sryan_chen { 756499853d6Sryan_chen struct udevice *bus = dev->parent; 757499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(bus); 758499853d6Sryan_chen struct aspeed_spi_flash *flash; 759499853d6Sryan_chen u8 *cmd_buf = priv->cmd_buf; 760499853d6Sryan_chen size_t data_bytes; 761499853d6Sryan_chen int err = 0; 762499853d6Sryan_chen 763499853d6Sryan_chen flash = aspeed_spi_get_flash(dev); 764499853d6Sryan_chen if (!flash) 765499853d6Sryan_chen return -ENXIO; 766499853d6Sryan_chen 767499853d6Sryan_chen if (flags & SPI_XFER_BEGIN) { 768499853d6Sryan_chen /* save command in progress */ 769499853d6Sryan_chen priv->cmd_len = bitlen / 8; 770499853d6Sryan_chen memcpy(cmd_buf, dout, priv->cmd_len); 771499853d6Sryan_chen } 772499853d6Sryan_chen 773499853d6Sryan_chen if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 774499853d6Sryan_chen /* if start and end bit are set, the data bytes is 0. */ 775499853d6Sryan_chen data_bytes = 0; 776499853d6Sryan_chen } else { 777499853d6Sryan_chen data_bytes = bitlen / 8; 778499853d6Sryan_chen } 779499853d6Sryan_chen 780499853d6Sryan_chen debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 781499853d6Sryan_chen din ? "read" : "write", priv->cmd_len, data_bytes); 782499853d6Sryan_chen 783499853d6Sryan_chen if ((flags & SPI_XFER_END) || flags == 0) { 784499853d6Sryan_chen if (priv->cmd_len == 0) { 785499853d6Sryan_chen pr_err("No command is progress !\n"); 786499853d6Sryan_chen return -1; 787499853d6Sryan_chen } 788499853d6Sryan_chen 789499853d6Sryan_chen if (din && data_bytes) { 790499853d6Sryan_chen if (priv->cmd_len == 1) 791499853d6Sryan_chen err = aspeed_spi_read_reg(priv, flash, 792499853d6Sryan_chen cmd_buf[0], 793499853d6Sryan_chen din, data_bytes); 794499853d6Sryan_chen else 795499853d6Sryan_chen err = aspeed_spi_read(priv, flash, 796499853d6Sryan_chen priv->cmd_len, 797499853d6Sryan_chen cmd_buf, data_bytes, 798499853d6Sryan_chen din); 799499853d6Sryan_chen } else if (dout) { 800499853d6Sryan_chen if (priv->cmd_len == 1) 801499853d6Sryan_chen err = aspeed_spi_write_reg(priv, flash, 802499853d6Sryan_chen cmd_buf[0], 803499853d6Sryan_chen dout, data_bytes); 804499853d6Sryan_chen else 805499853d6Sryan_chen err = aspeed_spi_write_user(priv, flash, 806499853d6Sryan_chen priv->cmd_len, 807499853d6Sryan_chen cmd_buf, data_bytes, 808499853d6Sryan_chen dout); 809499853d6Sryan_chen } 810499853d6Sryan_chen 811499853d6Sryan_chen if (flags & SPI_XFER_END) { 812499853d6Sryan_chen /* clear command */ 813499853d6Sryan_chen memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 814499853d6Sryan_chen priv->cmd_len = 0; 815499853d6Sryan_chen } 816499853d6Sryan_chen } 817499853d6Sryan_chen 818499853d6Sryan_chen return err; 819499853d6Sryan_chen } 820499853d6Sryan_chen 821499853d6Sryan_chen static int aspeed_spi_child_pre_probe(struct udevice *dev) 822499853d6Sryan_chen { 823499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 824499853d6Sryan_chen 825499853d6Sryan_chen debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 826499853d6Sryan_chen slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 827499853d6Sryan_chen 828499853d6Sryan_chen if (!aspeed_spi_get_flash(dev)) 829499853d6Sryan_chen return -ENXIO; 830499853d6Sryan_chen 831499853d6Sryan_chen return 0; 832499853d6Sryan_chen } 833499853d6Sryan_chen 834499853d6Sryan_chen /* 835499853d6Sryan_chen * It is possible to automatically define a contiguous address space 836499853d6Sryan_chen * on top of all CEs in the AHB window of the controller but it would 837499853d6Sryan_chen * require much more work. Let's start with a simple mapping scheme 838499853d6Sryan_chen * which should work fine for a single flash device. 839499853d6Sryan_chen * 840499853d6Sryan_chen * More complex schemes should probably be defined with the device 841499853d6Sryan_chen * tree. 842499853d6Sryan_chen */ 843499853d6Sryan_chen static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 844499853d6Sryan_chen struct aspeed_spi_flash *flash) 845499853d6Sryan_chen { 846499853d6Sryan_chen u32 seg_addr; 847499853d6Sryan_chen 848499853d6Sryan_chen /* could be configured through the device tree */ 849499853d6Sryan_chen flash->ahb_size = flash->spi->size; 850499853d6Sryan_chen 851da83dd7eSryan_chen if (priv->new_ver) { 852da83dd7eSryan_chen seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 853da83dd7eSryan_chen (u32)flash->ahb_base + flash->ahb_size); 854da83dd7eSryan_chen } else { 855499853d6Sryan_chen seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 856499853d6Sryan_chen (u32)flash->ahb_base + flash->ahb_size); 857da83dd7eSryan_chen } 858499853d6Sryan_chen writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 859499853d6Sryan_chen 860499853d6Sryan_chen return 0; 861499853d6Sryan_chen } 862499853d6Sryan_chen 863499853d6Sryan_chen static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 864499853d6Sryan_chen struct aspeed_spi_flash *flash, 865499853d6Sryan_chen struct udevice *dev) 866499853d6Sryan_chen { 867*beec505fSChin-Ting Kuo int ret; 868499853d6Sryan_chen struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 869499853d6Sryan_chen struct spi_slave *slave = dev_get_parent_priv(dev); 870499853d6Sryan_chen u32 read_hclk; 871499853d6Sryan_chen 872*beec505fSChin-Ting Kuo 873499853d6Sryan_chen /* 874499853d6Sryan_chen * The SPI flash device slave should not change, so initialize 875499853d6Sryan_chen * it only once. 876499853d6Sryan_chen */ 877499853d6Sryan_chen if (flash->init) 878499853d6Sryan_chen return 0; 879499853d6Sryan_chen 880499853d6Sryan_chen /* 881499853d6Sryan_chen * The flash device has not been probed yet. Initial transfers 882499853d6Sryan_chen * to read the JEDEC of the device will use the initial 883499853d6Sryan_chen * default settings of the registers. 884499853d6Sryan_chen */ 885499853d6Sryan_chen if (!spi_flash->name) 886499853d6Sryan_chen return 0; 887499853d6Sryan_chen 888499853d6Sryan_chen debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " 889499853d6Sryan_chen "cmds [ erase:%x read=%x write:%x ] dummy:%d\n", 890499853d6Sryan_chen flash->cs, 891499853d6Sryan_chen spi_flash->name, spi_flash->flags, spi_flash->size, 892499853d6Sryan_chen spi_flash->page_size, spi_flash->sector_size, 893499853d6Sryan_chen spi_flash->erase_size, spi_flash->erase_opcode, 894499853d6Sryan_chen spi_flash->read_opcode, spi_flash->program_opcode, 895499853d6Sryan_chen spi_flash->read_dummy); 896499853d6Sryan_chen 897499853d6Sryan_chen flash->spi = spi_flash; 898499853d6Sryan_chen 8997d182336Sryan_chen flash->ce_ctrl_user = CE_CTRL_USERMODE; 900499853d6Sryan_chen 901ac86fa8bSryan_chen if(priv->new_ver) 902ac86fa8bSryan_chen read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 903ac86fa8bSryan_chen else 9047d182336Sryan_chen read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 905499853d6Sryan_chen 906528cd552Sryan_chen switch(flash->spi->read_opcode) { 907528cd552Sryan_chen case SPINOR_OP_READ_1_1_2: 908528cd552Sryan_chen case SPINOR_OP_READ_1_1_2_4B: 909499853d6Sryan_chen flash->iomode = CE_CTRL_IO_DUAL_DATA; 910528cd552Sryan_chen break; 911528cd552Sryan_chen case SPINOR_OP_READ_1_1_4: 912528cd552Sryan_chen case SPINOR_OP_READ_1_1_4_4B: 913d32338fdSryan_chen flash->iomode = CE_CTRL_IO_QUAD_DATA; 914528cd552Sryan_chen break; 915528cd552Sryan_chen case SPINOR_OP_READ_1_4_4: 916528cd552Sryan_chen case SPINOR_OP_READ_1_4_4_4B: 917528cd552Sryan_chen flash->iomode = CE_CTRL_IO_QUAD_ADDR_DATA; 918528cd552Sryan_chen printf("need modify dummy for 3 bytes"); 919528cd552Sryan_chen break; 920499853d6Sryan_chen } 921499853d6Sryan_chen 922d32338fdSryan_chen if(priv->new_ver) { 9237d182336Sryan_chen flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 9247d182336Sryan_chen flash->iomode | 9257d182336Sryan_chen CE_CTRL_CMD(flash->spi->read_opcode) | 9267d182336Sryan_chen CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 9277d182336Sryan_chen CE_CTRL_FREADMODE; 928d32338fdSryan_chen } else { 929499853d6Sryan_chen flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 930499853d6Sryan_chen flash->iomode | 931499853d6Sryan_chen CE_CTRL_CMD(flash->spi->read_opcode) | 932499853d6Sryan_chen CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 933499853d6Sryan_chen CE_CTRL_FREADMODE; 934d32338fdSryan_chen } 935499853d6Sryan_chen 936499853d6Sryan_chen debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 937499853d6Sryan_chen flash->ce_ctrl_user, flash->ce_ctrl_fread); 938499853d6Sryan_chen 939499853d6Sryan_chen /* Set the CE Control Register default (FAST READ) */ 940499853d6Sryan_chen writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 941499853d6Sryan_chen 942499853d6Sryan_chen /* Set Address Segment Register for direct AHB accesses */ 943499853d6Sryan_chen aspeed_spi_flash_set_segment(priv, flash); 944499853d6Sryan_chen 945*beec505fSChin-Ting Kuo /* 946*beec505fSChin-Ting Kuo * Set the Read Timing Compensation Register. This setting 947*beec505fSChin-Ting Kuo * applies to all devices. 948*beec505fSChin-Ting Kuo */ 949*beec505fSChin-Ting Kuo ret = aspeed_spi_timing_calibration(priv); 950*beec505fSChin-Ting Kuo if (ret != 0) 951*beec505fSChin-Ting Kuo return ret; 952*beec505fSChin-Ting Kuo 953499853d6Sryan_chen /* All done */ 954499853d6Sryan_chen flash->init = true; 955499853d6Sryan_chen 956499853d6Sryan_chen return 0; 957499853d6Sryan_chen } 958499853d6Sryan_chen 959499853d6Sryan_chen static int aspeed_spi_claim_bus(struct udevice *dev) 960499853d6Sryan_chen { 961499853d6Sryan_chen struct udevice *bus = dev->parent; 962499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(bus); 963499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 964499853d6Sryan_chen struct aspeed_spi_flash *flash; 965499853d6Sryan_chen 966499853d6Sryan_chen debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 967499853d6Sryan_chen 968499853d6Sryan_chen flash = aspeed_spi_get_flash(dev); 969499853d6Sryan_chen if (!flash) 970499853d6Sryan_chen return -ENODEV; 971499853d6Sryan_chen 972499853d6Sryan_chen return aspeed_spi_flash_init(priv, flash, dev); 973499853d6Sryan_chen } 974499853d6Sryan_chen 975499853d6Sryan_chen static int aspeed_spi_release_bus(struct udevice *dev) 976499853d6Sryan_chen { 977499853d6Sryan_chen struct udevice *bus = dev->parent; 978499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 979499853d6Sryan_chen 980499853d6Sryan_chen debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 981499853d6Sryan_chen 982499853d6Sryan_chen if (!aspeed_spi_get_flash(dev)) 983499853d6Sryan_chen return -ENODEV; 984499853d6Sryan_chen 985499853d6Sryan_chen return 0; 986499853d6Sryan_chen } 987499853d6Sryan_chen 988499853d6Sryan_chen static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 989499853d6Sryan_chen { 990499853d6Sryan_chen debug("%s: setting mode to %x\n", bus->name, mode); 991499853d6Sryan_chen 992499853d6Sryan_chen if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 99376e3c7a9Sryan_chen #ifndef CONFIG_ASPEED_AST2600 994499853d6Sryan_chen pr_err("%s invalid QUAD IO mode\n", bus->name); 995499853d6Sryan_chen return -EINVAL; 99676e3c7a9Sryan_chen #endif 997499853d6Sryan_chen } 998499853d6Sryan_chen 999499853d6Sryan_chen /* The CE Control Register is set in claim_bus() */ 1000499853d6Sryan_chen return 0; 1001499853d6Sryan_chen } 1002499853d6Sryan_chen 1003499853d6Sryan_chen static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 1004499853d6Sryan_chen { 1005499853d6Sryan_chen debug("%s: setting speed to %u\n", bus->name, hz); 1006499853d6Sryan_chen 1007499853d6Sryan_chen /* The CE Control Register is set in claim_bus() */ 1008499853d6Sryan_chen return 0; 1009499853d6Sryan_chen } 1010499853d6Sryan_chen 1011499853d6Sryan_chen static int aspeed_spi_count_flash_devices(struct udevice *bus) 1012499853d6Sryan_chen { 1013499853d6Sryan_chen ofnode node; 1014499853d6Sryan_chen int count = 0; 1015499853d6Sryan_chen 1016499853d6Sryan_chen dev_for_each_subnode(node, bus) { 1017499853d6Sryan_chen if (ofnode_is_available(node) && 1018499853d6Sryan_chen ofnode_device_is_compatible(node, "spi-flash")) 1019499853d6Sryan_chen count++; 1020499853d6Sryan_chen } 1021499853d6Sryan_chen 1022499853d6Sryan_chen return count; 1023499853d6Sryan_chen } 1024499853d6Sryan_chen 1025499853d6Sryan_chen static int aspeed_spi_bind(struct udevice *bus) 1026499853d6Sryan_chen { 1027499853d6Sryan_chen debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 1028499853d6Sryan_chen bus->seq); 1029499853d6Sryan_chen 1030499853d6Sryan_chen return 0; 1031499853d6Sryan_chen } 1032499853d6Sryan_chen 1033499853d6Sryan_chen static int aspeed_spi_probe(struct udevice *bus) 1034499853d6Sryan_chen { 1035499853d6Sryan_chen struct resource res_regs, res_ahb; 1036499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(bus); 1037499853d6Sryan_chen struct clk hclk; 1038499853d6Sryan_chen int ret; 1039499853d6Sryan_chen 1040499853d6Sryan_chen ret = dev_read_resource(bus, 0, &res_regs); 1041499853d6Sryan_chen if (ret < 0) 1042499853d6Sryan_chen return ret; 1043499853d6Sryan_chen 1044499853d6Sryan_chen priv->regs = (void __iomem *)res_regs.start; 1045499853d6Sryan_chen 1046499853d6Sryan_chen ret = dev_read_resource(bus, 1, &res_ahb); 1047499853d6Sryan_chen if (ret < 0) 1048499853d6Sryan_chen return ret; 1049499853d6Sryan_chen 1050499853d6Sryan_chen priv->ahb_base = (void __iomem *)res_ahb.start; 1051499853d6Sryan_chen priv->ahb_size = res_ahb.end - res_ahb.start; 1052499853d6Sryan_chen 1053499853d6Sryan_chen ret = clk_get_by_index(bus, 0, &hclk); 1054499853d6Sryan_chen if (ret < 0) { 1055499853d6Sryan_chen pr_err("%s could not get clock: %d\n", bus->name, ret); 1056499853d6Sryan_chen return ret; 1057499853d6Sryan_chen } 1058499853d6Sryan_chen 1059499853d6Sryan_chen priv->hclk_rate = clk_get_rate(&hclk); 1060499853d6Sryan_chen clk_free(&hclk); 1061499853d6Sryan_chen 1062499853d6Sryan_chen priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1063499853d6Sryan_chen 100000000); 1064499853d6Sryan_chen 1065499853d6Sryan_chen priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 1066499853d6Sryan_chen 1067499853d6Sryan_chen priv->flash_count = aspeed_spi_count_flash_devices(bus); 1068499853d6Sryan_chen if (priv->flash_count > priv->num_cs) { 1069499853d6Sryan_chen pr_err("%s has too many flash devices: %d\n", bus->name, 1070499853d6Sryan_chen priv->flash_count); 1071499853d6Sryan_chen return -EINVAL; 1072499853d6Sryan_chen } 1073499853d6Sryan_chen 1074499853d6Sryan_chen if (!priv->flash_count) { 1075499853d6Sryan_chen pr_err("%s has no flash devices ?!\n", bus->name); 1076499853d6Sryan_chen return -ENODEV; 1077499853d6Sryan_chen } 1078499853d6Sryan_chen 10797d182336Sryan_chen if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 1080f87fadc3Sryan_chen device_is_compatible(bus, "aspeed,ast2600-spi")) { 1081499853d6Sryan_chen priv->new_ver = 1; 1082499853d6Sryan_chen } 1083499853d6Sryan_chen 1084499853d6Sryan_chen /* 1085499853d6Sryan_chen * There are some slight differences between the FMC and the 1086499853d6Sryan_chen * SPI controllers 1087499853d6Sryan_chen */ 1088499853d6Sryan_chen priv->is_fmc = dev_get_driver_data(bus); 1089499853d6Sryan_chen 1090499853d6Sryan_chen ret = aspeed_spi_controller_init(priv); 1091499853d6Sryan_chen if (ret) 1092499853d6Sryan_chen return ret; 1093499853d6Sryan_chen 1094499853d6Sryan_chen debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", 1095499853d6Sryan_chen bus->name, priv->regs, priv->ahb_base, priv->max_hz, 1096499853d6Sryan_chen priv->flash_count, bus->seq); 1097499853d6Sryan_chen 1098499853d6Sryan_chen return 0; 1099499853d6Sryan_chen } 1100499853d6Sryan_chen 1101499853d6Sryan_chen static const struct dm_spi_ops aspeed_spi_ops = { 1102499853d6Sryan_chen .claim_bus = aspeed_spi_claim_bus, 1103499853d6Sryan_chen .release_bus = aspeed_spi_release_bus, 1104499853d6Sryan_chen .set_mode = aspeed_spi_set_mode, 1105499853d6Sryan_chen .set_speed = aspeed_spi_set_speed, 1106499853d6Sryan_chen .xfer = aspeed_spi_xfer, 1107499853d6Sryan_chen }; 1108499853d6Sryan_chen 1109499853d6Sryan_chen static const struct udevice_id aspeed_spi_ids[] = { 1110499853d6Sryan_chen { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1111499853d6Sryan_chen { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1112499853d6Sryan_chen { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1113499853d6Sryan_chen { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1114499853d6Sryan_chen { } 1115499853d6Sryan_chen }; 1116499853d6Sryan_chen 1117499853d6Sryan_chen U_BOOT_DRIVER(aspeed_spi) = { 1118499853d6Sryan_chen .name = "aspeed_spi", 1119499853d6Sryan_chen .id = UCLASS_SPI, 1120499853d6Sryan_chen .of_match = aspeed_spi_ids, 1121499853d6Sryan_chen .ops = &aspeed_spi_ops, 1122499853d6Sryan_chen .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1123499853d6Sryan_chen .child_pre_probe = aspeed_spi_child_pre_probe, 1124499853d6Sryan_chen .bind = aspeed_spi_bind, 1125499853d6Sryan_chen .probe = aspeed_spi_probe, 1126499853d6Sryan_chen }; 1127