1499853d6Sryan_chen // SPDX-License-Identifier: GPL-2.0+ 2499853d6Sryan_chen /* 3499853d6Sryan_chen * ASPEED AST2500 FMC/SPI Controller driver 4499853d6Sryan_chen * 5499853d6Sryan_chen * Copyright (c) 2015-2018, IBM Corporation. 6499853d6Sryan_chen */ 7499853d6Sryan_chen 8499853d6Sryan_chen #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9499853d6Sryan_chen 10499853d6Sryan_chen #include <common.h> 11499853d6Sryan_chen #include <clk.h> 12499853d6Sryan_chen #include <dm.h> 13499853d6Sryan_chen #include <spi.h> 14499853d6Sryan_chen #include <spi_flash.h> 15499853d6Sryan_chen #include <asm/io.h> 16499853d6Sryan_chen #include <linux/ioport.h> 17499853d6Sryan_chen 18499853d6Sryan_chen #define ASPEED_SPI_MAX_CS 3 19499853d6Sryan_chen 20499853d6Sryan_chen struct aspeed_spi_regs { 21499853d6Sryan_chen u32 conf; /* 0x00 CE Type Setting */ 22499853d6Sryan_chen u32 ctrl; /* 0x04 Control */ 23499853d6Sryan_chen u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 24499853d6Sryan_chen u32 cmd_ctrl; /* 0x0c Command Control */ 25499853d6Sryan_chen u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 26499853d6Sryan_chen u32 _reserved0[5]; /* .. */ 27499853d6Sryan_chen u32 segment_addr[ASPEED_SPI_MAX_CS]; 28499853d6Sryan_chen /* 0x30 .. 0x38 Segment Address */ 29*0a73b911SChin-Ting Kuo u32 _reserved1[5]; /* .. */ 30*0a73b911SChin-Ting Kuo u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ 31*0a73b911SChin-Ting Kuo u32 _reserved2[11]; /* .. */ 32499853d6Sryan_chen u32 dma_ctrl; /* 0x80 DMA Control/Status */ 33499853d6Sryan_chen u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 34499853d6Sryan_chen u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 35499853d6Sryan_chen u32 dma_len; /* 0x8c DMA Length Register */ 36499853d6Sryan_chen u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 37499853d6Sryan_chen u32 timings; /* 0x94 Read Timing Compensation */ 38499853d6Sryan_chen 39499853d6Sryan_chen /* not used */ 40499853d6Sryan_chen u32 soft_strap_status; /* 0x9c Software Strap Status */ 41499853d6Sryan_chen u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 42499853d6Sryan_chen u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 43499853d6Sryan_chen u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 44499853d6Sryan_chen u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 45499853d6Sryan_chen u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 46499853d6Sryan_chen }; 47499853d6Sryan_chen 48499853d6Sryan_chen /* CE Type Setting Register */ 49499853d6Sryan_chen #define CONF_ENABLE_W2 BIT(18) 50499853d6Sryan_chen #define CONF_ENABLE_W1 BIT(17) 51499853d6Sryan_chen #define CONF_ENABLE_W0 BIT(16) 52499853d6Sryan_chen #define CONF_FLASH_TYPE2 4 53499853d6Sryan_chen #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 54499853d6Sryan_chen #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 55499853d6Sryan_chen #define CONF_FLASH_TYPE_NOR 0x0 56499853d6Sryan_chen #define CONF_FLASH_TYPE_SPI 0x2 57499853d6Sryan_chen 58499853d6Sryan_chen /* CE Control Register */ 59499853d6Sryan_chen #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 60499853d6Sryan_chen #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 61499853d6Sryan_chen #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 62499853d6Sryan_chen 63499853d6Sryan_chen /* Interrupt Control and Status Register */ 64499853d6Sryan_chen #define INTR_CTRL_DMA_STATUS BIT(11) 65499853d6Sryan_chen #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 66499853d6Sryan_chen #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 67499853d6Sryan_chen #define INTR_CTRL_DMA_EN BIT(3) 68499853d6Sryan_chen #define INTR_CTRL_CMD_ABORT_EN BIT(2) 69499853d6Sryan_chen #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 70499853d6Sryan_chen 71499853d6Sryan_chen /* CEx Control Register */ 72499853d6Sryan_chen #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 7376e3c7a9Sryan_chen #define CE_CTRL_IO_QPI_DATA BIT(31) 74499853d6Sryan_chen #define CE_CTRL_IO_DUAL_DATA BIT(29) 75499853d6Sryan_chen #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 76499853d6Sryan_chen #define CE_CTRL_IO_QUAD_DATA BIT(30) 77499853d6Sryan_chen #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 78499853d6Sryan_chen #define CE_CTRL_CMD_SHIFT 16 79499853d6Sryan_chen #define CE_CTRL_CMD_MASK 0xff 80499853d6Sryan_chen #define CE_CTRL_CMD(cmd) \ 81499853d6Sryan_chen (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 82499853d6Sryan_chen #define CE_CTRL_DUMMY_HIGH_SHIFT 14 83499853d6Sryan_chen #define CE_CTRL_DUMMY_HIGH_MASK 0x1 84499853d6Sryan_chen #define CE_CTRL_CLOCK_FREQ_SHIFT 8 85499853d6Sryan_chen #define CE_CTRL_CLOCK_FREQ_MASK 0xf 86499853d6Sryan_chen #define CE_CTRL_CLOCK_FREQ(div) \ 87499853d6Sryan_chen (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 887d182336Sryan_chen #define CE_G6_CTRL_CLOCK_FREQ(div) \ 897d182336Sryan_chen ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20)) 90499853d6Sryan_chen #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 91499853d6Sryan_chen #define CE_CTRL_DUMMY_LOW_MASK 0x3 92499853d6Sryan_chen #define CE_CTRL_DUMMY(dummy) \ 93499853d6Sryan_chen (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 94499853d6Sryan_chen << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 95499853d6Sryan_chen (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 96499853d6Sryan_chen #define CE_CTRL_STOP_ACTIVE BIT(2) 97499853d6Sryan_chen #define CE_CTRL_MODE_MASK 0x3 98499853d6Sryan_chen #define CE_CTRL_READMODE 0x0 99499853d6Sryan_chen #define CE_CTRL_FREADMODE 0x1 100499853d6Sryan_chen #define CE_CTRL_WRITEMODE 0x2 101499853d6Sryan_chen #define CE_CTRL_USERMODE 0x3 102499853d6Sryan_chen 103*0a73b911SChin-Ting Kuo /* Auto Soft-Reset Command Control */ 104*0a73b911SChin-Ting Kuo #define SOFT_RST_CMD_EN GENMASK(1, 0) 105*0a73b911SChin-Ting Kuo 106499853d6Sryan_chen /* 107499853d6Sryan_chen * The Segment Register uses a 8MB unit to encode the start address 108499853d6Sryan_chen * and the end address of the AHB window of a SPI flash device. 109499853d6Sryan_chen * Default segment addresses are : 110499853d6Sryan_chen * 111499853d6Sryan_chen * CE0 0x20000000 - 0x2fffffff 128MB 112499853d6Sryan_chen * CE1 0x28000000 - 0x29ffffff 32MB 113499853d6Sryan_chen * CE2 0x2a000000 - 0x2bffffff 32MB 114499853d6Sryan_chen * 115499853d6Sryan_chen * The full address space of the AHB window of the controller is 116499853d6Sryan_chen * covered and CE0 start address and CE2 end addresses are read-only. 117499853d6Sryan_chen */ 118499853d6Sryan_chen #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 119499853d6Sryan_chen #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 120499853d6Sryan_chen #define SEGMENT_ADDR_VALUE(start, end) \ 121499853d6Sryan_chen (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 122499853d6Sryan_chen 123da83dd7eSryan_chen #define G6_SEGMENT_ADDR_START(reg) (reg & 0xffff) 124da83dd7eSryan_chen #define G6_SEGMENT_ADDR_END(reg) ((reg >> 16) & 0xffff) 125da83dd7eSryan_chen #define G6_SEGMENT_ADDR_VALUE(start, end) \ 1266167da3dSryan_chen ((((start) >> 16) & 0xffff) | (((end) - 0x100000) & 0xffff0000)) 127da83dd7eSryan_chen 128499853d6Sryan_chen /* DMA Control/Status Register */ 129499853d6Sryan_chen #define DMA_CTRL_DELAY_SHIFT 8 130499853d6Sryan_chen #define DMA_CTRL_DELAY_MASK 0xf 131499853d6Sryan_chen #define DMA_CTRL_FREQ_SHIFT 4 132f87fadc3Sryan_chen #define G6_DMA_CTRL_FREQ_SHIFT 16 133f87fadc3Sryan_chen 134499853d6Sryan_chen #define DMA_CTRL_FREQ_MASK 0xf 135499853d6Sryan_chen #define TIMING_MASK(div, delay) \ 136499853d6Sryan_chen (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 137499853d6Sryan_chen ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 138f87fadc3Sryan_chen #define G6_TIMING_MASK(div, delay) \ 139f87fadc3Sryan_chen (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 140f87fadc3Sryan_chen ((div & DMA_CTRL_FREQ_MASK) << G6_DMA_CTRL_FREQ_SHIFT)) 141499853d6Sryan_chen #define DMA_CTRL_CALIB BIT(3) 142499853d6Sryan_chen #define DMA_CTRL_CKSUM BIT(2) 143499853d6Sryan_chen #define DMA_CTRL_WRITE BIT(1) 144499853d6Sryan_chen #define DMA_CTRL_ENABLE BIT(0) 145499853d6Sryan_chen 146*0a73b911SChin-Ting Kuo /* for ast2600 setting */ 147*0a73b911SChin-Ting Kuo #define SPI_3B_AUTO_CLR_REG 0x1e6e2510 148*0a73b911SChin-Ting Kuo #define SPI_3B_AUTO_CLR BIT(9) 149*0a73b911SChin-Ting Kuo 150*0a73b911SChin-Ting Kuo 151499853d6Sryan_chen /* 152*0a73b911SChin-Ting Kuo * flash related info 153499853d6Sryan_chen */ 154499853d6Sryan_chen struct aspeed_spi_flash { 155499853d6Sryan_chen u8 cs; 156499853d6Sryan_chen bool init; /* Initialized when the SPI bus is 157499853d6Sryan_chen * first claimed 158499853d6Sryan_chen */ 159499853d6Sryan_chen void __iomem *ahb_base; /* AHB Window for this device */ 160499853d6Sryan_chen u32 ahb_size; /* AHB Window segment size */ 161499853d6Sryan_chen u32 ce_ctrl_user; /* CE Control Register for USER mode */ 162499853d6Sryan_chen u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 163499853d6Sryan_chen u32 iomode; 164499853d6Sryan_chen 165499853d6Sryan_chen struct spi_flash *spi; /* Associated SPI Flash device */ 166499853d6Sryan_chen }; 167499853d6Sryan_chen 168499853d6Sryan_chen struct aspeed_spi_priv { 169499853d6Sryan_chen struct aspeed_spi_regs *regs; 170499853d6Sryan_chen void __iomem *ahb_base; /* AHB Window for all flash devices */ 171499853d6Sryan_chen int new_ver; 172499853d6Sryan_chen u32 ahb_size; /* AHB Window segments size */ 173499853d6Sryan_chen 174499853d6Sryan_chen ulong hclk_rate; /* AHB clock rate */ 175499853d6Sryan_chen u32 max_hz; 176499853d6Sryan_chen u8 num_cs; 177499853d6Sryan_chen bool is_fmc; 178499853d6Sryan_chen 179499853d6Sryan_chen struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 180499853d6Sryan_chen u32 flash_count; 181499853d6Sryan_chen 182499853d6Sryan_chen u8 cmd_buf[16]; /* SPI command in progress */ 183499853d6Sryan_chen size_t cmd_len; 184499853d6Sryan_chen }; 185499853d6Sryan_chen 186499853d6Sryan_chen static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 187499853d6Sryan_chen { 188499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 189499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 190499853d6Sryan_chen u8 cs = slave_plat->cs; 191499853d6Sryan_chen 192499853d6Sryan_chen if (cs >= priv->flash_count) { 193499853d6Sryan_chen pr_err("invalid CS %u\n", cs); 194499853d6Sryan_chen return NULL; 195499853d6Sryan_chen } 196499853d6Sryan_chen 197499853d6Sryan_chen return &priv->flashes[cs]; 198499853d6Sryan_chen } 199499853d6Sryan_chen 200ac86fa8bSryan_chen static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 201499853d6Sryan_chen { 2027d182336Sryan_chen u32 hclk_rate = priv->hclk_rate; 203499853d6Sryan_chen /* HCLK/1 .. HCLK/16 */ 204499853d6Sryan_chen const u8 hclk_masks[] = { 205499853d6Sryan_chen 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 206499853d6Sryan_chen }; 2077d182336Sryan_chen u8 base_div = 0; 208f87fadc3Sryan_chen int done = 0; 209f87fadc3Sryan_chen u32 i, j = 0; 2107d182336Sryan_chen u32 hclk_div_setting = 0; 211499853d6Sryan_chen 212f87fadc3Sryan_chen for (j = 0; j < 0xf; i++) { 2137d182336Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 2147d182336Sryan_chen base_div = j * 16; 215f87fadc3Sryan_chen if (max_hz >= (hclk_rate / ((i + 1) + base_div))) { 216f87fadc3Sryan_chen 217f87fadc3Sryan_chen done = 1; 2187d182336Sryan_chen break; 2197d182336Sryan_chen } 2207d182336Sryan_chen } 221f87fadc3Sryan_chen if (done) 222f87fadc3Sryan_chen break; 2237d182336Sryan_chen } 224499853d6Sryan_chen 225f87fadc3Sryan_chen debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n", 226f87fadc3Sryan_chen hclk_rate, max_hz, j, i + 1, hclk_masks[i], hclk_rate / (i + 1 + base_div)); 2277d182336Sryan_chen 2287d182336Sryan_chen hclk_div_setting = ((j << 4) | hclk_masks[i]); 2297d182336Sryan_chen 230ac86fa8bSryan_chen return hclk_div_setting; 231ac86fa8bSryan_chen 232ac86fa8bSryan_chen } 233ac86fa8bSryan_chen 234ac86fa8bSryan_chen static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 235ac86fa8bSryan_chen { 236ac86fa8bSryan_chen u32 hclk_rate = priv->hclk_rate; 237ac86fa8bSryan_chen /* HCLK/1 .. HCLK/16 */ 238ac86fa8bSryan_chen const u8 hclk_masks[] = { 239ac86fa8bSryan_chen 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 240ac86fa8bSryan_chen }; 241d32338fdSryan_chen u32 i; 242ac86fa8bSryan_chen u32 hclk_div_setting = 0; 243ac86fa8bSryan_chen 244499853d6Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 245499853d6Sryan_chen if (max_hz >= (hclk_rate / (i + 1))) 246499853d6Sryan_chen break; 247499853d6Sryan_chen } 248499853d6Sryan_chen debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 249499853d6Sryan_chen hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 250499853d6Sryan_chen 2517d182336Sryan_chen hclk_div_setting = hclk_masks[i]; 2527d182336Sryan_chen 2537d182336Sryan_chen return hclk_div_setting; 254499853d6Sryan_chen } 255499853d6Sryan_chen 256499853d6Sryan_chen /* 257499853d6Sryan_chen * Use some address/size under the first flash device CE0 258499853d6Sryan_chen */ 259499853d6Sryan_chen static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, 260499853d6Sryan_chen u8 delay) 261499853d6Sryan_chen { 262499853d6Sryan_chen u32 flash_addr = (u32)priv->ahb_base + 0x10000; 263499853d6Sryan_chen u32 flash_len = 0x200; 264499853d6Sryan_chen u32 dma_ctrl; 265499853d6Sryan_chen u32 checksum; 266499853d6Sryan_chen 267499853d6Sryan_chen writel(flash_addr, &priv->regs->dma_flash_addr); 268499853d6Sryan_chen writel(flash_len, &priv->regs->dma_len); 269499853d6Sryan_chen 270499853d6Sryan_chen /* 271499853d6Sryan_chen * When doing calibration, the SPI clock rate in the CE0 272499853d6Sryan_chen * Control Register and the data input delay cycles in the 273499853d6Sryan_chen * Read Timing Compensation Register are replaced by bit[11:4]. 274499853d6Sryan_chen */ 275f87fadc3Sryan_chen if(priv->new_ver) 276f87fadc3Sryan_chen dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 277f87fadc3Sryan_chen G6_TIMING_MASK(div, delay); 278f87fadc3Sryan_chen else 279499853d6Sryan_chen dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 280499853d6Sryan_chen TIMING_MASK(div, delay); 281499853d6Sryan_chen writel(dma_ctrl, &priv->regs->dma_ctrl); 282499853d6Sryan_chen 283499853d6Sryan_chen while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 284499853d6Sryan_chen ; 285499853d6Sryan_chen 286499853d6Sryan_chen writel(0x0, &priv->regs->intr_ctrl); 287499853d6Sryan_chen 288499853d6Sryan_chen checksum = readl(&priv->regs->dma_checksum); 289499853d6Sryan_chen 290499853d6Sryan_chen writel(0x0, &priv->regs->dma_ctrl); 291499853d6Sryan_chen 292499853d6Sryan_chen return checksum; 293499853d6Sryan_chen } 294499853d6Sryan_chen 295499853d6Sryan_chen static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, 296499853d6Sryan_chen u8 delay) 297499853d6Sryan_chen { 298499853d6Sryan_chen /* TODO(clg@kaod.org): the SPI controllers do not have the DMA 299499853d6Sryan_chen * registers. The algorithm is the same. 300499853d6Sryan_chen */ 301499853d6Sryan_chen if (!priv->is_fmc) { 302499853d6Sryan_chen pr_warn("No timing calibration support for SPI controllers"); 303499853d6Sryan_chen return 0xbadc0de; 304499853d6Sryan_chen } 305499853d6Sryan_chen 306499853d6Sryan_chen return aspeed_spi_fmc_checksum(priv, div, delay); 307499853d6Sryan_chen } 308499853d6Sryan_chen 309499853d6Sryan_chen #define TIMING_DELAY_DI_4NS BIT(3) 310499853d6Sryan_chen #define TIMING_DELAY_HCYCLE_MAX 5 311499853d6Sryan_chen 312499853d6Sryan_chen static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) 313499853d6Sryan_chen { 314499853d6Sryan_chen /* HCLK/5 .. HCLK/1 */ 315499853d6Sryan_chen const u8 hclk_masks[] = { 13, 6, 14, 7, 15 }; 316499853d6Sryan_chen u32 timing_reg = 0; 317499853d6Sryan_chen u32 checksum, gold_checksum; 318f87fadc3Sryan_chen int i, hcycle, delay_ns; 319499853d6Sryan_chen 320499853d6Sryan_chen debug("Read timing calibration :\n"); 321499853d6Sryan_chen 322499853d6Sryan_chen /* Compute reference checksum at lowest freq HCLK/16 */ 323499853d6Sryan_chen gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); 324499853d6Sryan_chen 325499853d6Sryan_chen /* 326499853d6Sryan_chen * Set CE0 Control Register to FAST READ command mode. The 327499853d6Sryan_chen * HCLK divisor will be set through the DMA Control Register. 328499853d6Sryan_chen */ 329499853d6Sryan_chen writel(CE_CTRL_CMD(0xb) | CE_CTRL_DUMMY(1) | CE_CTRL_FREADMODE, 330499853d6Sryan_chen &priv->regs->ce_ctrl[0]); 331499853d6Sryan_chen 332499853d6Sryan_chen /* Increase HCLK freq */ 3337d182336Sryan_chen if (priv->new_ver) { 3347d182336Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 3357d182336Sryan_chen u32 hdiv = 5 - i; 336f87fadc3Sryan_chen u32 hshift = (hdiv - 2) * 8; 3377d182336Sryan_chen bool pass = false; 3387d182336Sryan_chen u8 delay; 339f87fadc3Sryan_chen u16 first_delay = 0; 340f87fadc3Sryan_chen u16 end_delay = 0; 341f87fadc3Sryan_chen u32 cal_tmp; 342f87fadc3Sryan_chen debug(" hdiv %d, hshift %d \n", hdiv, hshift); 3437d182336Sryan_chen if (priv->hclk_rate / hdiv > priv->max_hz) { 3447d182336Sryan_chen debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 3457d182336Sryan_chen continue; 3467d182336Sryan_chen } 3477d182336Sryan_chen 3487d182336Sryan_chen /* Try without the 4ns DI delay */ 349f87fadc3Sryan_chen hcycle = delay = 0; 350f87fadc3Sryan_chen debug("** Dealy Disable ** \n"); 351f87fadc3Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], delay); 3527d182336Sryan_chen pass = (checksum == gold_checksum); 353d32338fdSryan_chen debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 3547d182336Sryan_chen hdiv, hcycle, pass ? "PASS" : "FAIL"); 3557d182336Sryan_chen 3567d182336Sryan_chen /* All good for this freq */ 3577d182336Sryan_chen if (pass) 358f87fadc3Sryan_chen goto next_div; 359f87fadc3Sryan_chen 360f87fadc3Sryan_chen /* Increase HCLK cycles until read succeeds */ 361f87fadc3Sryan_chen for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 362f87fadc3Sryan_chen /* Try first with a 4ns DI delay */ 363f87fadc3Sryan_chen delay = TIMING_DELAY_DI_4NS | hcycle; 364f87fadc3Sryan_chen debug("** Delay Enable : hcycle %x ** \n", hcycle); 365f87fadc3Sryan_chen for (delay_ns = 0; delay_ns < 0xf; delay_ns++) { 366f87fadc3Sryan_chen delay |= (delay_ns << 4); 367f87fadc3Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 368f87fadc3Sryan_chen delay); 369f87fadc3Sryan_chen pass = (checksum == gold_checksum); 370f87fadc3Sryan_chen debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle, %d delay_ns : %s\n", 371f87fadc3Sryan_chen hdiv, hcycle, delay_ns, pass ? "PASS" : "FAIL"); 372f87fadc3Sryan_chen 373f87fadc3Sryan_chen /* Try again with more HCLK cycles */ 374f87fadc3Sryan_chen if (!pass) { 375f87fadc3Sryan_chen if (!first_delay) 376f87fadc3Sryan_chen continue; 377f87fadc3Sryan_chen else { 378f87fadc3Sryan_chen end_delay = (hcycle << 4) | (delay_ns); 379f87fadc3Sryan_chen end_delay = end_delay - 1; 380f87fadc3Sryan_chen pass = 1; 381f87fadc3Sryan_chen debug("find end_delay %x %d %d\n", end_delay, hcycle, delay_ns); 3827d182336Sryan_chen break; 3837d182336Sryan_chen } 384f87fadc3Sryan_chen } else { 385f87fadc3Sryan_chen if (!first_delay) { 386f87fadc3Sryan_chen first_delay = (hcycle << 4) | delay_ns; 387f87fadc3Sryan_chen debug("find first_delay %x %d %d\n", first_delay, hcycle, delay_ns); 388f87fadc3Sryan_chen } 389f87fadc3Sryan_chen if (!end_delay) 390f87fadc3Sryan_chen pass = 0; 391f87fadc3Sryan_chen } 392f87fadc3Sryan_chen } 3937d182336Sryan_chen 3947d182336Sryan_chen if (pass) { 395f87fadc3Sryan_chen cal_tmp = (first_delay + end_delay) / 2; 396f87fadc3Sryan_chen delay = TIMING_DELAY_DI_4NS | ((cal_tmp & 0xf) << 4) | (cal_tmp >> 4); 397f87fadc3Sryan_chen break; 398f87fadc3Sryan_chen } 399f87fadc3Sryan_chen } 400f87fadc3Sryan_chen next_div: 401f87fadc3Sryan_chen if (pass) { 4027d182336Sryan_chen timing_reg &= ~(0xfu << hshift); 4037d182336Sryan_chen timing_reg |= delay << hshift; 404f87fadc3Sryan_chen debug("timing_reg %x, delay %x, hshift bit %d\n",timing_reg, delay, hshift); 4057d182336Sryan_chen } 4067d182336Sryan_chen } 4077d182336Sryan_chen } else { 408499853d6Sryan_chen for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 409499853d6Sryan_chen u32 hdiv = 5 - i; 410499853d6Sryan_chen u32 hshift = (hdiv - 1) << 2; 411499853d6Sryan_chen bool pass = false; 412499853d6Sryan_chen u8 delay; 413499853d6Sryan_chen 414499853d6Sryan_chen if (priv->hclk_rate / hdiv > priv->max_hz) { 415499853d6Sryan_chen debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 416499853d6Sryan_chen continue; 417499853d6Sryan_chen } 418499853d6Sryan_chen 419499853d6Sryan_chen /* Increase HCLK cycles until read succeeds */ 420499853d6Sryan_chen for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 421499853d6Sryan_chen /* Try first with a 4ns DI delay */ 422499853d6Sryan_chen delay = TIMING_DELAY_DI_4NS | hcycle; 423499853d6Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 424499853d6Sryan_chen delay); 425499853d6Sryan_chen pass = (checksum == gold_checksum); 426499853d6Sryan_chen debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 427499853d6Sryan_chen hdiv, hcycle, pass ? "PASS" : "FAIL"); 428499853d6Sryan_chen 429499853d6Sryan_chen /* Try again with more HCLK cycles */ 430499853d6Sryan_chen if (!pass) 431499853d6Sryan_chen continue; 432499853d6Sryan_chen 433499853d6Sryan_chen /* Try without the 4ns DI delay */ 434499853d6Sryan_chen delay = hcycle; 435499853d6Sryan_chen checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 436499853d6Sryan_chen delay); 437499853d6Sryan_chen pass = (checksum == gold_checksum); 438499853d6Sryan_chen debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 439499853d6Sryan_chen hdiv, hcycle, pass ? "PASS" : "FAIL"); 440499853d6Sryan_chen 441499853d6Sryan_chen /* All good for this freq */ 442499853d6Sryan_chen if (pass) 443499853d6Sryan_chen break; 444499853d6Sryan_chen } 445499853d6Sryan_chen 446499853d6Sryan_chen if (pass) { 447499853d6Sryan_chen timing_reg &= ~(0xfu << hshift); 448499853d6Sryan_chen timing_reg |= delay << hshift; 449499853d6Sryan_chen } 450499853d6Sryan_chen } 4517d182336Sryan_chen } 452499853d6Sryan_chen debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 453499853d6Sryan_chen writel(timing_reg, &priv->regs->timings); 454499853d6Sryan_chen 455499853d6Sryan_chen /* Reset CE0 Control Register */ 456499853d6Sryan_chen writel(0x0, &priv->regs->ce_ctrl[0]); 457499853d6Sryan_chen 458499853d6Sryan_chen return 0; 459499853d6Sryan_chen } 460499853d6Sryan_chen 461499853d6Sryan_chen static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 462499853d6Sryan_chen { 463499853d6Sryan_chen int cs, ret; 464499853d6Sryan_chen 465499853d6Sryan_chen /* 466499853d6Sryan_chen * Enable write on all flash devices as USER command mode 467499853d6Sryan_chen * requires it. 468499853d6Sryan_chen */ 469499853d6Sryan_chen setbits_le32(&priv->regs->conf, 470499853d6Sryan_chen CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 471499853d6Sryan_chen 472499853d6Sryan_chen /* 473499853d6Sryan_chen * Set the Read Timing Compensation Register. This setting 474499853d6Sryan_chen * applies to all devices. 475499853d6Sryan_chen */ 476499853d6Sryan_chen ret = aspeed_spi_timing_calibration(priv); 477499853d6Sryan_chen if (ret) 478499853d6Sryan_chen return ret; 479499853d6Sryan_chen 480499853d6Sryan_chen /* 481499853d6Sryan_chen * Set safe default settings for each device. These will be 482499853d6Sryan_chen * tuned after the SPI flash devices are probed. 483499853d6Sryan_chen */ 484da83dd7eSryan_chen if (priv->new_ver) { 485499853d6Sryan_chen for (cs = 0; cs < priv->flash_count; cs++) { 486499853d6Sryan_chen struct aspeed_spi_flash *flash = &priv->flashes[cs]; 487499853d6Sryan_chen u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 488d32338fdSryan_chen u32 addr_config = 0; 489499853d6Sryan_chen switch(cs) { 490da83dd7eSryan_chen case 0: 491da83dd7eSryan_chen flash->ahb_base = cs ? (void *)G6_SEGMENT_ADDR_START(seg_addr) : 492da83dd7eSryan_chen priv->ahb_base; 493d32338fdSryan_chen debug("cs0 mem-map : %x \n", (u32)flash->ahb_base); 494da83dd7eSryan_chen break; 495499853d6Sryan_chen case 1: 4966167da3dSryan_chen flash->ahb_base = priv->flashes[0].ahb_base + 0x8000000; //cs0 + 128Mb : use 64MB 4976167da3dSryan_chen debug("cs1 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 4986167da3dSryan_chen addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 128Mb 499d32338fdSryan_chen writel(addr_config, &priv->regs->segment_addr[cs]); 500499853d6Sryan_chen break; 501499853d6Sryan_chen case 2: 5026167da3dSryan_chen flash->ahb_base = priv->flashes[0].ahb_base + 0xc000000; //cs0 + 192Mb : use 64MB 5036167da3dSryan_chen debug("cs2 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 5046167da3dSryan_chen addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 128Mb 5056167da3dSryan_chen writel(addr_config, &priv->regs->segment_addr[cs]); 506499853d6Sryan_chen break; 507499853d6Sryan_chen } 508da83dd7eSryan_chen flash->cs = cs; 509da83dd7eSryan_chen flash->ce_ctrl_user = CE_CTRL_USERMODE; 510da83dd7eSryan_chen flash->ce_ctrl_fread = CE_CTRL_READMODE; 511499853d6Sryan_chen } 512da83dd7eSryan_chen } else { 513da83dd7eSryan_chen for (cs = 0; cs < priv->flash_count; cs++) { 514da83dd7eSryan_chen struct aspeed_spi_flash *flash = &priv->flashes[cs]; 515da83dd7eSryan_chen u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 516499853d6Sryan_chen /* 517499853d6Sryan_chen * The start address of the AHB window of CE0 is 518499853d6Sryan_chen * read-only and is the same as the address of the 519499853d6Sryan_chen * overall AHB window of the controller for all flash 520499853d6Sryan_chen * devices. 521499853d6Sryan_chen */ 522499853d6Sryan_chen flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 523499853d6Sryan_chen priv->ahb_base; 524499853d6Sryan_chen 525499853d6Sryan_chen flash->cs = cs; 526499853d6Sryan_chen flash->ce_ctrl_user = CE_CTRL_USERMODE; 527499853d6Sryan_chen flash->ce_ctrl_fread = CE_CTRL_READMODE; 528499853d6Sryan_chen } 529da83dd7eSryan_chen } 530499853d6Sryan_chen return 0; 531499853d6Sryan_chen } 532499853d6Sryan_chen 533499853d6Sryan_chen static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 534499853d6Sryan_chen size_t len) 535499853d6Sryan_chen { 536499853d6Sryan_chen size_t offset = 0; 537499853d6Sryan_chen 538499853d6Sryan_chen if (!((uintptr_t)buf % 4)) { 539499853d6Sryan_chen readsl(ahb_base, buf, len >> 2); 540499853d6Sryan_chen offset = len & ~0x3; 541499853d6Sryan_chen len -= offset; 542499853d6Sryan_chen } 543499853d6Sryan_chen readsb(ahb_base, (u8 *)buf + offset, len); 544499853d6Sryan_chen 545499853d6Sryan_chen return 0; 546499853d6Sryan_chen } 547499853d6Sryan_chen 548499853d6Sryan_chen static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 549499853d6Sryan_chen size_t len) 550499853d6Sryan_chen { 551499853d6Sryan_chen size_t offset = 0; 552499853d6Sryan_chen 553499853d6Sryan_chen if (!((uintptr_t)buf % 4)) { 554499853d6Sryan_chen writesl(ahb_base, buf, len >> 2); 555499853d6Sryan_chen offset = len & ~0x3; 556499853d6Sryan_chen len -= offset; 557499853d6Sryan_chen } 558499853d6Sryan_chen writesb(ahb_base, (u8 *)buf + offset, len); 559499853d6Sryan_chen 560499853d6Sryan_chen return 0; 561499853d6Sryan_chen } 562499853d6Sryan_chen 563499853d6Sryan_chen static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 564499853d6Sryan_chen struct aspeed_spi_flash *flash) 565499853d6Sryan_chen { 566499853d6Sryan_chen u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 567499853d6Sryan_chen 568499853d6Sryan_chen /* Deselect CS and set USER command mode */ 569499853d6Sryan_chen writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 570499853d6Sryan_chen 571499853d6Sryan_chen /* Select CS */ 572499853d6Sryan_chen clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 573499853d6Sryan_chen } 574499853d6Sryan_chen 575499853d6Sryan_chen static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 576499853d6Sryan_chen struct aspeed_spi_flash *flash) 577499853d6Sryan_chen { 578499853d6Sryan_chen /* Deselect CS first */ 579499853d6Sryan_chen setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 580499853d6Sryan_chen 581499853d6Sryan_chen /* Restore default command mode */ 582499853d6Sryan_chen writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 583499853d6Sryan_chen } 584499853d6Sryan_chen 585499853d6Sryan_chen static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 586499853d6Sryan_chen struct aspeed_spi_flash *flash, 587499853d6Sryan_chen u8 opcode, u8 *read_buf, int len) 588499853d6Sryan_chen { 589499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 590499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 591499853d6Sryan_chen aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 592499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 593499853d6Sryan_chen 594499853d6Sryan_chen return 0; 595499853d6Sryan_chen } 596499853d6Sryan_chen 597499853d6Sryan_chen static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 598499853d6Sryan_chen struct aspeed_spi_flash *flash, 599499853d6Sryan_chen u8 opcode, const u8 *write_buf, int len) 600499853d6Sryan_chen { 601499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 602499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 603499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 604499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 605499853d6Sryan_chen 606528cd552Sryan_chen debug("=== write opcode [%x] ==== \n", opcode); 607499853d6Sryan_chen switch(opcode) { 608499853d6Sryan_chen case SPINOR_OP_EN4B: 609*0a73b911SChin-Ting Kuo /* For ast2600, if 2 chips ABR mode is enabled, 610*0a73b911SChin-Ting Kuo * turn on 3B mode auto clear in order to avoid 611*0a73b911SChin-Ting Kuo * the scenario where spi controller is at 4B mode 612*0a73b911SChin-Ting Kuo * and flash site is at 3B mode after 3rd switch. 613*0a73b911SChin-Ting Kuo */ 614*0a73b911SChin-Ting Kuo if (priv->new_ver == 1 && (readl(SPI_3B_AUTO_CLR_REG) & SPI_3B_AUTO_CLR)) 615*0a73b911SChin-Ting Kuo writel(readl(&priv->regs->soft_rst_cmd_ctrl) | SOFT_RST_CMD_EN, 616*0a73b911SChin-Ting Kuo &priv->regs->soft_rst_cmd_ctrl); 617*0a73b911SChin-Ting Kuo 618499853d6Sryan_chen writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); 619499853d6Sryan_chen break; 620499853d6Sryan_chen case SPINOR_OP_EX4B: 621499853d6Sryan_chen writel(readl(&priv->regs->ctrl) & ~BIT(flash->cs), &priv->regs->ctrl); 622499853d6Sryan_chen break; 623499853d6Sryan_chen } 624499853d6Sryan_chen return 0; 625499853d6Sryan_chen } 626499853d6Sryan_chen 627499853d6Sryan_chen static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 628499853d6Sryan_chen struct aspeed_spi_flash *flash, 629499853d6Sryan_chen const u8 *cmdbuf, unsigned int cmdlen) 630499853d6Sryan_chen { 631499853d6Sryan_chen int i; 632499853d6Sryan_chen u8 byte0 = 0x0; 633499853d6Sryan_chen u8 addrlen = cmdlen - 1; 634499853d6Sryan_chen 635499853d6Sryan_chen /* First, send the opcode */ 636499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 637499853d6Sryan_chen 638528cd552Sryan_chen if(flash->iomode == CE_CTRL_IO_QUAD_ADDR_DATA) 639528cd552Sryan_chen writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); 640528cd552Sryan_chen 641499853d6Sryan_chen /* 642499853d6Sryan_chen * The controller is configured for 4BYTE address mode. Fix 643499853d6Sryan_chen * the address width and send an extra byte if the SPI Flash 644499853d6Sryan_chen * layer uses 3 bytes addresses. 645499853d6Sryan_chen */ 646499853d6Sryan_chen if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) 647499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); 648499853d6Sryan_chen 649499853d6Sryan_chen /* Then the address */ 650499853d6Sryan_chen for (i = 1 ; i < cmdlen; i++) 651499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 652499853d6Sryan_chen } 653499853d6Sryan_chen 654499853d6Sryan_chen static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 655499853d6Sryan_chen struct aspeed_spi_flash *flash, 656499853d6Sryan_chen unsigned int cmdlen, const u8 *cmdbuf, 657499853d6Sryan_chen unsigned int len, u8 *read_buf) 658499853d6Sryan_chen { 659499853d6Sryan_chen u8 dummy = 0xff; 660499853d6Sryan_chen int i; 661499853d6Sryan_chen 662499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 663499853d6Sryan_chen 664499853d6Sryan_chen /* cmd buffer = cmd + addr + dummies */ 665499853d6Sryan_chen aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 666499853d6Sryan_chen cmdlen - (flash->spi->read_dummy/8)); 667499853d6Sryan_chen 668499853d6Sryan_chen for (i = 0 ; i < (flash->spi->read_dummy/8); i++) 669499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 670499853d6Sryan_chen 671499853d6Sryan_chen if (flash->iomode) { 672499853d6Sryan_chen clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 673499853d6Sryan_chen CE_CTRL_IO_MODE_MASK); 674499853d6Sryan_chen setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->iomode); 675499853d6Sryan_chen } 676499853d6Sryan_chen 677499853d6Sryan_chen aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 678499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 679499853d6Sryan_chen 680499853d6Sryan_chen return 0; 681499853d6Sryan_chen } 682499853d6Sryan_chen 683499853d6Sryan_chen static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 684499853d6Sryan_chen struct aspeed_spi_flash *flash, 685499853d6Sryan_chen unsigned int cmdlen, const u8 *cmdbuf, 686499853d6Sryan_chen unsigned int len, const u8 *write_buf) 687499853d6Sryan_chen { 688499853d6Sryan_chen aspeed_spi_start_user(priv, flash); 689499853d6Sryan_chen 69076e3c7a9Sryan_chen /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ 691499853d6Sryan_chen aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); 69276e3c7a9Sryan_chen 69376e3c7a9Sryan_chen /* data will use io mode */ 69476e3c7a9Sryan_chen if(flash->iomode == CE_CTRL_IO_QUAD_DATA) 69576e3c7a9Sryan_chen writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); 69676e3c7a9Sryan_chen 697499853d6Sryan_chen aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 698499853d6Sryan_chen 699499853d6Sryan_chen aspeed_spi_stop_user(priv, flash); 700499853d6Sryan_chen 701499853d6Sryan_chen return 0; 702499853d6Sryan_chen } 703499853d6Sryan_chen 704499853d6Sryan_chen static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 705499853d6Sryan_chen const u8 *cmdbuf, unsigned int cmdlen) 706499853d6Sryan_chen { 707499853d6Sryan_chen u8 addrlen = cmdlen - 1; 708499853d6Sryan_chen u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 709499853d6Sryan_chen 710499853d6Sryan_chen /* 711499853d6Sryan_chen * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 712499853d6Sryan_chen * change one day 713499853d6Sryan_chen */ 714499853d6Sryan_chen if (addrlen == 4) 715499853d6Sryan_chen addr = (addr << 8) | cmdbuf[4]; 716499853d6Sryan_chen 717499853d6Sryan_chen return addr; 718499853d6Sryan_chen } 719499853d6Sryan_chen 720499853d6Sryan_chen /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 721499853d6Sryan_chen static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 722499853d6Sryan_chen struct aspeed_spi_flash *flash, 723499853d6Sryan_chen unsigned int cmdlen, const u8 *cmdbuf, 724499853d6Sryan_chen unsigned int len, u8 *read_buf) 725499853d6Sryan_chen { 726499853d6Sryan_chen /* cmd buffer = cmd + addr + dummies */ 727499853d6Sryan_chen u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 728499853d6Sryan_chen cmdlen - (flash->spi->read_dummy/8)); 729499853d6Sryan_chen 730499853d6Sryan_chen /* 731499853d6Sryan_chen * Switch to USER command mode if the AHB window configured 732499853d6Sryan_chen * for the device is too small for the read operation 733499853d6Sryan_chen */ 734499853d6Sryan_chen if (offset + len >= flash->ahb_size) { 735499853d6Sryan_chen return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 736499853d6Sryan_chen len, read_buf); 737499853d6Sryan_chen } 738499853d6Sryan_chen 739499853d6Sryan_chen memcpy_fromio(read_buf, flash->ahb_base + offset, len); 740499853d6Sryan_chen 741499853d6Sryan_chen return 0; 742499853d6Sryan_chen } 743499853d6Sryan_chen 744499853d6Sryan_chen static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 745499853d6Sryan_chen const void *dout, void *din, unsigned long flags) 746499853d6Sryan_chen { 747499853d6Sryan_chen struct udevice *bus = dev->parent; 748499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(bus); 749499853d6Sryan_chen struct aspeed_spi_flash *flash; 750499853d6Sryan_chen u8 *cmd_buf = priv->cmd_buf; 751499853d6Sryan_chen size_t data_bytes; 752499853d6Sryan_chen int err = 0; 753499853d6Sryan_chen 754499853d6Sryan_chen flash = aspeed_spi_get_flash(dev); 755499853d6Sryan_chen if (!flash) 756499853d6Sryan_chen return -ENXIO; 757499853d6Sryan_chen 758499853d6Sryan_chen if (flags & SPI_XFER_BEGIN) { 759499853d6Sryan_chen /* save command in progress */ 760499853d6Sryan_chen priv->cmd_len = bitlen / 8; 761499853d6Sryan_chen memcpy(cmd_buf, dout, priv->cmd_len); 762499853d6Sryan_chen } 763499853d6Sryan_chen 764499853d6Sryan_chen if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 765499853d6Sryan_chen /* if start and end bit are set, the data bytes is 0. */ 766499853d6Sryan_chen data_bytes = 0; 767499853d6Sryan_chen } else { 768499853d6Sryan_chen data_bytes = bitlen / 8; 769499853d6Sryan_chen } 770499853d6Sryan_chen 771499853d6Sryan_chen debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 772499853d6Sryan_chen din ? "read" : "write", priv->cmd_len, data_bytes); 773499853d6Sryan_chen 774499853d6Sryan_chen if ((flags & SPI_XFER_END) || flags == 0) { 775499853d6Sryan_chen if (priv->cmd_len == 0) { 776499853d6Sryan_chen pr_err("No command is progress !\n"); 777499853d6Sryan_chen return -1; 778499853d6Sryan_chen } 779499853d6Sryan_chen 780499853d6Sryan_chen if (din && data_bytes) { 781499853d6Sryan_chen if (priv->cmd_len == 1) 782499853d6Sryan_chen err = aspeed_spi_read_reg(priv, flash, 783499853d6Sryan_chen cmd_buf[0], 784499853d6Sryan_chen din, data_bytes); 785499853d6Sryan_chen else 786499853d6Sryan_chen err = aspeed_spi_read(priv, flash, 787499853d6Sryan_chen priv->cmd_len, 788499853d6Sryan_chen cmd_buf, data_bytes, 789499853d6Sryan_chen din); 790499853d6Sryan_chen } else if (dout) { 791499853d6Sryan_chen if (priv->cmd_len == 1) 792499853d6Sryan_chen err = aspeed_spi_write_reg(priv, flash, 793499853d6Sryan_chen cmd_buf[0], 794499853d6Sryan_chen dout, data_bytes); 795499853d6Sryan_chen else 796499853d6Sryan_chen err = aspeed_spi_write_user(priv, flash, 797499853d6Sryan_chen priv->cmd_len, 798499853d6Sryan_chen cmd_buf, data_bytes, 799499853d6Sryan_chen dout); 800499853d6Sryan_chen } 801499853d6Sryan_chen 802499853d6Sryan_chen if (flags & SPI_XFER_END) { 803499853d6Sryan_chen /* clear command */ 804499853d6Sryan_chen memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 805499853d6Sryan_chen priv->cmd_len = 0; 806499853d6Sryan_chen } 807499853d6Sryan_chen } 808499853d6Sryan_chen 809499853d6Sryan_chen return err; 810499853d6Sryan_chen } 811499853d6Sryan_chen 812499853d6Sryan_chen static int aspeed_spi_child_pre_probe(struct udevice *dev) 813499853d6Sryan_chen { 814499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 815499853d6Sryan_chen 816499853d6Sryan_chen debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 817499853d6Sryan_chen slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 818499853d6Sryan_chen 819499853d6Sryan_chen if (!aspeed_spi_get_flash(dev)) 820499853d6Sryan_chen return -ENXIO; 821499853d6Sryan_chen 822499853d6Sryan_chen return 0; 823499853d6Sryan_chen } 824499853d6Sryan_chen 825499853d6Sryan_chen /* 826499853d6Sryan_chen * It is possible to automatically define a contiguous address space 827499853d6Sryan_chen * on top of all CEs in the AHB window of the controller but it would 828499853d6Sryan_chen * require much more work. Let's start with a simple mapping scheme 829499853d6Sryan_chen * which should work fine for a single flash device. 830499853d6Sryan_chen * 831499853d6Sryan_chen * More complex schemes should probably be defined with the device 832499853d6Sryan_chen * tree. 833499853d6Sryan_chen */ 834499853d6Sryan_chen static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 835499853d6Sryan_chen struct aspeed_spi_flash *flash) 836499853d6Sryan_chen { 837499853d6Sryan_chen u32 seg_addr; 838499853d6Sryan_chen 839499853d6Sryan_chen /* could be configured through the device tree */ 840499853d6Sryan_chen flash->ahb_size = flash->spi->size; 841499853d6Sryan_chen 842da83dd7eSryan_chen if (priv->new_ver) { 843da83dd7eSryan_chen seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 844da83dd7eSryan_chen (u32)flash->ahb_base + flash->ahb_size); 845da83dd7eSryan_chen } else { 846499853d6Sryan_chen seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 847499853d6Sryan_chen (u32)flash->ahb_base + flash->ahb_size); 848da83dd7eSryan_chen } 849499853d6Sryan_chen writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 850499853d6Sryan_chen 851499853d6Sryan_chen return 0; 852499853d6Sryan_chen } 853499853d6Sryan_chen 854499853d6Sryan_chen static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 855499853d6Sryan_chen struct aspeed_spi_flash *flash, 856499853d6Sryan_chen struct udevice *dev) 857499853d6Sryan_chen { 858499853d6Sryan_chen struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 859499853d6Sryan_chen struct spi_slave *slave = dev_get_parent_priv(dev); 860499853d6Sryan_chen u32 read_hclk; 861499853d6Sryan_chen 862499853d6Sryan_chen /* 863499853d6Sryan_chen * The SPI flash device slave should not change, so initialize 864499853d6Sryan_chen * it only once. 865499853d6Sryan_chen */ 866499853d6Sryan_chen if (flash->init) 867499853d6Sryan_chen return 0; 868499853d6Sryan_chen 869499853d6Sryan_chen /* 870499853d6Sryan_chen * The flash device has not been probed yet. Initial transfers 871499853d6Sryan_chen * to read the JEDEC of the device will use the initial 872499853d6Sryan_chen * default settings of the registers. 873499853d6Sryan_chen */ 874499853d6Sryan_chen if (!spi_flash->name) 875499853d6Sryan_chen return 0; 876499853d6Sryan_chen 877499853d6Sryan_chen debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " 878499853d6Sryan_chen "cmds [ erase:%x read=%x write:%x ] dummy:%d\n", 879499853d6Sryan_chen flash->cs, 880499853d6Sryan_chen spi_flash->name, spi_flash->flags, spi_flash->size, 881499853d6Sryan_chen spi_flash->page_size, spi_flash->sector_size, 882499853d6Sryan_chen spi_flash->erase_size, spi_flash->erase_opcode, 883499853d6Sryan_chen spi_flash->read_opcode, spi_flash->program_opcode, 884499853d6Sryan_chen spi_flash->read_dummy); 885499853d6Sryan_chen 886499853d6Sryan_chen flash->spi = spi_flash; 887499853d6Sryan_chen 8887d182336Sryan_chen flash->ce_ctrl_user = CE_CTRL_USERMODE; 889499853d6Sryan_chen 890ac86fa8bSryan_chen if(priv->new_ver) 891ac86fa8bSryan_chen read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 892ac86fa8bSryan_chen else 8937d182336Sryan_chen read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 894499853d6Sryan_chen 895528cd552Sryan_chen switch(flash->spi->read_opcode) { 896528cd552Sryan_chen case SPINOR_OP_READ_1_1_2: 897528cd552Sryan_chen case SPINOR_OP_READ_1_1_2_4B: 898499853d6Sryan_chen flash->iomode = CE_CTRL_IO_DUAL_DATA; 899528cd552Sryan_chen break; 900528cd552Sryan_chen case SPINOR_OP_READ_1_1_4: 901528cd552Sryan_chen case SPINOR_OP_READ_1_1_4_4B: 902d32338fdSryan_chen flash->iomode = CE_CTRL_IO_QUAD_DATA; 903528cd552Sryan_chen break; 904528cd552Sryan_chen case SPINOR_OP_READ_1_4_4: 905528cd552Sryan_chen case SPINOR_OP_READ_1_4_4_4B: 906528cd552Sryan_chen flash->iomode = CE_CTRL_IO_QUAD_ADDR_DATA; 907528cd552Sryan_chen printf("need modify dummy for 3 bytes"); 908528cd552Sryan_chen break; 909499853d6Sryan_chen } 910499853d6Sryan_chen 911d32338fdSryan_chen if(priv->new_ver) { 9127d182336Sryan_chen flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 9137d182336Sryan_chen flash->iomode | 9147d182336Sryan_chen CE_CTRL_CMD(flash->spi->read_opcode) | 9157d182336Sryan_chen CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 9167d182336Sryan_chen CE_CTRL_FREADMODE; 917d32338fdSryan_chen } else { 918499853d6Sryan_chen flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 919499853d6Sryan_chen flash->iomode | 920499853d6Sryan_chen CE_CTRL_CMD(flash->spi->read_opcode) | 921499853d6Sryan_chen CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 922499853d6Sryan_chen CE_CTRL_FREADMODE; 923d32338fdSryan_chen } 924499853d6Sryan_chen 925499853d6Sryan_chen debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 926499853d6Sryan_chen flash->ce_ctrl_user, flash->ce_ctrl_fread); 927499853d6Sryan_chen 928499853d6Sryan_chen /* Set the CE Control Register default (FAST READ) */ 929499853d6Sryan_chen writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 930499853d6Sryan_chen 931499853d6Sryan_chen /* Set Address Segment Register for direct AHB accesses */ 932499853d6Sryan_chen aspeed_spi_flash_set_segment(priv, flash); 933499853d6Sryan_chen 934499853d6Sryan_chen /* All done */ 935499853d6Sryan_chen flash->init = true; 936499853d6Sryan_chen 937499853d6Sryan_chen return 0; 938499853d6Sryan_chen } 939499853d6Sryan_chen 940499853d6Sryan_chen static int aspeed_spi_claim_bus(struct udevice *dev) 941499853d6Sryan_chen { 942499853d6Sryan_chen struct udevice *bus = dev->parent; 943499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(bus); 944499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 945499853d6Sryan_chen struct aspeed_spi_flash *flash; 946499853d6Sryan_chen 947499853d6Sryan_chen debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 948499853d6Sryan_chen 949499853d6Sryan_chen flash = aspeed_spi_get_flash(dev); 950499853d6Sryan_chen if (!flash) 951499853d6Sryan_chen return -ENODEV; 952499853d6Sryan_chen 953499853d6Sryan_chen return aspeed_spi_flash_init(priv, flash, dev); 954499853d6Sryan_chen } 955499853d6Sryan_chen 956499853d6Sryan_chen static int aspeed_spi_release_bus(struct udevice *dev) 957499853d6Sryan_chen { 958499853d6Sryan_chen struct udevice *bus = dev->parent; 959499853d6Sryan_chen struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 960499853d6Sryan_chen 961499853d6Sryan_chen debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 962499853d6Sryan_chen 963499853d6Sryan_chen if (!aspeed_spi_get_flash(dev)) 964499853d6Sryan_chen return -ENODEV; 965499853d6Sryan_chen 966499853d6Sryan_chen return 0; 967499853d6Sryan_chen } 968499853d6Sryan_chen 969499853d6Sryan_chen static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 970499853d6Sryan_chen { 971499853d6Sryan_chen debug("%s: setting mode to %x\n", bus->name, mode); 972499853d6Sryan_chen 973499853d6Sryan_chen if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 97476e3c7a9Sryan_chen #ifndef CONFIG_ASPEED_AST2600 975499853d6Sryan_chen pr_err("%s invalid QUAD IO mode\n", bus->name); 976499853d6Sryan_chen return -EINVAL; 97776e3c7a9Sryan_chen #endif 978499853d6Sryan_chen } 979499853d6Sryan_chen 980499853d6Sryan_chen /* The CE Control Register is set in claim_bus() */ 981499853d6Sryan_chen return 0; 982499853d6Sryan_chen } 983499853d6Sryan_chen 984499853d6Sryan_chen static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 985499853d6Sryan_chen { 986499853d6Sryan_chen debug("%s: setting speed to %u\n", bus->name, hz); 987499853d6Sryan_chen 988499853d6Sryan_chen /* The CE Control Register is set in claim_bus() */ 989499853d6Sryan_chen return 0; 990499853d6Sryan_chen } 991499853d6Sryan_chen 992499853d6Sryan_chen static int aspeed_spi_count_flash_devices(struct udevice *bus) 993499853d6Sryan_chen { 994499853d6Sryan_chen ofnode node; 995499853d6Sryan_chen int count = 0; 996499853d6Sryan_chen 997499853d6Sryan_chen dev_for_each_subnode(node, bus) { 998499853d6Sryan_chen if (ofnode_is_available(node) && 999499853d6Sryan_chen ofnode_device_is_compatible(node, "spi-flash")) 1000499853d6Sryan_chen count++; 1001499853d6Sryan_chen } 1002499853d6Sryan_chen 1003499853d6Sryan_chen return count; 1004499853d6Sryan_chen } 1005499853d6Sryan_chen 1006499853d6Sryan_chen static int aspeed_spi_bind(struct udevice *bus) 1007499853d6Sryan_chen { 1008499853d6Sryan_chen debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 1009499853d6Sryan_chen bus->seq); 1010499853d6Sryan_chen 1011499853d6Sryan_chen return 0; 1012499853d6Sryan_chen } 1013499853d6Sryan_chen 1014499853d6Sryan_chen static int aspeed_spi_probe(struct udevice *bus) 1015499853d6Sryan_chen { 1016499853d6Sryan_chen struct resource res_regs, res_ahb; 1017499853d6Sryan_chen struct aspeed_spi_priv *priv = dev_get_priv(bus); 1018499853d6Sryan_chen struct clk hclk; 1019499853d6Sryan_chen int ret; 1020499853d6Sryan_chen 1021499853d6Sryan_chen ret = dev_read_resource(bus, 0, &res_regs); 1022499853d6Sryan_chen if (ret < 0) 1023499853d6Sryan_chen return ret; 1024499853d6Sryan_chen 1025499853d6Sryan_chen priv->regs = (void __iomem *)res_regs.start; 1026499853d6Sryan_chen 1027499853d6Sryan_chen ret = dev_read_resource(bus, 1, &res_ahb); 1028499853d6Sryan_chen if (ret < 0) 1029499853d6Sryan_chen return ret; 1030499853d6Sryan_chen 1031499853d6Sryan_chen priv->ahb_base = (void __iomem *)res_ahb.start; 1032499853d6Sryan_chen priv->ahb_size = res_ahb.end - res_ahb.start; 1033499853d6Sryan_chen 1034499853d6Sryan_chen ret = clk_get_by_index(bus, 0, &hclk); 1035499853d6Sryan_chen if (ret < 0) { 1036499853d6Sryan_chen pr_err("%s could not get clock: %d\n", bus->name, ret); 1037499853d6Sryan_chen return ret; 1038499853d6Sryan_chen } 1039499853d6Sryan_chen 1040499853d6Sryan_chen priv->hclk_rate = clk_get_rate(&hclk); 1041499853d6Sryan_chen clk_free(&hclk); 1042499853d6Sryan_chen 1043499853d6Sryan_chen priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1044499853d6Sryan_chen 100000000); 1045499853d6Sryan_chen 1046499853d6Sryan_chen priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 1047499853d6Sryan_chen 1048499853d6Sryan_chen priv->flash_count = aspeed_spi_count_flash_devices(bus); 1049499853d6Sryan_chen if (priv->flash_count > priv->num_cs) { 1050499853d6Sryan_chen pr_err("%s has too many flash devices: %d\n", bus->name, 1051499853d6Sryan_chen priv->flash_count); 1052499853d6Sryan_chen return -EINVAL; 1053499853d6Sryan_chen } 1054499853d6Sryan_chen 1055499853d6Sryan_chen if (!priv->flash_count) { 1056499853d6Sryan_chen pr_err("%s has no flash devices ?!\n", bus->name); 1057499853d6Sryan_chen return -ENODEV; 1058499853d6Sryan_chen } 1059499853d6Sryan_chen 10607d182336Sryan_chen if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 1061f87fadc3Sryan_chen device_is_compatible(bus, "aspeed,ast2600-spi")) { 1062499853d6Sryan_chen priv->new_ver = 1; 1063499853d6Sryan_chen } 1064499853d6Sryan_chen 1065499853d6Sryan_chen /* 1066499853d6Sryan_chen * There are some slight differences between the FMC and the 1067499853d6Sryan_chen * SPI controllers 1068499853d6Sryan_chen */ 1069499853d6Sryan_chen priv->is_fmc = dev_get_driver_data(bus); 1070499853d6Sryan_chen 1071499853d6Sryan_chen ret = aspeed_spi_controller_init(priv); 1072499853d6Sryan_chen if (ret) 1073499853d6Sryan_chen return ret; 1074499853d6Sryan_chen 1075499853d6Sryan_chen debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", 1076499853d6Sryan_chen bus->name, priv->regs, priv->ahb_base, priv->max_hz, 1077499853d6Sryan_chen priv->flash_count, bus->seq); 1078499853d6Sryan_chen 1079499853d6Sryan_chen return 0; 1080499853d6Sryan_chen } 1081499853d6Sryan_chen 1082499853d6Sryan_chen static const struct dm_spi_ops aspeed_spi_ops = { 1083499853d6Sryan_chen .claim_bus = aspeed_spi_claim_bus, 1084499853d6Sryan_chen .release_bus = aspeed_spi_release_bus, 1085499853d6Sryan_chen .set_mode = aspeed_spi_set_mode, 1086499853d6Sryan_chen .set_speed = aspeed_spi_set_speed, 1087499853d6Sryan_chen .xfer = aspeed_spi_xfer, 1088499853d6Sryan_chen }; 1089499853d6Sryan_chen 1090499853d6Sryan_chen static const struct udevice_id aspeed_spi_ids[] = { 1091499853d6Sryan_chen { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1092499853d6Sryan_chen { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1093499853d6Sryan_chen { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1094499853d6Sryan_chen { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1095499853d6Sryan_chen { } 1096499853d6Sryan_chen }; 1097499853d6Sryan_chen 1098499853d6Sryan_chen U_BOOT_DRIVER(aspeed_spi) = { 1099499853d6Sryan_chen .name = "aspeed_spi", 1100499853d6Sryan_chen .id = UCLASS_SPI, 1101499853d6Sryan_chen .of_match = aspeed_spi_ids, 1102499853d6Sryan_chen .ops = &aspeed_spi_ops, 1103499853d6Sryan_chen .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1104499853d6Sryan_chen .child_pre_probe = aspeed_spi_child_pre_probe, 1105499853d6Sryan_chen .bind = aspeed_spi_bind, 1106499853d6Sryan_chen .probe = aspeed_spi_probe, 1107499853d6Sryan_chen }; 1108