1 /* 2 * (C) Copyright 2012 Samsung Electronics 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 */ 10 11 #ifndef __WM8994_REGISTERS_H__ 12 #define __WM8994_REGISTERS_H__ 13 14 /* 15 * Register values. 16 */ 17 #define WM8994_SOFTWARE_RESET 0x00 18 #define WM8994_POWER_MANAGEMENT_1 0x01 19 #define WM8994_POWER_MANAGEMENT_2 0x02 20 #define WM8994_POWER_MANAGEMENT_5 0x05 21 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C 22 #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 23 #define WM8994_OUTPUT_MIXER_1 0x2D 24 #define WM8994_OUTPUT_MIXER_2 0x2E 25 #define WM8994_CHARGE_PUMP_1 0x4C 26 #define WM8994_DC_SERVO_1 0x54 27 #define WM8994_ANALOGUE_HP_1 0x60 28 #define WM8994_CHIP_REVISION 0x100 29 #define WM8994_AIF1_CLOCKING_1 0x200 30 #define WM8994_AIF1_CLOCKING_2 0x201 31 #define WM8994_AIF2_CLOCKING_1 0x204 32 #define WM8994_CLOCKING_1 0x208 33 #define WM8994_CLOCKING_2 0x209 34 #define WM8994_AIF1_RATE 0x210 35 #define WM8994_AIF2_RATE 0x211 36 #define WM8994_RATE_STATUS 0x212 37 #define WM8994_AIF1_CONTROL_1 0x300 38 #define WM8994_AIF1_CONTROL_2 0x301 39 #define WM8994_AIF1_MASTER_SLAVE 0x302 40 #define WM8994_AIF1_BCLK 0x303 41 #define WM8994_AIF2_CONTROL_1 0x310 42 #define WM8994_AIF2_CONTROL_2 0x311 43 #define WM8994_AIF2_MASTER_SLAVE 0x312 44 #define WM8994_AIF2_BCLK 0x313 45 #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 46 #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 47 #define WM8994_AIF2_DAC_FILTERS_1 0x520 48 #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 49 #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 50 #define WM8994_DAC1_LEFT_VOLUME 0x610 51 #define WM8994_DAC1_RIGHT_VOLUME 0x611 52 #define WM8994_GPIO_3 0x702 53 #define WM8994_GPIO_4 0x703 54 #define WM8994_GPIO_5 0x704 55 56 /* 57 * Field Definitions. 58 */ 59 60 /* 61 * R0 (0x00) - Software Reset 62 */ 63 /* SW_RESET */ 64 #define WM8994_SW_RESET 1 65 /* 66 * R1 (0x01) - Power Management (1) 67 */ 68 /* HPOUT1L_ENA */ 69 #define WM8994_HPOUT1L_ENA 0x0200 70 /* HPOUT1L_ENA */ 71 #define WM8994_HPOUT1L_ENA_MASK 0x0200 72 /* HPOUT1R_ENA */ 73 #define WM8994_HPOUT1R_ENA 0x0100 74 /* HPOUT1R_ENA */ 75 #define WM8994_HPOUT1R_ENA_MASK 0x0100 76 /* VMID_SEL - [2:1] */ 77 #define WM8994_VMID_SEL_MASK 0x0006 78 /* BIAS_ENA */ 79 #define WM8994_BIAS_ENA 0x0001 80 /* BIAS_ENA */ 81 #define WM8994_BIAS_ENA_MASK 0x0001 82 83 /* 84 * R2 (0x02) - Power Management (2) 85 */ 86 /* OPCLK_ENA */ 87 #define WM8994_OPCLK_ENA 0x0800 88 89 /* 90 * R5 (0x05) - Power Management (5) 91 */ 92 /* AIF2DACL_ENA */ 93 #define WM8994_AIF2DACL_ENA 0x2000 94 #define WM8994_AIF2DACL_ENA_MASK 0x2000 95 /* AIF2DACR_ENA */ 96 #define WM8994_AIF2DACR_ENA 0x1000 97 #define WM8994_AIF2DACR_ENA_MASK 0x1000 98 /* DAC1L_ENA */ 99 #define WM8994_DAC1L_ENA 0x0002 100 #define WM8994_DAC1L_ENA_MASK 0x0002 101 /* DAC1R_ENA */ 102 #define WM8994_DAC1R_ENA 0x0001 103 #define WM8994_DAC1R_ENA_MASK 0x0001 104 105 /* 106 * R45 (0x2D) - Output Mixer (1) 107 */ 108 /* DAC1L_TO_HPOUT1L */ 109 #define WM8994_DAC1L_TO_HPOUT1L 0x0100 110 #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 111 112 /* 113 * R46 (0x2E) - Output Mixer (2) 114 */ 115 /* DAC1R_TO_HPOUT1R */ 116 #define WM8994_DAC1R_TO_HPOUT1R 0x0100 117 #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 118 119 /* 120 * R76 (0x4C) - Charge Pump (1) 121 */ 122 /* CP_ENA */ 123 #define WM8994_CP_ENA 0x8000 124 #define WM8994_CP_ENA_MASK 0x8000 125 /* 126 * R84 (0x54) - DC Servo (1) 127 */ 128 /* DCS_ENA_CHAN_1 */ 129 #define WM8994_DCS_ENA_CHAN_1 0x0002 130 #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 131 /* DCS_ENA_CHAN_0 */ 132 #define WM8994_DCS_ENA_CHAN_0 0x0001 133 #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 134 135 /* 136 * R96 (0x60) - Analogue HP (1) 137 */ 138 /* HPOUT1L_RMV_SHORT */ 139 #define WM8994_HPOUT1L_RMV_SHORT 0x0080 140 #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 141 /* HPOUT1L_OUTP */ 142 #define WM8994_HPOUT1L_OUTP 0x0040 143 #define WM8994_HPOUT1L_OUTP_MASK 0x0040 144 /* HPOUT1L_DLY */ 145 #define WM8994_HPOUT1L_DLY 0x0020 146 #define WM8994_HPOUT1L_DLY_MASK 0x0020 147 /* HPOUT1R_RMV_SHORT */ 148 #define WM8994_HPOUT1R_RMV_SHORT 0x0008 149 #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 150 /* HPOUT1R_OUTP */ 151 #define WM8994_HPOUT1R_OUTP 0x0004 152 #define WM8994_HPOUT1R_OUTP_MASK 0x0004 153 /* HPOUT1R_DLY */ 154 #define WM8994_HPOUT1R_DLY 0x0002 155 #define WM8994_HPOUT1R_DLY_MASK 0x0002 156 157 /* 158 * R512 (0x200) - AIF1 Clocking (1) 159 */ 160 /* AIF1CLK_SRC - [4:3] */ 161 #define WM8994_AIF1CLK_SRC_MASK 0x0018 162 /* AIF1CLK_DIV */ 163 #define WM8994_AIF1CLK_DIV 0x0002 164 /* AIF1CLK_ENA */ 165 #define WM8994_AIF1CLK_ENA 0x0001 166 #define WM8994_AIF1CLK_ENA_MASK 0x0001 167 168 /* 169 * R517 (0x205) - AIF2 Clocking (2) 170 */ 171 /* AIF2DAC_DIV - [5:3] */ 172 #define WM8994_AIF2DAC_DIV_MASK 0x0038 173 174 /* 175 * R520 (0x208) - Clocking (1) 176 */ 177 /* AIF2DSPCLK_ENA */ 178 #define WM8994_AIF2DSPCLK_ENA 0x0004 179 #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 180 /* SYSDSPCLK_ENA */ 181 #define WM8994_SYSDSPCLK_ENA 0x0002 182 #define WM8994_SYSDSPCLK_ENA_MASK 0x0002 183 /* SYSCLK_SRC */ 184 #define WM8994_SYSCLK_SRC 0x0001 185 186 /* 187 * R521 (0x209) - Clocking (2) 188 */ 189 /* OPCLK_DIV - [2:0] */ 190 #define WM8994_OPCLK_DIV_MASK 0x0007 191 192 /* 193 * R528 (0x210) - AIF1 Rate 194 */ 195 /* AIF1_SR - [7:4] */ 196 #define WM8994_AIF1_SR_MASK 0x00F0 197 #define WM8994_AIF1_SR_SHIFT 4 198 /* AIF1CLK_RATE - [3:0] */ 199 #define WM8994_AIF1CLK_RATE_MASK 0x000F 200 201 /* 202 * R768 (0x300) - AIF1 Control (1) 203 */ 204 /* AIF1_BCLK_INV */ 205 #define WM8994_AIF1_BCLK_INV 0x0100 206 /* AIF1_LRCLK_INV */ 207 #define WM8994_AIF1_LRCLK_INV 0x0080 208 #define WM8994_AIF1_LRCLK_INV_MASK 0x0080 209 /* AIF1_WL - [6:5] */ 210 #define WM8994_AIF1_WL_MASK 0x0060 211 /* AIF1_FMT - [4:3] */ 212 #define WM8994_AIF1_FMT_MASK 0x0018 213 214 /* 215 * R769 (0x301) - AIF1 Control (2) 216 */ 217 /* AIF1_MONO */ 218 #define WM8994_AIF1_MONO 0x0100 219 220 /* 221 * R770 (0x302) - AIF1 Master/Slave 222 */ 223 /* AIF1_MSTR */ 224 #define WM8994_AIF1_MSTR 0x4000 225 #define WM8994_AIF1_MSTR_MASK 0x4000 226 227 /* 228 * R771 (0x303) - AIF1 BCLK 229 */ 230 /* AIF1_BCLK_DIV - [8:4] */ 231 #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 232 #define WM8994_AIF1_BCLK_DIV_SHIFT 4 233 234 /* 235 * R1282 (0x502) - AIF2 DAC Left Volume 236 */ 237 /* AIF2DAC_VU */ 238 #define WM8994_AIF2DAC_VU 0x0100 239 #define WM8994_AIF2DAC_VU_MASK 0x0100 240 /* AIF2DACL_VOL - [7:0] */ 241 #define WM8994_AIF2DACL_VOL_MASK 0x00FF 242 243 /* 244 * R1283 (0x503) - AIF2 DAC Right Volume 245 */ 246 /* AIF2DACR_VOL - [7:0] */ 247 #define WM8994_AIF2DACR_VOL_MASK 0x00FF 248 249 /* 250 * R1312 (0x520) - AIF2 DAC Filters (1) 251 */ 252 /* AIF2DAC_MUTE */ 253 #define WM8994_AIF2DAC_MUTE_MASK 0x0200 254 255 /* 256 * R1537 (0x601) - DAC1 Left Mixer Routing 257 */ 258 /* AIF2DACL_TO_DAC1L */ 259 #define WM8994_AIF2DACL_TO_DAC1L 0x0004 260 #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 261 262 /* 263 * R1538 (0x602) - DAC1 Right Mixer Routing 264 */ 265 /* AIF2DACR_TO_DAC1R */ 266 #define WM8994_AIF2DACR_TO_DAC1R 0x0004 267 #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 268 269 /* 270 * R1552 (0x610) - DAC1 Left Volume 271 */ 272 /* DAC1L_MUTE */ 273 #define WM8994_DAC1L_MUTE_MASK 0x0200 274 /* DAC1_VU */ 275 #define WM8994_DAC1_VU 0x0100 276 #define WM8994_DAC1_VU_MASK 0x0100 277 /* DAC1L_VOL - [7:0] */ 278 #define WM8994_DAC1L_VOL_MASK 0x00FF 279 280 /* 281 * R1553 (0x611) - DAC1 Right Volume 282 */ 283 /* DAC1R_MUTE */ 284 #define WM8994_DAC1R_MUTE_MASK 0x0200 285 /* DAC1R_VOL - [7:0] */ 286 #define WM8994_DAC1R_VOL_MASK 0x00FF 287 288 /* 289 * GPIO 290 */ 291 /* OUTPUT PIN */ 292 #define WM8994_GPIO_DIR_OUTPUT 0x8000 293 /* GPIO PIN MASK */ 294 #define WM8994_GPIO_DIR_MASK 0xFFE0 295 /* I2S CLK */ 296 #define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000 297 /* GPn FN */ 298 #define WM8994_GPIO_FUNCTION_MASK 0x001F 299 #endif 300