1 /* 2 * (C) Copyright 2012 Samsung Electronics 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __WM8994_REGISTERS_H__ 8 #define __WM8994_REGISTERS_H__ 9 10 /* 11 * Register values. 12 */ 13 #define WM8994_SOFTWARE_RESET 0x00 14 #define WM8994_POWER_MANAGEMENT_1 0x01 15 #define WM8994_POWER_MANAGEMENT_2 0x02 16 #define WM8994_POWER_MANAGEMENT_5 0x05 17 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C 18 #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 19 #define WM8994_OUTPUT_MIXER_1 0x2D 20 #define WM8994_OUTPUT_MIXER_2 0x2E 21 #define WM8994_CHARGE_PUMP_1 0x4C 22 #define WM8994_DC_SERVO_1 0x54 23 #define WM8994_ANALOGUE_HP_1 0x60 24 #define WM8994_CHIP_REVISION 0x100 25 #define WM8994_AIF1_CLOCKING_1 0x200 26 #define WM8994_AIF1_CLOCKING_2 0x201 27 #define WM8994_AIF2_CLOCKING_1 0x204 28 #define WM8994_CLOCKING_1 0x208 29 #define WM8994_CLOCKING_2 0x209 30 #define WM8994_AIF1_RATE 0x210 31 #define WM8994_AIF2_RATE 0x211 32 #define WM8994_RATE_STATUS 0x212 33 #define WM8994_AIF1_CONTROL_1 0x300 34 #define WM8994_AIF1_CONTROL_2 0x301 35 #define WM8994_AIF1_MASTER_SLAVE 0x302 36 #define WM8994_AIF1_BCLK 0x303 37 #define WM8994_AIF2_CONTROL_1 0x310 38 #define WM8994_AIF2_CONTROL_2 0x311 39 #define WM8994_AIF2_MASTER_SLAVE 0x312 40 #define WM8994_AIF2_BCLK 0x313 41 #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 42 #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 43 #define WM8994_AIF2_DAC_FILTERS_1 0x520 44 #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 45 #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 46 #define WM8994_DAC1_LEFT_VOLUME 0x610 47 #define WM8994_DAC1_RIGHT_VOLUME 0x611 48 #define WM8994_GPIO_3 0x702 49 #define WM8994_GPIO_4 0x703 50 #define WM8994_GPIO_5 0x704 51 52 /* 53 * Field Definitions. 54 */ 55 56 /* 57 * R0 (0x00) - Software Reset 58 */ 59 /* SW_RESET */ 60 #define WM8994_SW_RESET 1 61 /* 62 * R1 (0x01) - Power Management (1) 63 */ 64 /* HPOUT1L_ENA */ 65 #define WM8994_HPOUT1L_ENA 0x0200 66 /* HPOUT1L_ENA */ 67 #define WM8994_HPOUT1L_ENA_MASK 0x0200 68 /* HPOUT1R_ENA */ 69 #define WM8994_HPOUT1R_ENA 0x0100 70 /* HPOUT1R_ENA */ 71 #define WM8994_HPOUT1R_ENA_MASK 0x0100 72 /* VMID_SEL - [2:1] */ 73 #define WM8994_VMID_SEL_MASK 0x0006 74 /* BIAS_ENA */ 75 #define WM8994_BIAS_ENA 0x0001 76 /* BIAS_ENA */ 77 #define WM8994_BIAS_ENA_MASK 0x0001 78 79 /* 80 * R2 (0x02) - Power Management (2) 81 */ 82 /* OPCLK_ENA */ 83 #define WM8994_OPCLK_ENA 0x0800 84 85 /* 86 * R5 (0x05) - Power Management (5) 87 */ 88 /* AIF2DACL_ENA */ 89 #define WM8994_AIF2DACL_ENA 0x2000 90 #define WM8994_AIF2DACL_ENA_MASK 0x2000 91 /* AIF2DACR_ENA */ 92 #define WM8994_AIF2DACR_ENA 0x1000 93 #define WM8994_AIF2DACR_ENA_MASK 0x1000 94 /* DAC1L_ENA */ 95 #define WM8994_DAC1L_ENA 0x0002 96 #define WM8994_DAC1L_ENA_MASK 0x0002 97 /* DAC1R_ENA */ 98 #define WM8994_DAC1R_ENA 0x0001 99 #define WM8994_DAC1R_ENA_MASK 0x0001 100 101 /* 102 * R45 (0x2D) - Output Mixer (1) 103 */ 104 /* DAC1L_TO_HPOUT1L */ 105 #define WM8994_DAC1L_TO_HPOUT1L 0x0100 106 #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 107 108 /* 109 * R46 (0x2E) - Output Mixer (2) 110 */ 111 /* DAC1R_TO_HPOUT1R */ 112 #define WM8994_DAC1R_TO_HPOUT1R 0x0100 113 #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 114 115 /* 116 * R76 (0x4C) - Charge Pump (1) 117 */ 118 /* CP_ENA */ 119 #define WM8994_CP_ENA 0x8000 120 #define WM8994_CP_ENA_MASK 0x8000 121 /* 122 * R84 (0x54) - DC Servo (1) 123 */ 124 /* DCS_ENA_CHAN_1 */ 125 #define WM8994_DCS_ENA_CHAN_1 0x0002 126 #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 127 /* DCS_ENA_CHAN_0 */ 128 #define WM8994_DCS_ENA_CHAN_0 0x0001 129 #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 130 131 /* 132 * R96 (0x60) - Analogue HP (1) 133 */ 134 /* HPOUT1L_RMV_SHORT */ 135 #define WM8994_HPOUT1L_RMV_SHORT 0x0080 136 #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 137 /* HPOUT1L_OUTP */ 138 #define WM8994_HPOUT1L_OUTP 0x0040 139 #define WM8994_HPOUT1L_OUTP_MASK 0x0040 140 /* HPOUT1L_DLY */ 141 #define WM8994_HPOUT1L_DLY 0x0020 142 #define WM8994_HPOUT1L_DLY_MASK 0x0020 143 /* HPOUT1R_RMV_SHORT */ 144 #define WM8994_HPOUT1R_RMV_SHORT 0x0008 145 #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 146 /* HPOUT1R_OUTP */ 147 #define WM8994_HPOUT1R_OUTP 0x0004 148 #define WM8994_HPOUT1R_OUTP_MASK 0x0004 149 /* HPOUT1R_DLY */ 150 #define WM8994_HPOUT1R_DLY 0x0002 151 #define WM8994_HPOUT1R_DLY_MASK 0x0002 152 153 /* 154 * R512 (0x200) - AIF1 Clocking (1) 155 */ 156 /* AIF1CLK_SRC - [4:3] */ 157 #define WM8994_AIF1CLK_SRC_MASK 0x0018 158 /* AIF1CLK_DIV */ 159 #define WM8994_AIF1CLK_DIV 0x0002 160 /* AIF1CLK_ENA */ 161 #define WM8994_AIF1CLK_ENA 0x0001 162 #define WM8994_AIF1CLK_ENA_MASK 0x0001 163 164 /* 165 * R517 (0x205) - AIF2 Clocking (2) 166 */ 167 /* AIF2DAC_DIV - [5:3] */ 168 #define WM8994_AIF2DAC_DIV_MASK 0x0038 169 170 /* 171 * R520 (0x208) - Clocking (1) 172 */ 173 /* AIF2DSPCLK_ENA */ 174 #define WM8994_AIF2DSPCLK_ENA 0x0004 175 #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 176 /* SYSDSPCLK_ENA */ 177 #define WM8994_SYSDSPCLK_ENA 0x0002 178 #define WM8994_SYSDSPCLK_ENA_MASK 0x0002 179 /* SYSCLK_SRC */ 180 #define WM8994_SYSCLK_SRC 0x0001 181 182 /* 183 * R521 (0x209) - Clocking (2) 184 */ 185 /* OPCLK_DIV - [2:0] */ 186 #define WM8994_OPCLK_DIV_MASK 0x0007 187 188 /* 189 * R528 (0x210) - AIF1 Rate 190 */ 191 /* AIF1_SR - [7:4] */ 192 #define WM8994_AIF1_SR_MASK 0x00F0 193 #define WM8994_AIF1_SR_SHIFT 4 194 /* AIF1CLK_RATE - [3:0] */ 195 #define WM8994_AIF1CLK_RATE_MASK 0x000F 196 197 /* 198 * R768 (0x300) - AIF1 Control (1) 199 */ 200 /* AIF1_BCLK_INV */ 201 #define WM8994_AIF1_BCLK_INV 0x0100 202 /* AIF1_LRCLK_INV */ 203 #define WM8994_AIF1_LRCLK_INV 0x0080 204 #define WM8994_AIF1_LRCLK_INV_MASK 0x0080 205 /* AIF1_WL - [6:5] */ 206 #define WM8994_AIF1_WL_MASK 0x0060 207 /* AIF1_FMT - [4:3] */ 208 #define WM8994_AIF1_FMT_MASK 0x0018 209 210 /* 211 * R769 (0x301) - AIF1 Control (2) 212 */ 213 /* AIF1_MONO */ 214 #define WM8994_AIF1_MONO 0x0100 215 216 /* 217 * R770 (0x302) - AIF1 Master/Slave 218 */ 219 /* AIF1_MSTR */ 220 #define WM8994_AIF1_MSTR 0x4000 221 #define WM8994_AIF1_MSTR_MASK 0x4000 222 223 /* 224 * R771 (0x303) - AIF1 BCLK 225 */ 226 /* AIF1_BCLK_DIV - [8:4] */ 227 #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 228 #define WM8994_AIF1_BCLK_DIV_SHIFT 4 229 230 /* 231 * R1282 (0x502) - AIF2 DAC Left Volume 232 */ 233 /* AIF2DAC_VU */ 234 #define WM8994_AIF2DAC_VU 0x0100 235 #define WM8994_AIF2DAC_VU_MASK 0x0100 236 /* AIF2DACL_VOL - [7:0] */ 237 #define WM8994_AIF2DACL_VOL_MASK 0x00FF 238 239 /* 240 * R1283 (0x503) - AIF2 DAC Right Volume 241 */ 242 /* AIF2DACR_VOL - [7:0] */ 243 #define WM8994_AIF2DACR_VOL_MASK 0x00FF 244 245 /* 246 * R1312 (0x520) - AIF2 DAC Filters (1) 247 */ 248 /* AIF2DAC_MUTE */ 249 #define WM8994_AIF2DAC_MUTE_MASK 0x0200 250 251 /* 252 * R1537 (0x601) - DAC1 Left Mixer Routing 253 */ 254 /* AIF2DACL_TO_DAC1L */ 255 #define WM8994_AIF2DACL_TO_DAC1L 0x0004 256 #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 257 258 /* 259 * R1538 (0x602) - DAC1 Right Mixer Routing 260 */ 261 /* AIF2DACR_TO_DAC1R */ 262 #define WM8994_AIF2DACR_TO_DAC1R 0x0004 263 #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 264 265 /* 266 * R1552 (0x610) - DAC1 Left Volume 267 */ 268 /* DAC1L_MUTE */ 269 #define WM8994_DAC1L_MUTE_MASK 0x0200 270 /* DAC1_VU */ 271 #define WM8994_DAC1_VU 0x0100 272 #define WM8994_DAC1_VU_MASK 0x0100 273 /* DAC1L_VOL - [7:0] */ 274 #define WM8994_DAC1L_VOL_MASK 0x00FF 275 276 /* 277 * R1553 (0x611) - DAC1 Right Volume 278 */ 279 /* DAC1R_MUTE */ 280 #define WM8994_DAC1R_MUTE_MASK 0x0200 281 /* DAC1R_VOL - [7:0] */ 282 #define WM8994_DAC1R_VOL_MASK 0x00FF 283 284 /* 285 * GPIO 286 */ 287 /* OUTPUT PIN */ 288 #define WM8994_GPIO_DIR_OUTPUT 0x8000 289 /* GPIO PIN MASK */ 290 #define WM8994_GPIO_DIR_MASK 0xFFE0 291 /* I2S CLK */ 292 #define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000 293 /* GPn FN */ 294 #define WM8994_GPIO_FUNCTION_MASK 0x001F 295 #endif 296