1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Samsung Electronics 4 * R. Chadrasekar <rcsekar@samsung.com> 5 */ 6 7 #ifndef __WM8994_H__ 8 #define __WM8994_H__ 9 10 /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 11 #define WM8994_SYSCLK_MCLK1 1 12 #define WM8994_SYSCLK_MCLK2 2 13 #define WM8994_SYSCLK_FLL1 3 14 #define WM8994_SYSCLK_FLL2 4 15 16 /* Avilable audi interface ports in wm8994 codec */ 17 enum en_audio_interface { 18 WM8994_AIF1, 19 WM8994_AIF2, 20 WM8994_AIF3 21 }; 22 23 /* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */ 24 #define WM8994_SYSCLK_OPCLK 5 25 26 #define WM8994_FLL1 1 27 #define WM8994_FLL2 2 28 29 #define WM8994_FLL_SRC_MCLK1 1 30 #define WM8994_FLL_SRC_MCLK2 2 31 #define WM8994_FLL_SRC_LRCLK 3 32 #define WM8994_FLL_SRC_BCLK 4 33 34 /* maximum available digital interfac in the dac to configure */ 35 #define WM8994_MAX_AIF 2 36 37 #define WM8994_MAX_INPUT_CLK_FREQ 13500000 38 #define WM8994_ID 0x8994 39 40 enum wm8994_vmid_mode { 41 WM8994_VMID_NORMAL, 42 WM8994_VMID_FORCE, 43 }; 44 45 /* wm 8994 family devices */ 46 enum wm8994_type { 47 WM8994 = 0, 48 WM8958 = 1, 49 WM1811 = 2, 50 }; 51 52 /* 53 * intialise wm8994 sound codec device for the given configuration 54 * 55 * @param blob FDT node for codec values 56 * @param aif_id enum value of codec interface port in which 57 * soc i2s is connected 58 * @param sampling_rate Sampling rate ranges between from 8khz to 96khz 59 * @param mclk_freq Master clock frequency. 60 * @param bits_per_sample bits per Sample can be 16 or 24 61 * @param channels Number of channnels, maximum 2 62 * 63 * @returns -1 for error and 0 Success. 64 */ 65 int wm8994_init(const void *blob, enum en_audio_interface aif_id, 66 int sampling_rate, int mclk_freq, 67 int bits_per_sample, unsigned int channels); 68 #endif /*__WM8994_H__ */ 69