1a2d8e0a7SRajeshwari Shinde /* 2a2d8e0a7SRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics 3a2d8e0a7SRajeshwari Shinde * R. Chadrasekar <rcsekar@samsung.com> 4a2d8e0a7SRajeshwari Shinde * 5a2d8e0a7SRajeshwari Shinde * See file CREDITS for list of people who contributed to this 6a2d8e0a7SRajeshwari Shinde * project. 7a2d8e0a7SRajeshwari Shinde * 8a2d8e0a7SRajeshwari Shinde * This program is free software; you can redistribute it and/or 9a2d8e0a7SRajeshwari Shinde * modify it under the terms of the GNU General Public License as 10a2d8e0a7SRajeshwari Shinde * published by the Free Software Foundation; either version 2 of 11a2d8e0a7SRajeshwari Shinde * the License, or (at your option) any later version. 12a2d8e0a7SRajeshwari Shinde * 13a2d8e0a7SRajeshwari Shinde * This program is distributed in the hope that it will be useful, 14a2d8e0a7SRajeshwari Shinde * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a2d8e0a7SRajeshwari Shinde * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a2d8e0a7SRajeshwari Shinde * GNU General Public License for more details. 17a2d8e0a7SRajeshwari Shinde * 18a2d8e0a7SRajeshwari Shinde * You should have received a copy of the GNU General Public License 19a2d8e0a7SRajeshwari Shinde * along with this program; if not, write to the Free Software 20a2d8e0a7SRajeshwari Shinde * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a2d8e0a7SRajeshwari Shinde * MA 02111-1307 USA 22a2d8e0a7SRajeshwari Shinde */ 23a2d8e0a7SRajeshwari Shinde 24a2d8e0a7SRajeshwari Shinde #ifndef __WM8994_H__ 25a2d8e0a7SRajeshwari Shinde #define __WM8994_H__ 26a2d8e0a7SRajeshwari Shinde 27a2d8e0a7SRajeshwari Shinde /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 28a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_MCLK1 1 29a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_MCLK2 2 30a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_FLL1 3 31a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_FLL2 4 32a2d8e0a7SRajeshwari Shinde 33a2d8e0a7SRajeshwari Shinde /* Avilable audi interface ports in wm8994 codec */ 34a2d8e0a7SRajeshwari Shinde enum en_audio_interface { 35a2d8e0a7SRajeshwari Shinde WM8994_AIF1 = 1, 36a2d8e0a7SRajeshwari Shinde WM8994_AIF2, 37a2d8e0a7SRajeshwari Shinde WM8994_AIF3 38a2d8e0a7SRajeshwari Shinde }; 39a2d8e0a7SRajeshwari Shinde 40a2d8e0a7SRajeshwari Shinde /* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */ 41a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_OPCLK 5 42a2d8e0a7SRajeshwari Shinde 43a2d8e0a7SRajeshwari Shinde #define WM8994_FLL1 1 44a2d8e0a7SRajeshwari Shinde #define WM8994_FLL2 2 45a2d8e0a7SRajeshwari Shinde 46a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_MCLK1 1 47a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_MCLK2 2 48a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_LRCLK 3 49a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_BCLK 4 50a2d8e0a7SRajeshwari Shinde 51a2d8e0a7SRajeshwari Shinde /* maximum available digital interfac in the dac to configure */ 52a2d8e0a7SRajeshwari Shinde #define WM8994_MAX_AIF 2 53a2d8e0a7SRajeshwari Shinde 54a2d8e0a7SRajeshwari Shinde #define WM8994_MAX_INPUT_CLK_FREQ 13500000 55a2d8e0a7SRajeshwari Shinde #define WM8994_ID 0x8994 56a2d8e0a7SRajeshwari Shinde 57a2d8e0a7SRajeshwari Shinde enum wm8994_vmid_mode { 58a2d8e0a7SRajeshwari Shinde WM8994_VMID_NORMAL, 59a2d8e0a7SRajeshwari Shinde WM8994_VMID_FORCE, 60a2d8e0a7SRajeshwari Shinde }; 61a2d8e0a7SRajeshwari Shinde 62a2d8e0a7SRajeshwari Shinde /* wm 8994 family devices */ 63a2d8e0a7SRajeshwari Shinde enum wm8994_type { 64a2d8e0a7SRajeshwari Shinde WM8994 = 0, 65a2d8e0a7SRajeshwari Shinde WM8958 = 1, 66a2d8e0a7SRajeshwari Shinde WM1811 = 2, 67a2d8e0a7SRajeshwari Shinde }; 68a2d8e0a7SRajeshwari Shinde 69a2d8e0a7SRajeshwari Shinde /* 70a2d8e0a7SRajeshwari Shinde * intialise wm8994 sound codec device for the given configuration 71a2d8e0a7SRajeshwari Shinde * 72*6647c7acSRajeshwari Shinde * @param blob FDT node for codec values 73a2d8e0a7SRajeshwari Shinde * @param aif_id enum value of codec interface port in which 74a2d8e0a7SRajeshwari Shinde * soc i2s is connected 75a2d8e0a7SRajeshwari Shinde * @param sampling_rate Sampling rate ranges between from 8khz to 96khz 76a2d8e0a7SRajeshwari Shinde * @param mclk_freq Master clock frequency. 77a2d8e0a7SRajeshwari Shinde * @param bits_per_sample bits per Sample can be 16 or 24 78a2d8e0a7SRajeshwari Shinde * @param channels Number of channnels, maximum 2 79a2d8e0a7SRajeshwari Shinde * 80a2d8e0a7SRajeshwari Shinde * @returns -1 for error and 0 Success. 81a2d8e0a7SRajeshwari Shinde */ 82*6647c7acSRajeshwari Shinde int wm8994_init(const void *blob, enum en_audio_interface aif_id, 83a2d8e0a7SRajeshwari Shinde int sampling_rate, int mclk_freq, 84a2d8e0a7SRajeshwari Shinde int bits_per_sample, unsigned int channels); 85a2d8e0a7SRajeshwari Shinde #endif /*__WM8994_H__ */ 86