183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a2d8e0a7SRajeshwari Shinde /* 3a2d8e0a7SRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics 4a2d8e0a7SRajeshwari Shinde * R. Chadrasekar <rcsekar@samsung.com> 5a2d8e0a7SRajeshwari Shinde */ 6a2d8e0a7SRajeshwari Shinde 7a2d8e0a7SRajeshwari Shinde #ifndef __WM8994_H__ 8a2d8e0a7SRajeshwari Shinde #define __WM8994_H__ 9a2d8e0a7SRajeshwari Shinde 10a2d8e0a7SRajeshwari Shinde /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 11a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_MCLK1 1 12a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_MCLK2 2 13a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_FLL1 3 14a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_FLL2 4 15a2d8e0a7SRajeshwari Shinde 16a2d8e0a7SRajeshwari Shinde /* Avilable audi interface ports in wm8994 codec */ 17a2d8e0a7SRajeshwari Shinde enum en_audio_interface { 18*6c986cfeSSimon Glass WM8994_AIF1, 19a2d8e0a7SRajeshwari Shinde WM8994_AIF2, 20a2d8e0a7SRajeshwari Shinde WM8994_AIF3 21a2d8e0a7SRajeshwari Shinde }; 22a2d8e0a7SRajeshwari Shinde 23a2d8e0a7SRajeshwari Shinde /* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */ 24a2d8e0a7SRajeshwari Shinde #define WM8994_SYSCLK_OPCLK 5 25a2d8e0a7SRajeshwari Shinde 26a2d8e0a7SRajeshwari Shinde #define WM8994_FLL1 1 27a2d8e0a7SRajeshwari Shinde #define WM8994_FLL2 2 28a2d8e0a7SRajeshwari Shinde 29a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_MCLK1 1 30a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_MCLK2 2 31a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_LRCLK 3 32a2d8e0a7SRajeshwari Shinde #define WM8994_FLL_SRC_BCLK 4 33a2d8e0a7SRajeshwari Shinde 34a2d8e0a7SRajeshwari Shinde /* maximum available digital interfac in the dac to configure */ 35a2d8e0a7SRajeshwari Shinde #define WM8994_MAX_AIF 2 36a2d8e0a7SRajeshwari Shinde 37a2d8e0a7SRajeshwari Shinde #define WM8994_MAX_INPUT_CLK_FREQ 13500000 38a2d8e0a7SRajeshwari Shinde #define WM8994_ID 0x8994 39a2d8e0a7SRajeshwari Shinde 40a2d8e0a7SRajeshwari Shinde enum wm8994_vmid_mode { 41a2d8e0a7SRajeshwari Shinde WM8994_VMID_NORMAL, 42a2d8e0a7SRajeshwari Shinde WM8994_VMID_FORCE, 43a2d8e0a7SRajeshwari Shinde }; 44a2d8e0a7SRajeshwari Shinde 45a2d8e0a7SRajeshwari Shinde /* wm 8994 family devices */ 46a2d8e0a7SRajeshwari Shinde enum wm8994_type { 47a2d8e0a7SRajeshwari Shinde WM8994 = 0, 48a2d8e0a7SRajeshwari Shinde WM8958 = 1, 49a2d8e0a7SRajeshwari Shinde WM1811 = 2, 50a2d8e0a7SRajeshwari Shinde }; 51a2d8e0a7SRajeshwari Shinde 52a2d8e0a7SRajeshwari Shinde /* 53a2d8e0a7SRajeshwari Shinde * intialise wm8994 sound codec device for the given configuration 54a2d8e0a7SRajeshwari Shinde * 556647c7acSRajeshwari Shinde * @param blob FDT node for codec values 56a2d8e0a7SRajeshwari Shinde * @param aif_id enum value of codec interface port in which 57a2d8e0a7SRajeshwari Shinde * soc i2s is connected 58a2d8e0a7SRajeshwari Shinde * @param sampling_rate Sampling rate ranges between from 8khz to 96khz 59a2d8e0a7SRajeshwari Shinde * @param mclk_freq Master clock frequency. 60a2d8e0a7SRajeshwari Shinde * @param bits_per_sample bits per Sample can be 16 or 24 61a2d8e0a7SRajeshwari Shinde * @param channels Number of channnels, maximum 2 62a2d8e0a7SRajeshwari Shinde * 63a2d8e0a7SRajeshwari Shinde * @returns -1 for error and 0 Success. 64a2d8e0a7SRajeshwari Shinde */ 656647c7acSRajeshwari Shinde int wm8994_init(const void *blob, enum en_audio_interface aif_id, 66a2d8e0a7SRajeshwari Shinde int sampling_rate, int mclk_freq, 67a2d8e0a7SRajeshwari Shinde int bits_per_sample, unsigned int channels); 68a2d8e0a7SRajeshwari Shinde #endif /*__WM8994_H__ */ 69