1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * R. Chandrasekar <rcsekar@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <asm/arch/clk.h> 8 #include <asm/arch/cpu.h> 9 #include <asm/gpio.h> 10 #include <asm/io.h> 11 #include <common.h> 12 #include <div64.h> 13 #include <fdtdec.h> 14 #include <i2c.h> 15 #include <i2s.h> 16 #include <sound.h> 17 #include <asm/arch/sound.h> 18 #include "wm8994.h" 19 #include "wm8994_registers.h" 20 21 /* defines for wm8994 system clock selection */ 22 #define SEL_MCLK1 0x00 23 #define SEL_MCLK2 0x08 24 #define SEL_FLL1 0x10 25 #define SEL_FLL2 0x18 26 27 /* fll config to configure fll */ 28 struct wm8994_fll_config { 29 int src; /* Source */ 30 int in; /* Input frequency in Hz */ 31 int out; /* output frequency in Hz */ 32 }; 33 34 /* codec private data */ 35 struct wm8994_priv { 36 enum wm8994_type type; /* codec type of wolfson */ 37 int revision; /* Revision */ 38 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */ 39 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */ 40 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */ 41 struct wm8994_fll_config fll[2]; /* fll config to configure fll */ 42 }; 43 44 /* wm 8994 supported sampling rate values */ 45 static unsigned int src_rate[] = { 46 8000, 11025, 12000, 16000, 22050, 24000, 47 32000, 44100, 48000, 88200, 96000 48 }; 49 50 /* op clock divisions */ 51 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 52 53 /* lr clock frame size ratio */ 54 static int fs_ratios[] = { 55 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 56 }; 57 58 /* bit clock divisors */ 59 static int bclk_divs[] = { 60 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 61 640, 880, 960, 1280, 1760, 1920 62 }; 63 64 static struct wm8994_priv g_wm8994_info; 65 static unsigned char g_wm8994_i2c_dev_addr; 66 static struct sound_codec_info g_codec_info; 67 68 /* 69 * Initialise I2C for wm 8994 70 * 71 * @param bus no i2c bus number in which wm8994 is connected 72 */ 73 static void wm8994_i2c_init(int bus_no) 74 { 75 i2c_set_bus_num(bus_no); 76 } 77 78 /* 79 * Writes value to a device register through i2c 80 * 81 * @param reg reg number to be write 82 * @param data data to be writen to the above registor 83 * 84 * @return int value 1 for change, 0 for no change or negative error code. 85 */ 86 static int wm8994_i2c_write(unsigned int reg, unsigned short data) 87 { 88 unsigned char val[2]; 89 90 val[0] = (unsigned char)((data >> 8) & 0xff); 91 val[1] = (unsigned char)(data & 0xff); 92 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data); 93 94 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 95 } 96 97 /* 98 * Read a value from a device register through i2c 99 * 100 * @param reg reg number to be read 101 * @param data address of read data to be stored 102 * 103 * @return int value 0 for success, -1 in case of error. 104 */ 105 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) 106 { 107 unsigned char val[2]; 108 int ret; 109 110 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 111 if (ret != 0) { 112 debug("%s: Error while reading register %#04x\n", 113 __func__, reg); 114 return -1; 115 } 116 117 *data = val[0]; 118 *data <<= 8; 119 *data |= val[1]; 120 121 return 0; 122 } 123 124 /* 125 * update device register bits through i2c 126 * 127 * @param reg codec register 128 * @param mask register mask 129 * @param value new value 130 * 131 * @return int value 1 if change in the register value, 132 * 0 for no change or negative error code. 133 */ 134 static int wm8994_update_bits(unsigned int reg, unsigned short mask, 135 unsigned short value) 136 { 137 int change , ret = 0; 138 unsigned short old, new; 139 140 if (wm8994_i2c_read(reg, &old) != 0) 141 return -1; 142 new = (old & ~mask) | (value & mask); 143 change = (old != new) ? 1 : 0; 144 if (change) 145 ret = wm8994_i2c_write(reg, new); 146 if (ret < 0) 147 return ret; 148 149 return change; 150 } 151 152 /* 153 * Sets i2s set format 154 * 155 * @param aif_id Interface ID 156 * @param fmt i2S format 157 * 158 * @return -1 for error and 0 Success. 159 */ 160 int wm8994_set_fmt(int aif_id, unsigned int fmt) 161 { 162 int ms_reg; 163 int aif_reg; 164 int ms = 0; 165 int aif = 0; 166 int aif_clk = 0; 167 int error = 0; 168 169 switch (aif_id) { 170 case 1: 171 ms_reg = WM8994_AIF1_MASTER_SLAVE; 172 aif_reg = WM8994_AIF1_CONTROL_1; 173 aif_clk = WM8994_AIF1_CLOCKING_1; 174 break; 175 case 2: 176 ms_reg = WM8994_AIF2_MASTER_SLAVE; 177 aif_reg = WM8994_AIF2_CONTROL_1; 178 aif_clk = WM8994_AIF2_CLOCKING_1; 179 break; 180 default: 181 debug("%s: Invalid audio interface selection\n", __func__); 182 return -1; 183 } 184 185 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 186 case SND_SOC_DAIFMT_CBS_CFS: 187 break; 188 case SND_SOC_DAIFMT_CBM_CFM: 189 ms = WM8994_AIF1_MSTR; 190 break; 191 default: 192 debug("%s: Invalid i2s master selection\n", __func__); 193 return -1; 194 } 195 196 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 197 case SND_SOC_DAIFMT_DSP_B: 198 aif |= WM8994_AIF1_LRCLK_INV; 199 case SND_SOC_DAIFMT_DSP_A: 200 aif |= 0x18; 201 break; 202 case SND_SOC_DAIFMT_I2S: 203 aif |= 0x10; 204 break; 205 case SND_SOC_DAIFMT_RIGHT_J: 206 break; 207 case SND_SOC_DAIFMT_LEFT_J: 208 aif |= 0x8; 209 break; 210 default: 211 debug("%s: Invalid i2s format selection\n", __func__); 212 return -1; 213 } 214 215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 216 case SND_SOC_DAIFMT_DSP_A: 217 case SND_SOC_DAIFMT_DSP_B: 218 /* frame inversion not valid for DSP modes */ 219 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 220 case SND_SOC_DAIFMT_NB_NF: 221 break; 222 case SND_SOC_DAIFMT_IB_NF: 223 aif |= WM8994_AIF1_BCLK_INV; 224 break; 225 default: 226 debug("%s: Invalid i2s frame inverse selection\n", 227 __func__); 228 return -1; 229 } 230 break; 231 232 case SND_SOC_DAIFMT_I2S: 233 case SND_SOC_DAIFMT_RIGHT_J: 234 case SND_SOC_DAIFMT_LEFT_J: 235 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 236 case SND_SOC_DAIFMT_NB_NF: 237 break; 238 case SND_SOC_DAIFMT_IB_IF: 239 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 240 break; 241 case SND_SOC_DAIFMT_IB_NF: 242 aif |= WM8994_AIF1_BCLK_INV; 243 break; 244 case SND_SOC_DAIFMT_NB_IF: 245 aif |= WM8994_AIF1_LRCLK_INV; 246 break; 247 default: 248 debug("%s: Invalid i2s clock polarity selection\n", 249 __func__); 250 return -1; 251 } 252 break; 253 default: 254 debug("%s: Invalid i2s format selection\n", __func__); 255 return -1; 256 } 257 258 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV | 259 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif); 260 261 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms); 262 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK, 263 WM8994_AIF1CLK_ENA); 264 if (error < 0) { 265 debug("%s: codec register access error\n", __func__); 266 return -1; 267 } 268 269 return 0; 270 } 271 272 /* 273 * Sets hw params FOR WM8994 274 * 275 * @param wm8994 wm8994 information pointer 276 * @param aif_id Audio interface ID 277 * @param sampling_rate Sampling rate 278 * @param bits_per_sample Bits per sample 279 * @param Channels Channels in the given audio input 280 * 281 * @return -1 for error and 0 Success. 282 */ 283 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, 284 unsigned int sampling_rate, unsigned int bits_per_sample, 285 unsigned int channels) 286 { 287 int aif1_reg; 288 int aif2_reg; 289 int bclk_reg; 290 int bclk = 0; 291 int rate_reg; 292 int aif1 = 0; 293 int aif2 = 0; 294 int rate_val = 0; 295 int id = aif_id - 1; 296 int i, cur_val, best_val, bclk_rate, best; 297 unsigned short reg_data; 298 int ret = 0; 299 300 switch (aif_id) { 301 case 1: 302 aif1_reg = WM8994_AIF1_CONTROL_1; 303 aif2_reg = WM8994_AIF1_CONTROL_2; 304 bclk_reg = WM8994_AIF1_BCLK; 305 rate_reg = WM8994_AIF1_RATE; 306 break; 307 case 2: 308 aif1_reg = WM8994_AIF2_CONTROL_1; 309 aif2_reg = WM8994_AIF2_CONTROL_2; 310 bclk_reg = WM8994_AIF2_BCLK; 311 rate_reg = WM8994_AIF2_RATE; 312 break; 313 default: 314 return -1; 315 } 316 317 bclk_rate = sampling_rate * 32; 318 switch (bits_per_sample) { 319 case 16: 320 bclk_rate *= 16; 321 break; 322 case 20: 323 bclk_rate *= 20; 324 aif1 |= 0x20; 325 break; 326 case 24: 327 bclk_rate *= 24; 328 aif1 |= 0x40; 329 break; 330 case 32: 331 bclk_rate *= 32; 332 aif1 |= 0x60; 333 break; 334 default: 335 return -1; 336 } 337 338 /* Try to find an appropriate sample rate; look for an exact match. */ 339 for (i = 0; i < ARRAY_SIZE(src_rate); i++) 340 if (src_rate[i] == sampling_rate) 341 break; 342 343 if (i == ARRAY_SIZE(src_rate)) { 344 debug("%s: Could not get the best matching samplingrate\n", 345 __func__); 346 return -1; 347 } 348 349 rate_val |= i << WM8994_AIF1_SR_SHIFT; 350 351 /* AIFCLK/fs ratio; look for a close match in either direction */ 352 best = 0; 353 best_val = abs((fs_ratios[0] * sampling_rate) 354 - wm8994->aifclk[id]); 355 356 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 357 cur_val = abs((fs_ratios[i] * sampling_rate) 358 - wm8994->aifclk[id]); 359 if (cur_val >= best_val) 360 continue; 361 best = i; 362 best_val = cur_val; 363 } 364 365 rate_val |= best; 366 367 /* 368 * We may not get quite the right frequency if using 369 * approximate clocks so look for the closest match that is 370 * higher than the target (we need to ensure that there enough 371 * BCLKs to clock out the samples). 372 */ 373 best = 0; 374 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 375 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 376 if (cur_val < 0) /* BCLK table is sorted */ 377 break; 378 best = i; 379 } 380 381 if (i == ARRAY_SIZE(bclk_divs)) { 382 debug("%s: Could not get the best matching bclk division\n", 383 __func__); 384 return -1; 385 } 386 387 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 388 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 389 390 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) { 391 debug("%s: AIF1 register read Failed\n", __func__); 392 return -1; 393 } 394 395 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) 396 aif2 |= WM8994_AIF1_MONO; 397 398 if (wm8994->aifclk[id] == 0) { 399 debug("%s:Audio interface clock not set\n", __func__); 400 return -1; 401 } 402 403 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1); 404 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2); 405 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 406 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK | 407 WM8994_AIF1CLK_RATE_MASK, rate_val); 408 409 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk); 410 411 if (ret < 0) { 412 debug("%s: codec register access error\n", __func__); 413 return -1; 414 } 415 416 return 0; 417 } 418 419 /* 420 * Configures Audio interface Clock 421 * 422 * @param wm8994 wm8994 information pointer 423 * @param aif Audio Interface ID 424 * 425 * @return -1 for error and 0 Success. 426 */ 427 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) 428 { 429 int rate; 430 int reg1 = 0; 431 int offset; 432 int ret; 433 434 /* AIF(1/0) register adress offset calculated */ 435 if (aif-1) 436 offset = 4; 437 else 438 offset = 0; 439 440 switch (wm8994->sysclk[aif-1]) { 441 case WM8994_SYSCLK_MCLK1: 442 reg1 |= SEL_MCLK1; 443 rate = wm8994->mclk[0]; 444 break; 445 446 case WM8994_SYSCLK_MCLK2: 447 reg1 |= SEL_MCLK2; 448 rate = wm8994->mclk[1]; 449 break; 450 451 case WM8994_SYSCLK_FLL1: 452 reg1 |= SEL_FLL1; 453 rate = wm8994->fll[0].out; 454 break; 455 456 case WM8994_SYSCLK_FLL2: 457 reg1 |= SEL_FLL2; 458 rate = wm8994->fll[1].out; 459 break; 460 461 default: 462 debug("%s: Invalid input clock selection [%d]\n", 463 __func__, wm8994->sysclk[aif-1]); 464 return -1; 465 } 466 467 /* if input clock frequenct is more than 135Mhz then divide */ 468 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) { 469 rate /= 2; 470 reg1 |= WM8994_AIF1CLK_DIV; 471 } 472 473 wm8994->aifclk[aif-1] = rate; 474 475 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, 476 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 477 reg1); 478 479 if (aif == WM8994_AIF1) 480 ret |= wm8994_update_bits(WM8994_CLOCKING_1, 481 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK, 482 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); 483 else if (aif == WM8994_AIF2) 484 ret |= wm8994_update_bits(WM8994_CLOCKING_1, 485 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | 486 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | 487 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); 488 489 if (ret < 0) { 490 debug("%s: codec register access error\n", __func__); 491 return -1; 492 } 493 494 return 0; 495 } 496 497 /* 498 * Configures Audio interface for the given frequency 499 * 500 * @param wm8994 wm8994 information 501 * @param aif_id Audio Interface 502 * @param clk_id Input Clock ID 503 * @param freq Sampling frequency in Hz 504 * 505 * @return -1 for error and 0 success. 506 */ 507 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, 508 int clk_id, unsigned int freq) 509 { 510 int i; 511 int ret = 0; 512 513 wm8994->sysclk[aif_id - 1] = clk_id; 514 515 switch (clk_id) { 516 case WM8994_SYSCLK_MCLK1: 517 wm8994->mclk[0] = freq; 518 if (aif_id == 2) { 519 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 , 520 WM8994_AIF2DAC_DIV_MASK , 0); 521 } 522 break; 523 524 case WM8994_SYSCLK_MCLK2: 525 /* TODO: Set GPIO AF */ 526 wm8994->mclk[1] = freq; 527 break; 528 529 case WM8994_SYSCLK_FLL1: 530 case WM8994_SYSCLK_FLL2: 531 break; 532 533 case WM8994_SYSCLK_OPCLK: 534 /* 535 * Special case - a division (times 10) is given and 536 * no effect on main clocking. 537 */ 538 if (freq) { 539 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 540 if (opclk_divs[i] == freq) 541 break; 542 if (i == ARRAY_SIZE(opclk_divs)) { 543 debug("%s frequency divisor not found\n", 544 __func__); 545 return -1; 546 } 547 ret = wm8994_update_bits(WM8994_CLOCKING_2, 548 WM8994_OPCLK_DIV_MASK, i); 549 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 550 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 551 } else { 552 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 553 WM8994_OPCLK_ENA, 0); 554 } 555 556 default: 557 debug("%s Invalid input clock selection [%d]\n", 558 __func__, clk_id); 559 return -1; 560 } 561 562 ret |= configure_aif_clock(wm8994, aif_id); 563 564 if (ret < 0) { 565 debug("%s: codec register access error\n", __func__); 566 return -1; 567 } 568 569 return 0; 570 } 571 572 /* 573 * Initializes Volume for AIF2 to HP path 574 * 575 * @returns -1 for error and 0 Success. 576 * 577 */ 578 static int wm8994_init_volume_aif2_dac1(void) 579 { 580 int ret; 581 582 /* Unmute AIF2DAC */ 583 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1, 584 WM8994_AIF2DAC_MUTE_MASK, 0); 585 586 587 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME, 588 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK, 589 WM8994_AIF2DAC_VU | 0xff); 590 591 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME, 592 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK, 593 WM8994_AIF2DAC_VU | 0xff); 594 595 596 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, 597 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | 598 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 599 600 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, 601 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | 602 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 603 /* Head Phone Volume */ 604 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); 605 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); 606 607 if (ret < 0) { 608 debug("%s: codec register access error\n", __func__); 609 return -1; 610 } 611 612 return 0; 613 } 614 615 /* 616 * Initializes Volume for AIF1 to HP path 617 * 618 * @returns -1 for error and 0 Success. 619 * 620 */ 621 static int wm8994_init_volume_aif1_dac1(void) 622 { 623 int ret = 0; 624 625 /* Unmute AIF1DAC */ 626 ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000); 627 628 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, 629 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | 630 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 631 632 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, 633 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | 634 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 635 /* Head Phone Volume */ 636 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); 637 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); 638 639 if (ret < 0) { 640 debug("%s: codec register access error\n", __func__); 641 return -1; 642 } 643 644 return 0; 645 } 646 647 /* 648 * Intialise wm8994 codec device 649 * 650 * @param wm8994 wm8994 information 651 * 652 * @returns -1 for error and 0 Success. 653 */ 654 static int wm8994_device_init(struct wm8994_priv *wm8994, 655 enum en_audio_interface aif_id) 656 { 657 const char *devname; 658 unsigned short reg_data; 659 int ret; 660 661 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */ 662 663 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data); 664 if (ret < 0) { 665 debug("Failed to read ID register\n"); 666 goto err; 667 } 668 669 if (reg_data == WM8994_ID) { 670 devname = "WM8994"; 671 debug("Device registered as type %d\n", wm8994->type); 672 wm8994->type = WM8994; 673 } else { 674 debug("Device is not a WM8994, ID is %x\n", ret); 675 ret = -1; 676 goto err; 677 } 678 679 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data); 680 if (ret < 0) { 681 debug("Failed to read revision register: %d\n", ret); 682 goto err; 683 } 684 wm8994->revision = reg_data; 685 debug("%s revision %c\n", devname, 'A' + wm8994->revision); 686 687 /* VMID Selection */ 688 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 689 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3); 690 691 /* Charge Pump Enable */ 692 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK, 693 WM8994_CP_ENA); 694 695 /* Head Phone Power Enable */ 696 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 697 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA); 698 699 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 700 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); 701 702 if (aif_id == WM8994_AIF1) { 703 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2, 704 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA | 705 WM8994_MIXINR_ENA | WM8994_IN2L_ENA | 706 WM8994_IN2R_ENA); 707 708 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4, 709 WM8994_ADCL_ENA | WM8994_ADCR_ENA | 710 WM8994_AIF1ADC1R_ENA | 711 WM8994_AIF1ADC1L_ENA); 712 713 /* Power enable for AIF1 and DAC1 */ 714 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5, 715 WM8994_AIF1DACL_ENA | 716 WM8994_AIF1DACR_ENA | 717 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); 718 } else if (aif_id == WM8994_AIF2) { 719 /* Power enable for AIF2 and DAC1 */ 720 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, 721 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | 722 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, 723 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | 724 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA); 725 } 726 /* Head Phone Initialisation */ 727 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 728 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, 729 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY); 730 731 ret |= wm8994_update_bits(WM8994_DC_SERVO_1, 732 WM8994_DCS_ENA_CHAN_0_MASK | 733 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 | 734 WM8994_DCS_ENA_CHAN_1); 735 736 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 737 WM8994_HPOUT1L_DLY_MASK | 738 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK | 739 WM8994_HPOUT1R_OUTP_MASK | 740 WM8994_HPOUT1L_RMV_SHORT_MASK | 741 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY | 742 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP | 743 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT | 744 WM8994_HPOUT1R_RMV_SHORT); 745 746 /* MIXER Config DAC1 to HP */ 747 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1, 748 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L); 749 750 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, 751 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); 752 753 if (aif_id == WM8994_AIF1) { 754 /* Routing AIF1 to DAC1 */ 755 ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING, 756 WM8994_AIF1DAC1L_TO_DAC1L); 757 758 ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING, 759 WM8994_AIF1DAC1R_TO_DAC1R); 760 761 /* GPIO Settings for AIF1 */ 762 ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT 763 | WM8994_GPIO_FUNCTION_I2S_CLK 764 | WM8994_GPIO_INPUT_DEBOUNCE); 765 766 ret |= wm8994_init_volume_aif1_dac1(); 767 } else if (aif_id == WM8994_AIF2) { 768 /* Routing AIF2 to DAC1 */ 769 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, 770 WM8994_AIF2DACL_TO_DAC1L_MASK, 771 WM8994_AIF2DACL_TO_DAC1L); 772 773 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, 774 WM8994_AIF2DACR_TO_DAC1R_MASK, 775 WM8994_AIF2DACR_TO_DAC1R); 776 777 /* GPIO Settings for AIF2 */ 778 /* B CLK */ 779 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | 780 WM8994_GPIO_FUNCTION_MASK , 781 WM8994_GPIO_DIR_OUTPUT); 782 783 /* LR CLK */ 784 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | 785 WM8994_GPIO_FUNCTION_MASK, 786 WM8994_GPIO_DIR_OUTPUT); 787 788 /* DATA */ 789 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | 790 WM8994_GPIO_FUNCTION_MASK, 791 WM8994_GPIO_DIR_OUTPUT); 792 793 ret |= wm8994_init_volume_aif2_dac1(); 794 } 795 796 if (ret < 0) 797 goto err; 798 799 debug("%s: Codec chip init ok\n", __func__); 800 return 0; 801 err: 802 debug("%s: Codec chip init error\n", __func__); 803 return -1; 804 } 805 806 /* 807 * Gets fdt values for wm8994 config parameters 808 * 809 * @param pcodec_info codec information structure 810 * @param blob FDT blob 811 * @return int value, 0 for success 812 */ 813 static int get_codec_values(struct sound_codec_info *pcodec_info, 814 const void *blob) 815 { 816 int error = 0; 817 #if CONFIG_IS_ENABLED(OF_CONTROL) 818 enum fdt_compat_id compat; 819 int node; 820 int parent; 821 822 /* Get the node from FDT for codec */ 823 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC); 824 if (node <= 0) { 825 debug("EXYNOS_SOUND: No node for codec in device tree\n"); 826 debug("node = %d\n", node); 827 return -1; 828 } 829 830 parent = fdt_parent_offset(blob, node); 831 if (parent < 0) { 832 debug("%s: Cannot find node parent\n", __func__); 833 return -1; 834 } 835 836 compat = fdtdec_lookup(blob, parent); 837 switch (compat) { 838 case COMPAT_SAMSUNG_S3C2440_I2C: 839 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); 840 error |= pcodec_info->i2c_bus; 841 debug("i2c bus = %d\n", pcodec_info->i2c_bus); 842 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, 843 "reg", 0); 844 error |= pcodec_info->i2c_dev_addr; 845 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 846 break; 847 default: 848 debug("%s: Unknown compat id %d\n", __func__, compat); 849 return -1; 850 } 851 #else 852 pcodec_info->i2c_bus = AUDIO_I2C_BUS; 853 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; 854 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 855 #endif 856 857 pcodec_info->codec_type = CODEC_WM_8994; 858 859 if (error == -1) { 860 debug("fail to get wm8994 codec node properties\n"); 861 return -1; 862 } 863 864 return 0; 865 } 866 867 /* WM8994 Device Initialisation */ 868 int wm8994_init(const void *blob, enum en_audio_interface aif_id, 869 int sampling_rate, int mclk_freq, 870 int bits_per_sample, unsigned int channels) 871 { 872 int ret = 0; 873 struct sound_codec_info *pcodec_info = &g_codec_info; 874 875 /* Get the codec Values */ 876 if (get_codec_values(pcodec_info, blob) < 0) { 877 debug("FDT Codec values failed\n"); 878 return -1; 879 } 880 881 /* shift the device address by 1 for 7 bit addressing */ 882 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; 883 wm8994_i2c_init(pcodec_info->i2c_bus); 884 885 if (pcodec_info->codec_type == CODEC_WM_8994) { 886 g_wm8994_info.type = WM8994; 887 } else { 888 debug("%s: Codec id [%d] not defined\n", __func__, 889 pcodec_info->codec_type); 890 return -1; 891 } 892 893 ret = wm8994_device_init(&g_wm8994_info, aif_id); 894 if (ret < 0) { 895 debug("%s: wm8994 codec chip init failed\n", __func__); 896 return ret; 897 } 898 899 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1, 900 mclk_freq); 901 if (ret < 0) { 902 debug("%s: wm8994 codec set sys clock failed\n", __func__); 903 return ret; 904 } 905 906 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate, 907 bits_per_sample, channels); 908 909 if (ret == 0) { 910 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S | 911 SND_SOC_DAIFMT_NB_NF | 912 SND_SOC_DAIFMT_CBS_CFS); 913 } 914 return ret; 915 } 916