1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * R. Chandrasekar <rcsekar@samsung.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <asm/arch/clk.h> 24 #include <asm/arch/cpu.h> 25 #include <asm/gpio.h> 26 #include <asm/io.h> 27 #include <common.h> 28 #include <div64.h> 29 #include <i2c.h> 30 #include <i2s.h> 31 #include <sound.h> 32 #include "wm8994.h" 33 #include "wm8994_registers.h" 34 35 /* defines for wm8994 system clock selection */ 36 #define SEL_MCLK1 0x00 37 #define SEL_MCLK2 0x08 38 #define SEL_FLL1 0x10 39 #define SEL_FLL2 0x18 40 41 /* fll config to configure fll */ 42 struct wm8994_fll_config { 43 int src; /* Source */ 44 int in; /* Input frequency in Hz */ 45 int out; /* output frequency in Hz */ 46 }; 47 48 /* codec private data */ 49 struct wm8994_priv { 50 enum wm8994_type type; /* codec type of wolfson */ 51 int revision; /* Revision */ 52 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */ 53 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */ 54 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */ 55 struct wm8994_fll_config fll[2]; /* fll config to configure fll */ 56 }; 57 58 /* wm 8994 supported sampling rate values */ 59 static unsigned int src_rate[] = { 60 8000, 11025, 12000, 16000, 22050, 24000, 61 32000, 44100, 48000, 88200, 96000 62 }; 63 64 /* op clock divisions */ 65 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 66 67 /* lr clock frame size ratio */ 68 static int fs_ratios[] = { 69 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 70 }; 71 72 /* bit clock divisors */ 73 static int bclk_divs[] = { 74 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 75 640, 880, 960, 1280, 1760, 1920 76 }; 77 78 static struct wm8994_priv g_wm8994_info; 79 static unsigned char g_wm8994_i2c_dev_addr; 80 81 /* 82 * Initialise I2C for wm 8994 83 * 84 * @param bus no i2c bus number in which wm8994 is connected 85 */ 86 static void wm8994_i2c_init(int bus_no) 87 { 88 i2c_set_bus_num(bus_no); 89 } 90 91 /* 92 * Writes value to a device register through i2c 93 * 94 * @param reg reg number to be write 95 * @param data data to be writen to the above registor 96 * 97 * @return int value 1 for change, 0 for no change or negative error code. 98 */ 99 static int wm8994_i2c_write(unsigned int reg, unsigned short data) 100 { 101 unsigned char val[2]; 102 103 val[0] = (unsigned char)((data >> 8) & 0xff); 104 val[1] = (unsigned char)(data & 0xff); 105 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data); 106 107 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 108 } 109 110 /* 111 * Read a value from a device register through i2c 112 * 113 * @param reg reg number to be read 114 * @param data address of read data to be stored 115 * 116 * @return int value 0 for success, -1 in case of error. 117 */ 118 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) 119 { 120 unsigned char val[2]; 121 int ret; 122 123 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 124 if (ret != 0) { 125 debug("%s: Error while reading register %#04x\n", 126 __func__, reg); 127 return -1; 128 } 129 130 *data = val[0]; 131 *data <<= 8; 132 *data |= val[1]; 133 134 return 0; 135 } 136 137 /* 138 * update device register bits through i2c 139 * 140 * @param reg codec register 141 * @param mask register mask 142 * @param value new value 143 * 144 * @return int value 1 if change in the register value, 145 * 0 for no change or negative error code. 146 */ 147 static int wm8994_update_bits(unsigned int reg, unsigned short mask, 148 unsigned short value) 149 { 150 int change , ret = 0; 151 unsigned short old, new; 152 153 if (wm8994_i2c_read(reg, &old) != 0) 154 return -1; 155 new = (old & ~mask) | (value & mask); 156 change = (old != new) ? 1 : 0; 157 if (change) 158 ret = wm8994_i2c_write(reg, new); 159 if (ret < 0) 160 return ret; 161 162 return change; 163 } 164 165 /* 166 * Sets i2s set format 167 * 168 * @param aif_id Interface ID 169 * @param fmt i2S format 170 * 171 * @return -1 for error and 0 Success. 172 */ 173 int wm8994_set_fmt(int aif_id, unsigned int fmt) 174 { 175 int ms_reg; 176 int aif_reg; 177 int ms = 0; 178 int aif = 0; 179 int aif_clk = 0; 180 int error = 0; 181 182 switch (aif_id) { 183 case 1: 184 ms_reg = WM8994_AIF1_MASTER_SLAVE; 185 aif_reg = WM8994_AIF1_CONTROL_1; 186 aif_clk = WM8994_AIF1_CLOCKING_1; 187 break; 188 case 2: 189 ms_reg = WM8994_AIF2_MASTER_SLAVE; 190 aif_reg = WM8994_AIF2_CONTROL_1; 191 aif_clk = WM8994_AIF2_CLOCKING_1; 192 break; 193 default: 194 debug("%s: Invalid audio interface selection\n", __func__); 195 return -1; 196 } 197 198 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 199 case SND_SOC_DAIFMT_CBS_CFS: 200 break; 201 case SND_SOC_DAIFMT_CBM_CFM: 202 ms = WM8994_AIF1_MSTR; 203 break; 204 default: 205 debug("%s: Invalid i2s master selection\n", __func__); 206 return -1; 207 } 208 209 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 210 case SND_SOC_DAIFMT_DSP_B: 211 aif |= WM8994_AIF1_LRCLK_INV; 212 case SND_SOC_DAIFMT_DSP_A: 213 aif |= 0x18; 214 break; 215 case SND_SOC_DAIFMT_I2S: 216 aif |= 0x10; 217 break; 218 case SND_SOC_DAIFMT_RIGHT_J: 219 break; 220 case SND_SOC_DAIFMT_LEFT_J: 221 aif |= 0x8; 222 break; 223 default: 224 debug("%s: Invalid i2s format selection\n", __func__); 225 return -1; 226 } 227 228 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 229 case SND_SOC_DAIFMT_DSP_A: 230 case SND_SOC_DAIFMT_DSP_B: 231 /* frame inversion not valid for DSP modes */ 232 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 233 case SND_SOC_DAIFMT_NB_NF: 234 break; 235 case SND_SOC_DAIFMT_IB_NF: 236 aif |= WM8994_AIF1_BCLK_INV; 237 break; 238 default: 239 debug("%s: Invalid i2s frame inverse selection\n", 240 __func__); 241 return -1; 242 } 243 break; 244 245 case SND_SOC_DAIFMT_I2S: 246 case SND_SOC_DAIFMT_RIGHT_J: 247 case SND_SOC_DAIFMT_LEFT_J: 248 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 249 case SND_SOC_DAIFMT_NB_NF: 250 break; 251 case SND_SOC_DAIFMT_IB_IF: 252 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 253 break; 254 case SND_SOC_DAIFMT_IB_NF: 255 aif |= WM8994_AIF1_BCLK_INV; 256 break; 257 case SND_SOC_DAIFMT_NB_IF: 258 aif |= WM8994_AIF1_LRCLK_INV; 259 break; 260 default: 261 debug("%s: Invalid i2s clock polarity selection\n", 262 __func__); 263 return -1; 264 } 265 break; 266 default: 267 debug("%s: Invalid i2s format selection\n", __func__); 268 return -1; 269 } 270 271 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV | 272 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif); 273 274 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms); 275 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK, 276 WM8994_AIF1CLK_ENA); 277 if (error < 0) { 278 debug("%s: codec register access error\n", __func__); 279 return -1; 280 } 281 282 return 0; 283 } 284 285 /* 286 * Sets hw params FOR WM8994 287 * 288 * @param wm8994 wm8994 information pointer 289 * @param aif_id Audio interface ID 290 * @param sampling_rate Sampling rate 291 * @param bits_per_sample Bits per sample 292 * @param Channels Channels in the given audio input 293 * 294 * @return -1 for error and 0 Success. 295 */ 296 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, 297 unsigned int sampling_rate, unsigned int bits_per_sample, 298 unsigned int channels) 299 { 300 int aif1_reg; 301 int aif2_reg; 302 int bclk_reg; 303 int bclk = 0; 304 int rate_reg; 305 int aif1 = 0; 306 int aif2 = 0; 307 int rate_val = 0; 308 int id = aif_id - 1; 309 int i, cur_val, best_val, bclk_rate, best; 310 unsigned short reg_data; 311 int ret = 0; 312 313 switch (aif_id) { 314 case 1: 315 aif1_reg = WM8994_AIF1_CONTROL_1; 316 aif2_reg = WM8994_AIF1_CONTROL_2; 317 bclk_reg = WM8994_AIF1_BCLK; 318 rate_reg = WM8994_AIF1_RATE; 319 break; 320 case 2: 321 aif1_reg = WM8994_AIF2_CONTROL_1; 322 aif2_reg = WM8994_AIF2_CONTROL_2; 323 bclk_reg = WM8994_AIF2_BCLK; 324 rate_reg = WM8994_AIF2_RATE; 325 break; 326 default: 327 return -1; 328 } 329 330 bclk_rate = sampling_rate * 32; 331 switch (bits_per_sample) { 332 case 16: 333 bclk_rate *= 16; 334 break; 335 case 20: 336 bclk_rate *= 20; 337 aif1 |= 0x20; 338 break; 339 case 24: 340 bclk_rate *= 24; 341 aif1 |= 0x40; 342 break; 343 case 32: 344 bclk_rate *= 32; 345 aif1 |= 0x60; 346 break; 347 default: 348 return -1; 349 } 350 351 /* Try to find an appropriate sample rate; look for an exact match. */ 352 for (i = 0; i < ARRAY_SIZE(src_rate); i++) 353 if (src_rate[i] == sampling_rate) 354 break; 355 356 if (i == ARRAY_SIZE(src_rate)) { 357 debug("%s: Could not get the best matching samplingrate\n", 358 __func__); 359 return -1; 360 } 361 362 rate_val |= i << WM8994_AIF1_SR_SHIFT; 363 364 /* AIFCLK/fs ratio; look for a close match in either direction */ 365 best = 0; 366 best_val = abs((fs_ratios[0] * sampling_rate) 367 - wm8994->aifclk[id]); 368 369 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 370 cur_val = abs((fs_ratios[i] * sampling_rate) 371 - wm8994->aifclk[id]); 372 if (cur_val >= best_val) 373 continue; 374 best = i; 375 best_val = cur_val; 376 } 377 378 rate_val |= best; 379 380 /* 381 * We may not get quite the right frequency if using 382 * approximate clocks so look for the closest match that is 383 * higher than the target (we need to ensure that there enough 384 * BCLKs to clock out the samples). 385 */ 386 best = 0; 387 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 388 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 389 if (cur_val < 0) /* BCLK table is sorted */ 390 break; 391 best = i; 392 } 393 394 if (i == ARRAY_SIZE(bclk_divs)) { 395 debug("%s: Could not get the best matching bclk division\n", 396 __func__); 397 return -1; 398 } 399 400 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 401 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 402 403 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) { 404 debug("%s: AIF1 register read Failed\n", __func__); 405 return -1; 406 } 407 408 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) 409 aif2 |= WM8994_AIF1_MONO; 410 411 if (wm8994->aifclk[id] == 0) { 412 debug("%s:Audio interface clock not set\n", __func__); 413 return -1; 414 } 415 416 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1); 417 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2); 418 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 419 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK | 420 WM8994_AIF1CLK_RATE_MASK, rate_val); 421 422 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk); 423 424 if (ret < 0) { 425 debug("%s: codec register access error\n", __func__); 426 return -1; 427 } 428 429 return 0; 430 } 431 432 /* 433 * Configures Audio interface Clock 434 * 435 * @param wm8994 wm8994 information pointer 436 * @param aif Audio Interface ID 437 * 438 * @return -1 for error and 0 Success. 439 */ 440 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) 441 { 442 int rate; 443 int reg1 = 0; 444 int offset; 445 int ret; 446 447 /* AIF(1/0) register adress offset calculated */ 448 if (aif) 449 offset = 4; 450 else 451 offset = 0; 452 453 switch (wm8994->sysclk[aif]) { 454 case WM8994_SYSCLK_MCLK1: 455 reg1 |= SEL_MCLK1; 456 rate = wm8994->mclk[0]; 457 break; 458 459 case WM8994_SYSCLK_MCLK2: 460 reg1 |= SEL_MCLK2; 461 rate = wm8994->mclk[1]; 462 break; 463 464 case WM8994_SYSCLK_FLL1: 465 reg1 |= SEL_FLL1; 466 rate = wm8994->fll[0].out; 467 break; 468 469 case WM8994_SYSCLK_FLL2: 470 reg1 |= SEL_FLL2; 471 rate = wm8994->fll[1].out; 472 break; 473 474 default: 475 debug("%s: Invalid input clock selection [%d]\n", 476 __func__, wm8994->sysclk[aif]); 477 return -1; 478 } 479 480 /* if input clock frequenct is more than 135Mhz then divide */ 481 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) { 482 rate /= 2; 483 reg1 |= WM8994_AIF1CLK_DIV; 484 } 485 486 wm8994->aifclk[aif] = rate; 487 488 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, 489 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 490 reg1); 491 492 ret |= wm8994_update_bits(WM8994_CLOCKING_1, 493 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | 494 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | 495 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); 496 497 if (ret < 0) { 498 debug("%s: codec register access error\n", __func__); 499 return -1; 500 } 501 502 return 0; 503 } 504 505 /* 506 * Configures Audio interface for the given frequency 507 * 508 * @param wm8994 wm8994 information 509 * @param aif_id Audio Interface 510 * @param clk_id Input Clock ID 511 * @param freq Sampling frequency in Hz 512 * 513 * @return -1 for error and 0 success. 514 */ 515 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, 516 int clk_id, unsigned int freq) 517 { 518 int i; 519 int ret = 0; 520 521 wm8994->sysclk[aif_id - 1] = clk_id; 522 523 switch (clk_id) { 524 case WM8994_SYSCLK_MCLK1: 525 wm8994->mclk[0] = freq; 526 if (aif_id == 2) { 527 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 , 528 WM8994_AIF2DAC_DIV_MASK , 0); 529 } 530 break; 531 532 case WM8994_SYSCLK_MCLK2: 533 /* TODO: Set GPIO AF */ 534 wm8994->mclk[1] = freq; 535 break; 536 537 case WM8994_SYSCLK_FLL1: 538 case WM8994_SYSCLK_FLL2: 539 break; 540 541 case WM8994_SYSCLK_OPCLK: 542 /* 543 * Special case - a division (times 10) is given and 544 * no effect on main clocking. 545 */ 546 if (freq) { 547 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 548 if (opclk_divs[i] == freq) 549 break; 550 if (i == ARRAY_SIZE(opclk_divs)) { 551 debug("%s frequency divisor not found\n", 552 __func__); 553 return -1; 554 } 555 ret = wm8994_update_bits(WM8994_CLOCKING_2, 556 WM8994_OPCLK_DIV_MASK, i); 557 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 558 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 559 } else { 560 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 561 WM8994_OPCLK_ENA, 0); 562 } 563 564 default: 565 debug("%s Invalid input clock selection [%d]\n", 566 __func__, clk_id); 567 return -1; 568 } 569 570 ret |= configure_aif_clock(wm8994, aif_id - 1); 571 572 if (ret < 0) { 573 debug("%s: codec register access error\n", __func__); 574 return -1; 575 } 576 577 return 0; 578 } 579 580 /* 581 * Initializes Volume for AIF2 to HP path 582 * 583 * @returns -1 for error and 0 Success. 584 * 585 */ 586 static int wm8994_init_volume_aif2_dac1(void) 587 { 588 int ret; 589 590 /* Unmute AIF2DAC */ 591 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1, 592 WM8994_AIF2DAC_MUTE_MASK, 0); 593 594 595 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME, 596 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK, 597 WM8994_AIF2DAC_VU | 0xff); 598 599 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME, 600 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK, 601 WM8994_AIF2DAC_VU | 0xff); 602 603 604 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, 605 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | 606 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 607 608 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, 609 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | 610 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 611 /* Head Phone Volume */ 612 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); 613 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); 614 615 if (ret < 0) { 616 debug("%s: codec register access error\n", __func__); 617 return -1; 618 } 619 620 return 0; 621 } 622 623 /* 624 * Intialise wm8994 codec device 625 * 626 * @param wm8994 wm8994 information 627 * 628 * @returns -1 for error and 0 Success. 629 */ 630 static int wm8994_device_init(struct wm8994_priv *wm8994) 631 { 632 const char *devname; 633 unsigned short reg_data; 634 int ret; 635 636 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */ 637 638 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data); 639 if (ret < 0) { 640 debug("Failed to read ID register\n"); 641 goto err; 642 } 643 644 if (reg_data == WM8994_ID) { 645 devname = "WM8994"; 646 debug("Device registered as type %d\n", wm8994->type); 647 wm8994->type = WM8994; 648 } else { 649 debug("Device is not a WM8994, ID is %x\n", ret); 650 ret = -1; 651 goto err; 652 } 653 654 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data); 655 if (ret < 0) { 656 debug("Failed to read revision register: %d\n", ret); 657 goto err; 658 } 659 wm8994->revision = reg_data; 660 debug("%s revision %c\n", devname, 'A' + wm8994->revision); 661 662 /* VMID Selection */ 663 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 664 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3); 665 666 /* Charge Pump Enable */ 667 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK, 668 WM8994_CP_ENA); 669 670 /* Head Phone Power Enable */ 671 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 672 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA); 673 674 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 675 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); 676 677 /* Power enable for AIF2 and DAC1 */ 678 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, 679 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | 680 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, 681 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA | 682 WM8994_DAC1R_ENA); 683 684 /* Head Phone Initialisation */ 685 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 686 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, 687 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY); 688 689 ret |= wm8994_update_bits(WM8994_DC_SERVO_1, 690 WM8994_DCS_ENA_CHAN_0_MASK | 691 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 | 692 WM8994_DCS_ENA_CHAN_1); 693 694 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 695 WM8994_HPOUT1L_DLY_MASK | 696 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK | 697 WM8994_HPOUT1R_OUTP_MASK | 698 WM8994_HPOUT1L_RMV_SHORT_MASK | 699 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY | 700 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP | 701 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT | 702 WM8994_HPOUT1R_RMV_SHORT); 703 704 /* MIXER Config DAC1 to HP */ 705 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1, 706 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L); 707 708 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, 709 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); 710 711 /* Routing AIF2 to DAC1 */ 712 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, 713 WM8994_AIF2DACL_TO_DAC1L_MASK, 714 WM8994_AIF2DACL_TO_DAC1L); 715 716 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, 717 WM8994_AIF2DACR_TO_DAC1R_MASK, 718 WM8994_AIF2DACR_TO_DAC1R); 719 720 /* GPIO Settings for AIF2 */ 721 /* B CLK */ 722 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | 723 WM8994_GPIO_FUNCTION_MASK , 724 WM8994_GPIO_DIR_OUTPUT | 725 WM8994_GPIO_FUNCTION_I2S_CLK); 726 727 /* LR CLK */ 728 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | 729 WM8994_GPIO_FUNCTION_MASK, 730 WM8994_GPIO_DIR_OUTPUT | 731 WM8994_GPIO_FUNCTION_I2S_CLK); 732 733 /* DATA */ 734 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | 735 WM8994_GPIO_FUNCTION_MASK, 736 WM8994_GPIO_DIR_OUTPUT | 737 WM8994_GPIO_FUNCTION_I2S_CLK); 738 739 ret |= wm8994_init_volume_aif2_dac1(); 740 if (ret < 0) 741 goto err; 742 743 debug("%s: Codec chip init ok\n", __func__); 744 return 0; 745 err: 746 debug("%s: Codec chip init error\n", __func__); 747 return -1; 748 } 749 750 /*wm8994 Device Initialisation */ 751 int wm8994_init(struct sound_codec_info *pcodec_info, 752 enum en_audio_interface aif_id, 753 int sampling_rate, int mclk_freq, 754 int bits_per_sample, unsigned int channels) 755 { 756 int ret = 0; 757 758 /* shift the device address by 1 for 7 bit addressing */ 759 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; 760 wm8994_i2c_init(pcodec_info->i2c_bus); 761 762 if (pcodec_info->codec_type == CODEC_WM_8994) 763 g_wm8994_info.type = WM8994; 764 else { 765 debug("%s: Codec id [%d] not defined\n", __func__, 766 pcodec_info->codec_type); 767 return -1; 768 } 769 770 ret = wm8994_device_init(&g_wm8994_info); 771 if (ret < 0) { 772 debug("%s: wm8994 codec chip init failed\n", __func__); 773 return ret; 774 } 775 776 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1, 777 mclk_freq); 778 if (ret < 0) { 779 debug("%s: wm8994 codec set sys clock failed\n", __func__); 780 return ret; 781 } 782 783 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate, 784 bits_per_sample, channels); 785 786 if (ret == 0) { 787 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S | 788 SND_SOC_DAIFMT_NB_NF | 789 SND_SOC_DAIFMT_CBS_CFS); 790 } 791 return ret; 792 } 793