1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * R. Chandrasekar <rcsekar@samsung.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <asm/arch/clk.h> 24 #include <asm/arch/cpu.h> 25 #include <asm/gpio.h> 26 #include <asm/io.h> 27 #include <common.h> 28 #include <div64.h> 29 #include <fdtdec.h> 30 #include <i2c.h> 31 #include <i2s.h> 32 #include <sound.h> 33 #include <asm/arch/sound.h> 34 #include "wm8994.h" 35 #include "wm8994_registers.h" 36 37 /* defines for wm8994 system clock selection */ 38 #define SEL_MCLK1 0x00 39 #define SEL_MCLK2 0x08 40 #define SEL_FLL1 0x10 41 #define SEL_FLL2 0x18 42 43 /* fll config to configure fll */ 44 struct wm8994_fll_config { 45 int src; /* Source */ 46 int in; /* Input frequency in Hz */ 47 int out; /* output frequency in Hz */ 48 }; 49 50 /* codec private data */ 51 struct wm8994_priv { 52 enum wm8994_type type; /* codec type of wolfson */ 53 int revision; /* Revision */ 54 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */ 55 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */ 56 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */ 57 struct wm8994_fll_config fll[2]; /* fll config to configure fll */ 58 }; 59 60 /* wm 8994 supported sampling rate values */ 61 static unsigned int src_rate[] = { 62 8000, 11025, 12000, 16000, 22050, 24000, 63 32000, 44100, 48000, 88200, 96000 64 }; 65 66 /* op clock divisions */ 67 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 68 69 /* lr clock frame size ratio */ 70 static int fs_ratios[] = { 71 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 72 }; 73 74 /* bit clock divisors */ 75 static int bclk_divs[] = { 76 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 77 640, 880, 960, 1280, 1760, 1920 78 }; 79 80 static struct wm8994_priv g_wm8994_info; 81 static unsigned char g_wm8994_i2c_dev_addr; 82 static struct sound_codec_info g_codec_info; 83 84 /* 85 * Initialise I2C for wm 8994 86 * 87 * @param bus no i2c bus number in which wm8994 is connected 88 */ 89 static void wm8994_i2c_init(int bus_no) 90 { 91 i2c_set_bus_num(bus_no); 92 } 93 94 /* 95 * Writes value to a device register through i2c 96 * 97 * @param reg reg number to be write 98 * @param data data to be writen to the above registor 99 * 100 * @return int value 1 for change, 0 for no change or negative error code. 101 */ 102 static int wm8994_i2c_write(unsigned int reg, unsigned short data) 103 { 104 unsigned char val[2]; 105 106 val[0] = (unsigned char)((data >> 8) & 0xff); 107 val[1] = (unsigned char)(data & 0xff); 108 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data); 109 110 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 111 } 112 113 /* 114 * Read a value from a device register through i2c 115 * 116 * @param reg reg number to be read 117 * @param data address of read data to be stored 118 * 119 * @return int value 0 for success, -1 in case of error. 120 */ 121 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data) 122 { 123 unsigned char val[2]; 124 int ret; 125 126 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2); 127 if (ret != 0) { 128 debug("%s: Error while reading register %#04x\n", 129 __func__, reg); 130 return -1; 131 } 132 133 *data = val[0]; 134 *data <<= 8; 135 *data |= val[1]; 136 137 return 0; 138 } 139 140 /* 141 * update device register bits through i2c 142 * 143 * @param reg codec register 144 * @param mask register mask 145 * @param value new value 146 * 147 * @return int value 1 if change in the register value, 148 * 0 for no change or negative error code. 149 */ 150 static int wm8994_update_bits(unsigned int reg, unsigned short mask, 151 unsigned short value) 152 { 153 int change , ret = 0; 154 unsigned short old, new; 155 156 if (wm8994_i2c_read(reg, &old) != 0) 157 return -1; 158 new = (old & ~mask) | (value & mask); 159 change = (old != new) ? 1 : 0; 160 if (change) 161 ret = wm8994_i2c_write(reg, new); 162 if (ret < 0) 163 return ret; 164 165 return change; 166 } 167 168 /* 169 * Sets i2s set format 170 * 171 * @param aif_id Interface ID 172 * @param fmt i2S format 173 * 174 * @return -1 for error and 0 Success. 175 */ 176 int wm8994_set_fmt(int aif_id, unsigned int fmt) 177 { 178 int ms_reg; 179 int aif_reg; 180 int ms = 0; 181 int aif = 0; 182 int aif_clk = 0; 183 int error = 0; 184 185 switch (aif_id) { 186 case 1: 187 ms_reg = WM8994_AIF1_MASTER_SLAVE; 188 aif_reg = WM8994_AIF1_CONTROL_1; 189 aif_clk = WM8994_AIF1_CLOCKING_1; 190 break; 191 case 2: 192 ms_reg = WM8994_AIF2_MASTER_SLAVE; 193 aif_reg = WM8994_AIF2_CONTROL_1; 194 aif_clk = WM8994_AIF2_CLOCKING_1; 195 break; 196 default: 197 debug("%s: Invalid audio interface selection\n", __func__); 198 return -1; 199 } 200 201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 202 case SND_SOC_DAIFMT_CBS_CFS: 203 break; 204 case SND_SOC_DAIFMT_CBM_CFM: 205 ms = WM8994_AIF1_MSTR; 206 break; 207 default: 208 debug("%s: Invalid i2s master selection\n", __func__); 209 return -1; 210 } 211 212 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 213 case SND_SOC_DAIFMT_DSP_B: 214 aif |= WM8994_AIF1_LRCLK_INV; 215 case SND_SOC_DAIFMT_DSP_A: 216 aif |= 0x18; 217 break; 218 case SND_SOC_DAIFMT_I2S: 219 aif |= 0x10; 220 break; 221 case SND_SOC_DAIFMT_RIGHT_J: 222 break; 223 case SND_SOC_DAIFMT_LEFT_J: 224 aif |= 0x8; 225 break; 226 default: 227 debug("%s: Invalid i2s format selection\n", __func__); 228 return -1; 229 } 230 231 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 232 case SND_SOC_DAIFMT_DSP_A: 233 case SND_SOC_DAIFMT_DSP_B: 234 /* frame inversion not valid for DSP modes */ 235 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 236 case SND_SOC_DAIFMT_NB_NF: 237 break; 238 case SND_SOC_DAIFMT_IB_NF: 239 aif |= WM8994_AIF1_BCLK_INV; 240 break; 241 default: 242 debug("%s: Invalid i2s frame inverse selection\n", 243 __func__); 244 return -1; 245 } 246 break; 247 248 case SND_SOC_DAIFMT_I2S: 249 case SND_SOC_DAIFMT_RIGHT_J: 250 case SND_SOC_DAIFMT_LEFT_J: 251 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 252 case SND_SOC_DAIFMT_NB_NF: 253 break; 254 case SND_SOC_DAIFMT_IB_IF: 255 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 256 break; 257 case SND_SOC_DAIFMT_IB_NF: 258 aif |= WM8994_AIF1_BCLK_INV; 259 break; 260 case SND_SOC_DAIFMT_NB_IF: 261 aif |= WM8994_AIF1_LRCLK_INV; 262 break; 263 default: 264 debug("%s: Invalid i2s clock polarity selection\n", 265 __func__); 266 return -1; 267 } 268 break; 269 default: 270 debug("%s: Invalid i2s format selection\n", __func__); 271 return -1; 272 } 273 274 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV | 275 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif); 276 277 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms); 278 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK, 279 WM8994_AIF1CLK_ENA); 280 if (error < 0) { 281 debug("%s: codec register access error\n", __func__); 282 return -1; 283 } 284 285 return 0; 286 } 287 288 /* 289 * Sets hw params FOR WM8994 290 * 291 * @param wm8994 wm8994 information pointer 292 * @param aif_id Audio interface ID 293 * @param sampling_rate Sampling rate 294 * @param bits_per_sample Bits per sample 295 * @param Channels Channels in the given audio input 296 * 297 * @return -1 for error and 0 Success. 298 */ 299 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id, 300 unsigned int sampling_rate, unsigned int bits_per_sample, 301 unsigned int channels) 302 { 303 int aif1_reg; 304 int aif2_reg; 305 int bclk_reg; 306 int bclk = 0; 307 int rate_reg; 308 int aif1 = 0; 309 int aif2 = 0; 310 int rate_val = 0; 311 int id = aif_id - 1; 312 int i, cur_val, best_val, bclk_rate, best; 313 unsigned short reg_data; 314 int ret = 0; 315 316 switch (aif_id) { 317 case 1: 318 aif1_reg = WM8994_AIF1_CONTROL_1; 319 aif2_reg = WM8994_AIF1_CONTROL_2; 320 bclk_reg = WM8994_AIF1_BCLK; 321 rate_reg = WM8994_AIF1_RATE; 322 break; 323 case 2: 324 aif1_reg = WM8994_AIF2_CONTROL_1; 325 aif2_reg = WM8994_AIF2_CONTROL_2; 326 bclk_reg = WM8994_AIF2_BCLK; 327 rate_reg = WM8994_AIF2_RATE; 328 break; 329 default: 330 return -1; 331 } 332 333 bclk_rate = sampling_rate * 32; 334 switch (bits_per_sample) { 335 case 16: 336 bclk_rate *= 16; 337 break; 338 case 20: 339 bclk_rate *= 20; 340 aif1 |= 0x20; 341 break; 342 case 24: 343 bclk_rate *= 24; 344 aif1 |= 0x40; 345 break; 346 case 32: 347 bclk_rate *= 32; 348 aif1 |= 0x60; 349 break; 350 default: 351 return -1; 352 } 353 354 /* Try to find an appropriate sample rate; look for an exact match. */ 355 for (i = 0; i < ARRAY_SIZE(src_rate); i++) 356 if (src_rate[i] == sampling_rate) 357 break; 358 359 if (i == ARRAY_SIZE(src_rate)) { 360 debug("%s: Could not get the best matching samplingrate\n", 361 __func__); 362 return -1; 363 } 364 365 rate_val |= i << WM8994_AIF1_SR_SHIFT; 366 367 /* AIFCLK/fs ratio; look for a close match in either direction */ 368 best = 0; 369 best_val = abs((fs_ratios[0] * sampling_rate) 370 - wm8994->aifclk[id]); 371 372 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 373 cur_val = abs((fs_ratios[i] * sampling_rate) 374 - wm8994->aifclk[id]); 375 if (cur_val >= best_val) 376 continue; 377 best = i; 378 best_val = cur_val; 379 } 380 381 rate_val |= best; 382 383 /* 384 * We may not get quite the right frequency if using 385 * approximate clocks so look for the closest match that is 386 * higher than the target (we need to ensure that there enough 387 * BCLKs to clock out the samples). 388 */ 389 best = 0; 390 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 391 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 392 if (cur_val < 0) /* BCLK table is sorted */ 393 break; 394 best = i; 395 } 396 397 if (i == ARRAY_SIZE(bclk_divs)) { 398 debug("%s: Could not get the best matching bclk division\n", 399 __func__); 400 return -1; 401 } 402 403 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 404 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 405 406 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) { 407 debug("%s: AIF1 register read Failed\n", __func__); 408 return -1; 409 } 410 411 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) 412 aif2 |= WM8994_AIF1_MONO; 413 414 if (wm8994->aifclk[id] == 0) { 415 debug("%s:Audio interface clock not set\n", __func__); 416 return -1; 417 } 418 419 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1); 420 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2); 421 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 422 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK | 423 WM8994_AIF1CLK_RATE_MASK, rate_val); 424 425 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk); 426 427 if (ret < 0) { 428 debug("%s: codec register access error\n", __func__); 429 return -1; 430 } 431 432 return 0; 433 } 434 435 /* 436 * Configures Audio interface Clock 437 * 438 * @param wm8994 wm8994 information pointer 439 * @param aif Audio Interface ID 440 * 441 * @return -1 for error and 0 Success. 442 */ 443 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif) 444 { 445 int rate; 446 int reg1 = 0; 447 int offset; 448 int ret; 449 450 /* AIF(1/0) register adress offset calculated */ 451 if (aif) 452 offset = 4; 453 else 454 offset = 0; 455 456 switch (wm8994->sysclk[aif]) { 457 case WM8994_SYSCLK_MCLK1: 458 reg1 |= SEL_MCLK1; 459 rate = wm8994->mclk[0]; 460 break; 461 462 case WM8994_SYSCLK_MCLK2: 463 reg1 |= SEL_MCLK2; 464 rate = wm8994->mclk[1]; 465 break; 466 467 case WM8994_SYSCLK_FLL1: 468 reg1 |= SEL_FLL1; 469 rate = wm8994->fll[0].out; 470 break; 471 472 case WM8994_SYSCLK_FLL2: 473 reg1 |= SEL_FLL2; 474 rate = wm8994->fll[1].out; 475 break; 476 477 default: 478 debug("%s: Invalid input clock selection [%d]\n", 479 __func__, wm8994->sysclk[aif]); 480 return -1; 481 } 482 483 /* if input clock frequenct is more than 135Mhz then divide */ 484 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) { 485 rate /= 2; 486 reg1 |= WM8994_AIF1CLK_DIV; 487 } 488 489 wm8994->aifclk[aif] = rate; 490 491 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset, 492 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 493 reg1); 494 495 ret |= wm8994_update_bits(WM8994_CLOCKING_1, 496 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK | 497 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC | 498 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA); 499 500 if (ret < 0) { 501 debug("%s: codec register access error\n", __func__); 502 return -1; 503 } 504 505 return 0; 506 } 507 508 /* 509 * Configures Audio interface for the given frequency 510 * 511 * @param wm8994 wm8994 information 512 * @param aif_id Audio Interface 513 * @param clk_id Input Clock ID 514 * @param freq Sampling frequency in Hz 515 * 516 * @return -1 for error and 0 success. 517 */ 518 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id, 519 int clk_id, unsigned int freq) 520 { 521 int i; 522 int ret = 0; 523 524 wm8994->sysclk[aif_id - 1] = clk_id; 525 526 switch (clk_id) { 527 case WM8994_SYSCLK_MCLK1: 528 wm8994->mclk[0] = freq; 529 if (aif_id == 2) { 530 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 , 531 WM8994_AIF2DAC_DIV_MASK , 0); 532 } 533 break; 534 535 case WM8994_SYSCLK_MCLK2: 536 /* TODO: Set GPIO AF */ 537 wm8994->mclk[1] = freq; 538 break; 539 540 case WM8994_SYSCLK_FLL1: 541 case WM8994_SYSCLK_FLL2: 542 break; 543 544 case WM8994_SYSCLK_OPCLK: 545 /* 546 * Special case - a division (times 10) is given and 547 * no effect on main clocking. 548 */ 549 if (freq) { 550 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 551 if (opclk_divs[i] == freq) 552 break; 553 if (i == ARRAY_SIZE(opclk_divs)) { 554 debug("%s frequency divisor not found\n", 555 __func__); 556 return -1; 557 } 558 ret = wm8994_update_bits(WM8994_CLOCKING_2, 559 WM8994_OPCLK_DIV_MASK, i); 560 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 561 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 562 } else { 563 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2, 564 WM8994_OPCLK_ENA, 0); 565 } 566 567 default: 568 debug("%s Invalid input clock selection [%d]\n", 569 __func__, clk_id); 570 return -1; 571 } 572 573 ret |= configure_aif_clock(wm8994, aif_id - 1); 574 575 if (ret < 0) { 576 debug("%s: codec register access error\n", __func__); 577 return -1; 578 } 579 580 return 0; 581 } 582 583 /* 584 * Initializes Volume for AIF2 to HP path 585 * 586 * @returns -1 for error and 0 Success. 587 * 588 */ 589 static int wm8994_init_volume_aif2_dac1(void) 590 { 591 int ret; 592 593 /* Unmute AIF2DAC */ 594 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1, 595 WM8994_AIF2DAC_MUTE_MASK, 0); 596 597 598 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME, 599 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK, 600 WM8994_AIF2DAC_VU | 0xff); 601 602 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME, 603 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK, 604 WM8994_AIF2DAC_VU | 0xff); 605 606 607 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME, 608 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK | 609 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 610 611 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME, 612 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK | 613 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0); 614 /* Head Phone Volume */ 615 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D); 616 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D); 617 618 if (ret < 0) { 619 debug("%s: codec register access error\n", __func__); 620 return -1; 621 } 622 623 return 0; 624 } 625 626 /* 627 * Intialise wm8994 codec device 628 * 629 * @param wm8994 wm8994 information 630 * 631 * @returns -1 for error and 0 Success. 632 */ 633 static int wm8994_device_init(struct wm8994_priv *wm8994) 634 { 635 const char *devname; 636 unsigned short reg_data; 637 int ret; 638 639 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */ 640 641 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data); 642 if (ret < 0) { 643 debug("Failed to read ID register\n"); 644 goto err; 645 } 646 647 if (reg_data == WM8994_ID) { 648 devname = "WM8994"; 649 debug("Device registered as type %d\n", wm8994->type); 650 wm8994->type = WM8994; 651 } else { 652 debug("Device is not a WM8994, ID is %x\n", ret); 653 ret = -1; 654 goto err; 655 } 656 657 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data); 658 if (ret < 0) { 659 debug("Failed to read revision register: %d\n", ret); 660 goto err; 661 } 662 wm8994->revision = reg_data; 663 debug("%s revision %c\n", devname, 'A' + wm8994->revision); 664 665 /* VMID Selection */ 666 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 667 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3); 668 669 /* Charge Pump Enable */ 670 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK, 671 WM8994_CP_ENA); 672 673 /* Head Phone Power Enable */ 674 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 675 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA); 676 677 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1, 678 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA); 679 680 /* Power enable for AIF2 and DAC1 */ 681 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5, 682 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK | 683 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK, 684 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA | 685 WM8994_DAC1R_ENA); 686 687 /* Head Phone Initialisation */ 688 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 689 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK, 690 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY); 691 692 ret |= wm8994_update_bits(WM8994_DC_SERVO_1, 693 WM8994_DCS_ENA_CHAN_0_MASK | 694 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 | 695 WM8994_DCS_ENA_CHAN_1); 696 697 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1, 698 WM8994_HPOUT1L_DLY_MASK | 699 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK | 700 WM8994_HPOUT1R_OUTP_MASK | 701 WM8994_HPOUT1L_RMV_SHORT_MASK | 702 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY | 703 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP | 704 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT | 705 WM8994_HPOUT1R_RMV_SHORT); 706 707 /* MIXER Config DAC1 to HP */ 708 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1, 709 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L); 710 711 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2, 712 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R); 713 714 /* Routing AIF2 to DAC1 */ 715 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING, 716 WM8994_AIF2DACL_TO_DAC1L_MASK, 717 WM8994_AIF2DACL_TO_DAC1L); 718 719 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING, 720 WM8994_AIF2DACR_TO_DAC1R_MASK, 721 WM8994_AIF2DACR_TO_DAC1R); 722 723 /* GPIO Settings for AIF2 */ 724 /* B CLK */ 725 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK | 726 WM8994_GPIO_FUNCTION_MASK , 727 WM8994_GPIO_DIR_OUTPUT | 728 WM8994_GPIO_FUNCTION_I2S_CLK); 729 730 /* LR CLK */ 731 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK | 732 WM8994_GPIO_FUNCTION_MASK, 733 WM8994_GPIO_DIR_OUTPUT | 734 WM8994_GPIO_FUNCTION_I2S_CLK); 735 736 /* DATA */ 737 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK | 738 WM8994_GPIO_FUNCTION_MASK, 739 WM8994_GPIO_DIR_OUTPUT | 740 WM8994_GPIO_FUNCTION_I2S_CLK); 741 742 ret |= wm8994_init_volume_aif2_dac1(); 743 if (ret < 0) 744 goto err; 745 746 debug("%s: Codec chip init ok\n", __func__); 747 return 0; 748 err: 749 debug("%s: Codec chip init error\n", __func__); 750 return -1; 751 } 752 753 /* 754 * Gets fdt values for wm8994 config parameters 755 * 756 * @param pcodec_info codec information structure 757 * @param blob FDT blob 758 * @return int value, 0 for success 759 */ 760 static int get_codec_values(struct sound_codec_info *pcodec_info, 761 const void *blob) 762 { 763 int error = 0; 764 #ifdef CONFIG_OF_CONTROL 765 enum fdt_compat_id compat; 766 int node; 767 int parent; 768 769 /* Get the node from FDT for codec */ 770 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC); 771 if (node <= 0) { 772 debug("EXYNOS_SOUND: No node for codec in device tree\n"); 773 debug("node = %d\n", node); 774 return -1; 775 } 776 777 parent = fdt_parent_offset(blob, node); 778 if (parent < 0) { 779 debug("%s: Cannot find node parent\n", __func__); 780 return -1; 781 } 782 783 compat = fdtdec_lookup(blob, parent); 784 switch (compat) { 785 case COMPAT_SAMSUNG_S3C2440_I2C: 786 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); 787 error |= pcodec_info->i2c_bus; 788 debug("i2c bus = %d\n", pcodec_info->i2c_bus); 789 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, 790 "reg", 0); 791 error |= pcodec_info->i2c_dev_addr; 792 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 793 break; 794 default: 795 debug("%s: Unknown compat id %d\n", __func__, compat); 796 return -1; 797 } 798 #else 799 pcodec_info->i2c_bus = AUDIO_I2C_BUS; 800 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; 801 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 802 #endif 803 804 pcodec_info->codec_type = CODEC_WM_8994; 805 806 if (error == -1) { 807 debug("fail to get wm8994 codec node properties\n"); 808 return -1; 809 } 810 811 return 0; 812 } 813 814 /*wm8994 Device Initialisation */ 815 int wm8994_init(const void *blob, enum en_audio_interface aif_id, 816 int sampling_rate, int mclk_freq, 817 int bits_per_sample, unsigned int channels) 818 { 819 int ret = 0; 820 struct sound_codec_info *pcodec_info = &g_codec_info; 821 822 /* Get the codec Values */ 823 if (get_codec_values(pcodec_info, blob) < 0) { 824 debug("FDT Codec values failed\n"); 825 return -1; 826 } 827 828 /* shift the device address by 1 for 7 bit addressing */ 829 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr; 830 wm8994_i2c_init(pcodec_info->i2c_bus); 831 832 if (pcodec_info->codec_type == CODEC_WM_8994) 833 g_wm8994_info.type = WM8994; 834 else { 835 debug("%s: Codec id [%d] not defined\n", __func__, 836 pcodec_info->codec_type); 837 return -1; 838 } 839 840 ret = wm8994_device_init(&g_wm8994_info); 841 if (ret < 0) { 842 debug("%s: wm8994 codec chip init failed\n", __func__); 843 return ret; 844 } 845 846 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1, 847 mclk_freq); 848 if (ret < 0) { 849 debug("%s: wm8994 codec set sys clock failed\n", __func__); 850 return ret; 851 } 852 853 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate, 854 bits_per_sample, channels); 855 856 if (ret == 0) { 857 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S | 858 SND_SOC_DAIFMT_NB_NF | 859 SND_SOC_DAIFMT_CBS_CFS); 860 } 861 return ret; 862 } 863