1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * R. Chandrasekar <rcsekar@samsung.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <asm/arch/clk.h> 25 #include <asm/arch/pinmux.h> 26 #include <asm/arch/i2s-regs.h> 27 #include <asm/io.h> 28 #include <common.h> 29 #include <sound.h> 30 #include <i2s.h> 31 32 #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf) 33 #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf) 34 #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf) 35 #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf) 36 #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f) 37 38 #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */ 39 40 /* 41 * Sets the frame size for I2S LR clock 42 * 43 * @param i2s_reg i2s regiter address 44 * @param rfs Frame Size 45 */ 46 static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) 47 { 48 unsigned int mod = readl(&i2s_reg->mod); 49 50 mod &= ~MOD_RCLK_MASK; 51 52 switch (rfs) { 53 case 768: 54 mod |= MOD_RCLK_768FS; 55 break; 56 case 512: 57 mod |= MOD_RCLK_512FS; 58 break; 59 case 384: 60 mod |= MOD_RCLK_384FS; 61 break; 62 default: 63 mod |= MOD_RCLK_256FS; 64 break; 65 } 66 67 writel(mod, &i2s_reg->mod); 68 } 69 70 /* 71 * Sets the i2s transfer control 72 * 73 * @param i2s_reg i2s regiter address 74 * @param on 1 enable tx , 0 disable tx transfer 75 */ 76 static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) 77 { 78 unsigned int con = readl(&i2s_reg->con); 79 unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK; 80 81 if (on) { 82 con |= CON_ACTIVE; 83 con &= ~CON_TXCH_PAUSE; 84 85 } else { 86 87 con |= CON_TXCH_PAUSE; 88 con &= ~CON_ACTIVE; 89 } 90 91 writel(mod, &i2s_reg->mod); 92 writel(con, &i2s_reg->con); 93 } 94 95 /* 96 * set the bit clock frame size (in multiples of LRCLK) 97 * 98 * @param i2s_reg i2s regiter address 99 * @param bfs bit Frame Size 100 */ 101 static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) 102 { 103 unsigned int mod = readl(&i2s_reg->mod); 104 105 mod &= ~MOD_BCLK_MASK; 106 107 switch (bfs) { 108 case 48: 109 mod |= MOD_BCLK_48FS; 110 break; 111 case 32: 112 mod |= MOD_BCLK_32FS; 113 break; 114 case 24: 115 mod |= MOD_BCLK_24FS; 116 break; 117 case 16: 118 mod |= MOD_BCLK_16FS; 119 break; 120 default: 121 return; 122 } 123 writel(mod, &i2s_reg->mod); 124 } 125 126 /* 127 * flushes the i2stx fifo 128 * 129 * @param i2s_reg i2s regiter address 130 * @param flush Tx fifo flush command (0x00 - do not flush 131 * 0x80 - flush tx fifo) 132 */ 133 void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) 134 { 135 /* Flush the FIFO */ 136 setbits_le32(&i2s_reg->fic, flush); 137 clrbits_le32(&i2s_reg->fic, flush); 138 } 139 140 /* 141 * Set System Clock direction 142 * 143 * @param i2s_reg i2s regiter address 144 * @param dir Clock direction 145 * 146 * @return int value 0 for success, -1 in case of error 147 */ 148 int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) 149 { 150 unsigned int mod = readl(&i2s_reg->mod); 151 152 if (dir == SND_SOC_CLOCK_IN) 153 mod |= MOD_CDCLKCON; 154 else 155 mod &= ~MOD_CDCLKCON; 156 157 writel(mod, &i2s_reg->mod); 158 159 return 0; 160 } 161 162 /* 163 * Sets I2S Clcok format 164 * 165 * @param fmt i2s clock properties 166 * @param i2s_reg i2s regiter address 167 * 168 * @return int value 0 for success, -1 in case of error 169 */ 170 int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) 171 { 172 unsigned int mod = readl(&i2s_reg->mod); 173 unsigned int tmp = 0; 174 unsigned int ret = 0; 175 176 /* Format is priority */ 177 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 178 case SND_SOC_DAIFMT_RIGHT_J: 179 tmp |= MOD_LR_RLOW; 180 tmp |= MOD_SDF_MSB; 181 break; 182 case SND_SOC_DAIFMT_LEFT_J: 183 tmp |= MOD_LR_RLOW; 184 tmp |= MOD_SDF_LSB; 185 break; 186 case SND_SOC_DAIFMT_I2S: 187 tmp |= MOD_SDF_IIS; 188 break; 189 default: 190 debug("%s: Invalid format priority [0x%x]\n", __func__, 191 (fmt & SND_SOC_DAIFMT_FORMAT_MASK)); 192 return -1; 193 } 194 195 /* 196 * INV flag is relative to the FORMAT flag - if set it simply 197 * flips the polarity specified by the Standard 198 */ 199 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 200 case SND_SOC_DAIFMT_NB_NF: 201 break; 202 case SND_SOC_DAIFMT_NB_IF: 203 if (tmp & MOD_LR_RLOW) 204 tmp &= ~MOD_LR_RLOW; 205 else 206 tmp |= MOD_LR_RLOW; 207 break; 208 default: 209 debug("%s: Invalid clock ploarity input [0x%x]\n", __func__, 210 (fmt & SND_SOC_DAIFMT_INV_MASK)); 211 return -1; 212 } 213 214 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 215 case SND_SOC_DAIFMT_CBS_CFS: 216 tmp |= MOD_SLAVE; 217 break; 218 case SND_SOC_DAIFMT_CBM_CFM: 219 /* Set default source clock in Master mode */ 220 ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT); 221 if (ret != 0) { 222 debug("%s:set i2s clock direction failed\n", __func__); 223 return -1; 224 } 225 break; 226 default: 227 debug("%s: Invalid master selection [0x%x]\n", __func__, 228 (fmt & SND_SOC_DAIFMT_MASTER_MASK)); 229 return -1; 230 } 231 232 mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE); 233 mod |= tmp; 234 writel(mod, &i2s_reg->mod); 235 236 return 0; 237 } 238 239 /* 240 * Sets the sample width in bits 241 * 242 * @param blc samplewidth (size of sample in bits) 243 * @param i2s_reg i2s regiter address 244 * 245 * @return int value 0 for success, -1 in case of error 246 */ 247 int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc) 248 { 249 unsigned int mod = readl(&i2s_reg->mod); 250 251 mod &= ~MOD_BLCP_MASK; 252 mod &= ~MOD_BLC_MASK; 253 254 switch (blc) { 255 case 8: 256 mod |= MOD_BLCP_8BIT; 257 mod |= MOD_BLC_8BIT; 258 break; 259 case 16: 260 mod |= MOD_BLCP_16BIT; 261 mod |= MOD_BLC_16BIT; 262 break; 263 case 24: 264 mod |= MOD_BLCP_24BIT; 265 mod |= MOD_BLC_24BIT; 266 break; 267 default: 268 debug("%s: Invalid sample size input [0x%x]\n", 269 __func__, blc); 270 return -1; 271 } 272 writel(mod, &i2s_reg->mod); 273 274 return 0; 275 } 276 277 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data, 278 unsigned long data_size) 279 { 280 int i; 281 int start; 282 struct i2s_reg *i2s_reg = 283 (struct i2s_reg *)pi2s_tx->base_address; 284 285 if (data_size < FIFO_LENGTH) { 286 debug("%s : Invalid data size\n", __func__); 287 return -1; /* invalid pcm data size */ 288 } 289 290 /* fill the tx buffer before stating the tx transmit */ 291 for (i = 0; i < FIFO_LENGTH; i++) 292 writel(*data++, &i2s_reg->txd); 293 294 data_size -= FIFO_LENGTH; 295 i2s_txctrl(i2s_reg, I2S_TX_ON); 296 297 while (data_size > 0) { 298 start = get_timer(0); 299 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { 300 writel(*data++, &i2s_reg->txd); 301 data_size--; 302 } else { 303 if (get_timer(start) > TIMEOUT_I2S_TX) { 304 i2s_txctrl(i2s_reg, I2S_TX_OFF); 305 debug("%s: I2S Transfer Timeout\n", __func__); 306 return -1; 307 } 308 } 309 } 310 i2s_txctrl(i2s_reg, I2S_TX_OFF); 311 312 return 0; 313 } 314 315 int i2s_tx_init(struct i2stx_info *pi2s_tx) 316 { 317 int ret; 318 struct i2s_reg *i2s_reg = 319 (struct i2s_reg *)pi2s_tx->base_address; 320 321 /* Initialize GPIO for I2s */ 322 exynos_pinmux_config(PERIPH_ID_I2S1, 0); 323 324 /* Set EPLL Clock */ 325 ret = set_epll_clk(pi2s_tx->audio_pll_clk); 326 if (ret != 0) { 327 debug("%s: epll clock set rate falied\n", __func__); 328 return -1; 329 } 330 331 /* Select Clk Source for Audio1 */ 332 set_i2s_clk_source(); 333 334 /* Set Prescaler to get MCLK */ 335 set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk, 336 (pi2s_tx->samplingrate * (pi2s_tx->rfs))); 337 338 /* Configure I2s format */ 339 ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | 340 SND_SOC_DAIFMT_CBM_CFM)); 341 if (ret == 0) { 342 i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs); 343 ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample); 344 if (ret != 0) { 345 debug("%s:set sample rate failed\n", __func__); 346 return -1; 347 } 348 349 i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs); 350 /* disable i2s transfer flag and flush the fifo */ 351 i2s_txctrl(i2s_reg, I2S_TX_OFF); 352 i2s_fifo(i2s_reg, FIC_TXFLUSH); 353 } else { 354 debug("%s: failed\n", __func__); 355 } 356 357 return ret; 358 } 359