1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * max98095.c -- MAX98095 ALSA SoC Audio driver 4 * 5 * Copyright 2011 Maxim Integrated Products 6 * 7 * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com) 8 */ 9 10 #include <common.h> 11 #include <audio_codec.h> 12 #include <dm.h> 13 #include <div64.h> 14 #include <fdtdec.h> 15 #include <i2c.h> 16 #include <sound.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/cpu.h> 21 #include <asm/arch/power.h> 22 #include "i2s.h" 23 #include "max98095.h" 24 25 /* Index 0 is reserved. */ 26 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 27 88200, 96000}; 28 29 /* 30 * codec mclk clock divider coefficients based on sampling rate 31 * 32 * @param rate sampling rate 33 * @param value address of indexvalue to be stored 34 * 35 * @return 0 for success or negative error code. 36 */ 37 static int rate_value(int rate, u8 *value) 38 { 39 int i; 40 41 for (i = 1; i < ARRAY_SIZE(rate_table); i++) { 42 if (rate_table[i] >= rate) { 43 *value = i; 44 return 0; 45 } 46 } 47 *value = 1; 48 49 return -EINVAL; 50 } 51 52 /* 53 * Sets hw params for max98095 54 * 55 * @param priv max98095 information pointer 56 * @param rate Sampling rate 57 * @param bits_per_sample Bits per sample 58 * 59 * @return 0 for success or negative error code. 60 */ 61 static int max98095_hw_params(struct maxim_priv *priv, 62 enum en_max_audio_interface aif_id, 63 unsigned int rate, unsigned int bits_per_sample) 64 { 65 u8 regval; 66 int error; 67 unsigned short M98095_DAI_CLKMODE; 68 unsigned short M98095_DAI_FORMAT; 69 unsigned short M98095_DAI_FILTERS; 70 71 if (aif_id == AIF1) { 72 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE; 73 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT; 74 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS; 75 } else { 76 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE; 77 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT; 78 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS; 79 } 80 81 switch (bits_per_sample) { 82 case 16: 83 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0); 84 break; 85 case 24: 86 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 87 M98095_DAI_WS); 88 break; 89 default: 90 debug("%s: Illegal bits per sample %d.\n", 91 __func__, bits_per_sample); 92 return -EINVAL; 93 } 94 95 if (rate_value(rate, ®val)) { 96 debug("%s: Failed to set sample rate to %d.\n", 97 __func__, rate); 98 return -EINVAL; 99 } 100 priv->rate = rate; 101 102 error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK, 103 regval); 104 105 /* Update sample rate mode */ 106 if (rate < 50000) 107 error |= maxim_bic_or(priv, M98095_DAI_FILTERS, 108 M98095_DAI_DHF, 0); 109 else 110 error |= maxim_bic_or(priv, M98095_DAI_FILTERS, 111 M98095_DAI_DHF, M98095_DAI_DHF); 112 113 if (error < 0) { 114 debug("%s: Error setting hardware params.\n", __func__); 115 return -EIO; 116 } 117 118 return 0; 119 } 120 121 /* 122 * Configures Audio interface system clock for the given frequency 123 * 124 * @param priv max98095 information 125 * @param freq Sampling frequency in Hz 126 * 127 * @return 0 for success or negative error code. 128 */ 129 static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq) 130 { 131 int error = 0; 132 133 /* Requested clock frequency is already setup */ 134 if (freq == priv->sysclk) 135 return 0; 136 137 /* Setup clocks for slave mode, and using the PLL 138 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 139 * 0x02 (when master clk is 20MHz to 40MHz).. 140 * 0x03 (when master clk is 40MHz to 60MHz).. 141 */ 142 if ((freq >= 10000000) && (freq < 20000000)) { 143 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10); 144 } else if ((freq >= 20000000) && (freq < 40000000)) { 145 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20); 146 } else if ((freq >= 40000000) && (freq < 60000000)) { 147 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30); 148 } else { 149 debug("%s: Invalid master clock frequency\n", __func__); 150 return -EINVAL; 151 } 152 153 debug("%s: Clock at %uHz\n", __func__, freq); 154 155 if (error < 0) 156 return -EIO; 157 158 priv->sysclk = freq; 159 return 0; 160 } 161 162 /* 163 * Sets Max98095 I2S format 164 * 165 * @param priv max98095 information 166 * @param fmt i2S format - supports a subset of the options defined 167 * in i2s.h. 168 * 169 * @return 0 for success or negative error code. 170 */ 171 static int max98095_set_fmt(struct maxim_priv *priv, int fmt, 172 enum en_max_audio_interface aif_id) 173 { 174 u8 regval = 0; 175 int error = 0; 176 unsigned short M98095_DAI_CLKCFG_HI; 177 unsigned short M98095_DAI_CLKCFG_LO; 178 unsigned short M98095_DAI_FORMAT; 179 unsigned short M98095_DAI_CLOCK; 180 181 if (fmt == priv->fmt) 182 return 0; 183 184 priv->fmt = fmt; 185 186 if (aif_id == AIF1) { 187 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI; 188 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO; 189 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT; 190 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK; 191 } else { 192 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI; 193 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO; 194 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT; 195 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK; 196 } 197 198 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 199 case SND_SOC_DAIFMT_CBS_CFS: 200 /* Slave mode PLL */ 201 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80); 202 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00); 203 break; 204 case SND_SOC_DAIFMT_CBM_CFM: 205 /* Set to master mode */ 206 regval |= M98095_DAI_MAS; 207 break; 208 case SND_SOC_DAIFMT_CBS_CFM: 209 case SND_SOC_DAIFMT_CBM_CFS: 210 default: 211 debug("%s: Clock mode unsupported\n", __func__); 212 return -EINVAL; 213 } 214 215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 216 case SND_SOC_DAIFMT_I2S: 217 regval |= M98095_DAI_DLY; 218 break; 219 case SND_SOC_DAIFMT_LEFT_J: 220 break; 221 default: 222 debug("%s: Unrecognized format.\n", __func__); 223 return -EINVAL; 224 } 225 226 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 227 case SND_SOC_DAIFMT_NB_NF: 228 break; 229 case SND_SOC_DAIFMT_NB_IF: 230 regval |= M98095_DAI_WCI; 231 break; 232 case SND_SOC_DAIFMT_IB_NF: 233 regval |= M98095_DAI_BCI; 234 break; 235 case SND_SOC_DAIFMT_IB_IF: 236 regval |= M98095_DAI_BCI | M98095_DAI_WCI; 237 break; 238 default: 239 debug("%s: Unrecognized inversion settings.\n", __func__); 240 return -EINVAL; 241 } 242 243 error |= maxim_bic_or(priv, M98095_DAI_FORMAT, 244 M98095_DAI_MAS | M98095_DAI_DLY | 245 M98095_DAI_BCI | M98095_DAI_WCI, regval); 246 247 error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64); 248 249 if (error < 0) { 250 debug("%s: Error setting i2s format.\n", __func__); 251 return -EIO; 252 } 253 254 return 0; 255 } 256 257 /* 258 * resets the audio codec 259 * 260 * @param priv Private data for driver 261 * @return 0 for success or negative error code. 262 */ 263 static int max98095_reset(struct maxim_priv *priv) 264 { 265 int i, ret; 266 267 /* 268 * Gracefully reset the DSP core and the codec hardware in a proper 269 * sequence. 270 */ 271 ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0); 272 if (ret != 0) { 273 debug("%s: Failed to reset DSP: %d\n", __func__, ret); 274 return ret; 275 } 276 277 ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0); 278 if (ret != 0) { 279 debug("%s: Failed to reset codec: %d\n", __func__, ret); 280 return ret; 281 } 282 283 /* 284 * Reset to hardware default for registers, as there is not a soft 285 * reset hardware control register. 286 */ 287 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 288 ret = maxim_i2c_write(priv, i, 0); 289 if (ret < 0) { 290 debug("%s: Failed to reset: %d\n", __func__, ret); 291 return ret; 292 } 293 } 294 295 return 0; 296 } 297 298 /* 299 * Intialise max98095 codec device 300 * 301 * @param priv max98095 information 302 * @return 0 for success or negative error code. 303 */ 304 static int max98095_device_init(struct maxim_priv *priv) 305 { 306 unsigned char id; 307 int ret; 308 309 /* Enable codec clock */ 310 set_xclkout(); 311 312 /* reset the codec, the DSP core, and disable all interrupts */ 313 ret = max98095_reset(priv); 314 if (ret != 0) { 315 debug("Reset\n"); 316 return ret; 317 } 318 319 /* initialize private data */ 320 priv->sysclk = -1U; 321 priv->rate = -1U; 322 priv->fmt = -1U; 323 324 ret = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id); 325 if (ret < 0) { 326 debug("%s: Failure reading hardware revision: %d\n", 327 __func__, id); 328 return ret; 329 } 330 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A'); 331 332 return 0; 333 } 334 335 static int max98095_setup_interface(struct maxim_priv *priv, 336 enum en_max_audio_interface aif_id) 337 { 338 int error; 339 340 error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV); 341 342 /* 343 * initialize registers to hardware default configuring audio 344 * interface2 to DAC 345 */ 346 if (aif_id == AIF1) 347 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR, 348 M98095_DAI1L_TO_DACL | 349 M98095_DAI1R_TO_DACR); 350 else 351 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR, 352 M98095_DAI2M_TO_DACL | 353 M98095_DAI2M_TO_DACR); 354 355 error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT, 356 M98095_SPK_SPREADSPECTRUM); 357 error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL); 358 if (aif_id == AIF1) 359 error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG, 360 M98095_S1NORMAL | M98095_SDATA); 361 else 362 error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG, 363 M98095_S2NORMAL | M98095_SDATA); 364 365 /* take the codec out of the shut down */ 366 error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN, 367 M98095_SHDNRUN); 368 /* 369 * route DACL and DACR output to HO and Speakers 370 * Ordering: DACL, DACR, DACL, DACR 371 */ 372 error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01); 373 error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01); 374 error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01); 375 error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01); 376 377 /* power Enable */ 378 error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3); 379 380 /* set Volume */ 381 error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15); 382 error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15); 383 error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16); 384 error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16); 385 386 /* Enable DAIs */ 387 error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30); 388 if (aif_id == AIF1) 389 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01); 390 else 391 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07); 392 393 if (error < 0) 394 return -EIO; 395 396 return 0; 397 } 398 399 static int max98095_do_init(struct maxim_priv *priv, 400 enum en_max_audio_interface aif_id, 401 int sampling_rate, int mclk_freq, 402 int bits_per_sample) 403 { 404 int ret = 0; 405 406 ret = max98095_setup_interface(priv, aif_id); 407 if (ret < 0) { 408 debug("%s: max98095 setup interface failed\n", __func__); 409 return ret; 410 } 411 412 ret = max98095_set_sysclk(priv, mclk_freq); 413 if (ret < 0) { 414 debug("%s: max98095 codec set sys clock failed\n", __func__); 415 return ret; 416 } 417 418 ret = max98095_hw_params(priv, aif_id, sampling_rate, 419 bits_per_sample); 420 421 if (ret == 0) { 422 ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S | 423 SND_SOC_DAIFMT_NB_NF | 424 SND_SOC_DAIFMT_CBS_CFS, 425 aif_id); 426 } 427 428 return ret; 429 } 430 431 static int max98095_set_params(struct udevice *dev, int interface, int rate, 432 int mclk_freq, int bits_per_sample, 433 uint channels) 434 { 435 struct maxim_priv *priv = dev_get_priv(dev); 436 437 return max98095_do_init(priv, interface, rate, mclk_freq, 438 bits_per_sample); 439 } 440 441 static int max98095_probe(struct udevice *dev) 442 { 443 struct maxim_priv *priv = dev_get_priv(dev); 444 int ret; 445 446 priv->dev = dev; 447 ret = max98095_device_init(priv); 448 if (ret < 0) { 449 debug("%s: max98095 codec chip init failed\n", __func__); 450 return ret; 451 } 452 453 return 0; 454 } 455 456 static const struct audio_codec_ops max98095_ops = { 457 .set_params = max98095_set_params, 458 }; 459 460 static const struct udevice_id max98095_ids[] = { 461 { .compatible = "maxim,max98095" }, 462 { } 463 }; 464 465 U_BOOT_DRIVER(max98095) = { 466 .name = "max98095", 467 .id = UCLASS_AUDIO_CODEC, 468 .of_match = max98095_ids, 469 .probe = max98095_probe, 470 .ops = &max98095_ops, 471 .priv_auto_alloc_size = sizeof(struct maxim_priv), 472 }; 473