1 /* 2 * max98095.c -- MAX98095 ALSA SoC Audio driver 3 * 4 * Copyright 2011 Maxim Integrated Products 5 * 6 * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #include <asm/arch/clk.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/power.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <common.h> 18 #include <div64.h> 19 #include <fdtdec.h> 20 #include <i2c.h> 21 #include <sound.h> 22 #include "i2s.h" 23 #include "max98095.h" 24 25 enum max98095_type { 26 MAX98095, 27 }; 28 29 struct max98095_priv { 30 enum max98095_type devtype; 31 unsigned int sysclk; 32 unsigned int rate; 33 unsigned int fmt; 34 }; 35 36 static struct sound_codec_info g_codec_info; 37 struct max98095_priv g_max98095_info; 38 unsigned int g_max98095_i2c_dev_addr; 39 40 /* Index 0 is reserved. */ 41 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, 42 88200, 96000}; 43 44 /* 45 * Writes value to a device register through i2c 46 * 47 * @param reg reg number to be write 48 * @param data data to be writen to the above registor 49 * 50 * @return int value 1 for change, 0 for no change or negative error code. 51 */ 52 static int max98095_i2c_write(unsigned int reg, unsigned char data) 53 { 54 debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n", 55 __func__, reg, data); 56 return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1); 57 } 58 59 /* 60 * Read a value from a device register through i2c 61 * 62 * @param reg reg number to be read 63 * @param data address of read data to be stored 64 * 65 * @return int value 0 for success, -1 in case of error. 66 */ 67 static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data) 68 { 69 int ret; 70 71 ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1); 72 if (ret != 0) { 73 debug("%s: Error while reading register %#04x\n", 74 __func__, reg); 75 return -1; 76 } 77 78 return 0; 79 } 80 81 /* 82 * update device register bits through i2c 83 * 84 * @param reg codec register 85 * @param mask register mask 86 * @param value new value 87 * 88 * @return int value 0 for success, non-zero error code. 89 */ 90 static int max98095_update_bits(unsigned int reg, unsigned char mask, 91 unsigned char value) 92 { 93 int change, ret = 0; 94 unsigned char old, new; 95 96 if (max98095_i2c_read(reg, &old) != 0) 97 return -1; 98 new = (old & ~mask) | (value & mask); 99 change = (old != new) ? 1 : 0; 100 if (change) 101 ret = max98095_i2c_write(reg, new); 102 if (ret < 0) 103 return ret; 104 105 return change; 106 } 107 108 /* 109 * codec mclk clock divider coefficients based on sampling rate 110 * 111 * @param rate sampling rate 112 * @param value address of indexvalue to be stored 113 * 114 * @return 0 for success or negative error code. 115 */ 116 static int rate_value(int rate, u8 *value) 117 { 118 int i; 119 120 for (i = 1; i < ARRAY_SIZE(rate_table); i++) { 121 if (rate_table[i] >= rate) { 122 *value = i; 123 return 0; 124 } 125 } 126 *value = 1; 127 128 return -1; 129 } 130 131 /* 132 * Sets hw params for max98095 133 * 134 * @param max98095 max98095 information pointer 135 * @param rate Sampling rate 136 * @param bits_per_sample Bits per sample 137 * 138 * @return -1 for error and 0 Success. 139 */ 140 static int max98095_hw_params(struct max98095_priv *max98095, 141 unsigned int rate, unsigned int bits_per_sample) 142 { 143 u8 regval; 144 int error; 145 146 switch (bits_per_sample) { 147 case 16: 148 error = max98095_update_bits(M98095_034_DAI2_FORMAT, 149 M98095_DAI_WS, 0); 150 break; 151 case 24: 152 error = max98095_update_bits(M98095_034_DAI2_FORMAT, 153 M98095_DAI_WS, M98095_DAI_WS); 154 break; 155 default: 156 debug("%s: Illegal bits per sample %d.\n", 157 __func__, bits_per_sample); 158 return -1; 159 } 160 161 if (rate_value(rate, ®val)) { 162 debug("%s: Failed to set sample rate to %d.\n", 163 __func__, rate); 164 return -1; 165 } 166 max98095->rate = rate; 167 168 error |= max98095_update_bits(M98095_031_DAI2_CLKMODE, 169 M98095_CLKMODE_MASK, regval); 170 171 /* Update sample rate mode */ 172 if (rate < 50000) 173 error |= max98095_update_bits(M98095_038_DAI2_FILTERS, 174 M98095_DAI_DHF, 0); 175 else 176 error |= max98095_update_bits(M98095_038_DAI2_FILTERS, 177 M98095_DAI_DHF, M98095_DAI_DHF); 178 179 if (error < 0) { 180 debug("%s: Error setting hardware params.\n", __func__); 181 return -1; 182 } 183 184 return 0; 185 } 186 187 /* 188 * Configures Audio interface system clock for the given frequency 189 * 190 * @param max98095 max98095 information 191 * @param freq Sampling frequency in Hz 192 * 193 * @return -1 for error and 0 success. 194 */ 195 static int max98095_set_sysclk(struct max98095_priv *max98095, 196 unsigned int freq) 197 { 198 int error = 0; 199 200 /* Requested clock frequency is already setup */ 201 if (freq == max98095->sysclk) 202 return 0; 203 204 /* Setup clocks for slave mode, and using the PLL 205 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 206 * 0x02 (when master clk is 20MHz to 40MHz).. 207 * 0x03 (when master clk is 40MHz to 60MHz).. 208 */ 209 if ((freq >= 10000000) && (freq < 20000000)) { 210 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10); 211 } else if ((freq >= 20000000) && (freq < 40000000)) { 212 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20); 213 } else if ((freq >= 40000000) && (freq < 60000000)) { 214 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30); 215 } else { 216 debug("%s: Invalid master clock frequency\n", __func__); 217 return -1; 218 } 219 220 debug("%s: Clock at %uHz\n", __func__, freq); 221 222 if (error < 0) 223 return -1; 224 225 max98095->sysclk = freq; 226 return 0; 227 } 228 229 /* 230 * Sets Max98095 I2S format 231 * 232 * @param max98095 max98095 information 233 * @param fmt i2S format - supports a subset of the options defined 234 * in i2s.h. 235 * 236 * @return -1 for error and 0 Success. 237 */ 238 static int max98095_set_fmt(struct max98095_priv *max98095, int fmt) 239 { 240 u8 regval = 0; 241 int error = 0; 242 243 if (fmt == max98095->fmt) 244 return 0; 245 246 max98095->fmt = fmt; 247 248 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 249 case SND_SOC_DAIFMT_CBS_CFS: 250 /* Slave mode PLL */ 251 error |= max98095_i2c_write(M98095_032_DAI2_CLKCFG_HI, 252 0x80); 253 error |= max98095_i2c_write(M98095_033_DAI2_CLKCFG_LO, 254 0x00); 255 break; 256 case SND_SOC_DAIFMT_CBM_CFM: 257 /* Set to master mode */ 258 regval |= M98095_DAI_MAS; 259 break; 260 case SND_SOC_DAIFMT_CBS_CFM: 261 case SND_SOC_DAIFMT_CBM_CFS: 262 default: 263 debug("%s: Clock mode unsupported\n", __func__); 264 return -1; 265 } 266 267 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 268 case SND_SOC_DAIFMT_I2S: 269 regval |= M98095_DAI_DLY; 270 break; 271 case SND_SOC_DAIFMT_LEFT_J: 272 break; 273 default: 274 debug("%s: Unrecognized format.\n", __func__); 275 return -1; 276 } 277 278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 279 case SND_SOC_DAIFMT_NB_NF: 280 break; 281 case SND_SOC_DAIFMT_NB_IF: 282 regval |= M98095_DAI_WCI; 283 break; 284 case SND_SOC_DAIFMT_IB_NF: 285 regval |= M98095_DAI_BCI; 286 break; 287 case SND_SOC_DAIFMT_IB_IF: 288 regval |= M98095_DAI_BCI | M98095_DAI_WCI; 289 break; 290 default: 291 debug("%s: Unrecognized inversion settings.\n", __func__); 292 return -1; 293 } 294 295 error |= max98095_update_bits(M98095_034_DAI2_FORMAT, 296 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 297 M98095_DAI_WCI, regval); 298 299 error |= max98095_i2c_write(M98095_035_DAI2_CLOCK, 300 M98095_DAI_BSEL64); 301 302 if (error < 0) { 303 debug("%s: Error setting i2s format.\n", __func__); 304 return -1; 305 } 306 307 return 0; 308 } 309 310 /* 311 * resets the audio codec 312 * 313 * @return -1 for error and 0 success. 314 */ 315 static int max98095_reset(void) 316 { 317 int i, ret; 318 319 /* 320 * Gracefully reset the DSP core and the codec hardware in a proper 321 * sequence. 322 */ 323 ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0); 324 if (ret != 0) { 325 debug("%s: Failed to reset DSP: %d\n", __func__, ret); 326 return ret; 327 } 328 329 ret = max98095_i2c_write(M98095_097_PWR_SYS, 0); 330 if (ret != 0) { 331 debug("%s: Failed to reset codec: %d\n", __func__, ret); 332 return ret; 333 } 334 335 /* 336 * Reset to hardware default for registers, as there is not a soft 337 * reset hardware control register. 338 */ 339 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 340 ret = max98095_i2c_write(i, 0); 341 if (ret < 0) { 342 debug("%s: Failed to reset: %d\n", __func__, ret); 343 return ret; 344 } 345 } 346 347 return 0; 348 } 349 350 /* 351 * Intialise max98095 codec device 352 * 353 * @param max98095 max98095 information 354 * 355 * @returns -1 for error and 0 Success. 356 */ 357 static int max98095_device_init(struct max98095_priv *max98095) 358 { 359 unsigned char id; 360 int error = 0; 361 362 /* reset the codec, the DSP core, and disable all interrupts */ 363 error = max98095_reset(); 364 if (error != 0) { 365 debug("Reset\n"); 366 return error; 367 } 368 369 /* initialize private data */ 370 max98095->sysclk = -1U; 371 max98095->rate = -1U; 372 max98095->fmt = -1U; 373 374 error = max98095_i2c_read(M98095_0FF_REV_ID, &id); 375 if (error < 0) { 376 debug("%s: Failure reading hardware revision: %d\n", 377 __func__, id); 378 goto err_access; 379 } 380 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A'); 381 382 error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV); 383 384 /* 385 * initialize registers to hardware default configuring audio 386 * interface2 to DAC 387 */ 388 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, 389 M98095_DAI2M_TO_DACL|M98095_DAI2M_TO_DACR); 390 391 error |= max98095_i2c_write(M98095_092_PWR_EN_OUT, 392 M98095_SPK_SPREADSPECTRUM); 393 error |= max98095_i2c_write(M98095_045_CFG_DSP, M98095_DSPNORMAL); 394 error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL); 395 396 error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG, 397 M98095_S1NORMAL|M98095_SDATA); 398 399 error |= max98095_i2c_write(M98095_036_DAI2_IOCFG, 400 M98095_S2NORMAL|M98095_SDATA); 401 402 error |= max98095_i2c_write(M98095_040_DAI3_IOCFG, 403 M98095_S3NORMAL|M98095_SDATA); 404 405 /* take the codec out of the shut down */ 406 error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN, 407 M98095_SHDNRUN); 408 /* route DACL and DACR output to HO and Spekers */ 409 error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */ 410 error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */ 411 error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */ 412 error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */ 413 414 /* power Enable */ 415 error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3); 416 417 /* set Volume */ 418 error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15); 419 error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15); 420 error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16); 421 error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16); 422 423 /* Enable DAIs */ 424 error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30); 425 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07); 426 427 err_access: 428 if (error < 0) 429 return -1; 430 431 return 0; 432 } 433 434 static int max98095_do_init(struct sound_codec_info *pcodec_info, 435 int sampling_rate, int mclk_freq, 436 int bits_per_sample) 437 { 438 int ret = 0; 439 440 /* Enable codec clock */ 441 set_xclkout(); 442 443 /* shift the device address by 1 for 7 bit addressing */ 444 g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1; 445 446 if (pcodec_info->codec_type == CODEC_MAX_98095) 447 g_max98095_info.devtype = MAX98095; 448 else { 449 debug("%s: Codec id [%d] not defined\n", __func__, 450 pcodec_info->codec_type); 451 return -1; 452 } 453 454 ret = max98095_device_init(&g_max98095_info); 455 if (ret < 0) { 456 debug("%s: max98095 codec chip init failed\n", __func__); 457 return ret; 458 } 459 460 ret = max98095_set_sysclk(&g_max98095_info, mclk_freq); 461 if (ret < 0) { 462 debug("%s: max98095 codec set sys clock failed\n", __func__); 463 return ret; 464 } 465 466 ret = max98095_hw_params(&g_max98095_info, sampling_rate, 467 bits_per_sample); 468 469 if (ret == 0) { 470 ret = max98095_set_fmt(&g_max98095_info, 471 SND_SOC_DAIFMT_I2S | 472 SND_SOC_DAIFMT_NB_NF | 473 SND_SOC_DAIFMT_CBS_CFS); 474 } 475 476 return ret; 477 } 478 479 static int get_max98095_codec_values(struct sound_codec_info *pcodec_info, 480 const void *blob) 481 { 482 int error = 0; 483 #ifdef CONFIG_OF_CONTROL 484 enum fdt_compat_id compat; 485 int node; 486 int parent; 487 488 /* Get the node from FDT for codec */ 489 node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC); 490 if (node <= 0) { 491 debug("EXYNOS_SOUND: No node for codec in device tree\n"); 492 debug("node = %d\n", node); 493 return -1; 494 } 495 496 parent = fdt_parent_offset(blob, node); 497 if (parent < 0) { 498 debug("%s: Cannot find node parent\n", __func__); 499 return -1; 500 } 501 502 compat = fdtdec_lookup(blob, parent); 503 switch (compat) { 504 case COMPAT_SAMSUNG_S3C2440_I2C: 505 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); 506 error |= pcodec_info->i2c_bus; 507 debug("i2c bus = %d\n", pcodec_info->i2c_bus); 508 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, 509 "reg", 0); 510 error |= pcodec_info->i2c_dev_addr; 511 debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr); 512 break; 513 default: 514 debug("%s: Unknown compat id %d\n", __func__, compat); 515 return -1; 516 } 517 #else 518 pcodec_info->i2c_bus = AUDIO_I2C_BUS; 519 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; 520 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); 521 #endif 522 pcodec_info->codec_type = CODEC_MAX_98095; 523 if (error == -1) { 524 debug("fail to get max98095 codec node properties\n"); 525 return -1; 526 } 527 528 return 0; 529 } 530 531 /* max98095 Device Initialisation */ 532 int max98095_init(const void *blob, int sampling_rate, int mclk_freq, 533 int bits_per_sample) 534 { 535 int ret; 536 int old_bus = i2c_get_bus_num(); 537 struct sound_codec_info *pcodec_info = &g_codec_info; 538 539 if (get_max98095_codec_values(pcodec_info, blob) < 0) { 540 debug("FDT Codec values failed\n"); 541 return -1; 542 } 543 544 i2c_set_bus_num(pcodec_info->i2c_bus); 545 ret = max98095_do_init(pcodec_info, sampling_rate, mclk_freq, 546 bits_per_sample); 547 i2c_set_bus_num(old_bus); 548 549 return ret; 550 } 551