1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Intel Broadwell I2S driver 4 * 5 * Copyright 2019 Google LLC 6 * 7 * Modified from dc i2s/broadwell/broadwell.h 8 */ 9 10 #ifndef __BROADWELL_I2S_H__ 11 #define __BROADWELL_I2S_H__ 12 13 enum { 14 SSP_FIFO_SIZE = 7, 15 }; 16 17 enum frame_sync_rel_timing_t { 18 NEXT_FRMS_AFTER_END_OF_T4 = 0, 19 NEXT_FRMS_WITH_LSB_PREVIOUS_FRM, 20 }; 21 22 enum frame_sync_pol_t { 23 SSP_FRMS_ACTIVE_LOW = 0, 24 SSP_FRMS_ACTIVE_HIGH, 25 }; 26 27 enum end_transfer_state_t { 28 SSP_END_TRANSFER_STATE_LOW = 0, 29 SSP_END_TRANSFER_STATE_PEVIOUS_BIT, 30 }; 31 32 enum clock_mode_t { 33 /* Data driven (falling), data sampled (rising), idle state (low) */ 34 SCLK_MODE_DDF_DSR_ISL, 35 /* Data driven (rising), data sampled (falling), idle state (low) */ 36 SCLK_MODE_DDR_DSF_ISL, 37 /* Data driven (rising), data sampled (falling), idle state (high) */ 38 SCLK_MODE_DDR_DSF_ISH, 39 /* Data driven (falling), data sampled (rising), idle state (high) */ 40 SCLK_MODE_DDF_DSR_ISH, 41 }; 42 43 struct i2s_shim_regs { 44 u32 csr; /* 0x00 */ 45 u32 reserved0[29]; /* 0x14 - 0x77 */ 46 u32 clkctl; /* 0x78 */ 47 u32 reserved1; /* 0x7c */ 48 u32 cs2; /* 0x80 */ 49 }; 50 51 struct broadwell_i2s_regs { 52 u32 sscr0; /* 0x00 */ 53 u32 sscr1; /* 0x04 */ 54 u32 sssr; /* 0x08 */ 55 u32 ssitr; /* 0x0c */ 56 u32 ssdr; /* 0x10 */ 57 u32 reserved0[5]; /* 0x14 - 0x27 */ 58 u32 ssto; /* 0x28 */ 59 u32 sspsp; /* 0x2c */ 60 u32 sstsa; /* 0x30 */ 61 u32 ssrsa; /* 0x34 */ 62 u32 sstss; /* 0x38 */ 63 u32 sscr2; /* 0x40 */ 64 u32 sspsp2; /* 0x44 */ 65 }; 66 67 /* SHIM Configuration & Status */ 68 enum { 69 /* Low Power Clock Select */ 70 SHIM_CS_LPCS = 1 << 31, 71 /* SSP Force Clock Running */ 72 SHIM_CS_SFCR_SSP1 = 1 << 28, 73 SHIM_CS_SFCR_SSP0 = 1 << 27, 74 /* SSP1 IO Clock Select */ 75 SHIM_CS_S1IOCS = 1 << 23, 76 /* SSP0 IO Clock Select */ 77 SHIM_CS_S0IOCS = 1 << 21, 78 /* Parity Check Enable */ 79 SHIM_CS_PCE = 1 << 15, 80 /* SSP DMA or PIO Mode */ 81 SHIM_CS_SDPM_PIO_SSP1 = 1 << 12, 82 SHIM_CS_SDPM_DMA_SSP1 = 0 << 12, 83 SHIM_CS_SDPM_PIO_SSP0 = 1 << 11, 84 SHIM_CS_SDPM_DMA_SSP0 = 0 << 11, 85 /* Run / Stall */ 86 SHIM_CS_STALL = 1 << 10, 87 /* DSP Clock Select */ 88 SHIM_CS_DCS_DSP320_AF80 = 0 << 4, 89 SHIM_CS_DCS_DSP160_AF80 = 1 << 4, 90 SHIM_CS_DCS_DSP80_AF80 = 2 << 4, 91 SHIM_CS_DCS_DSP320_AF160 = 4 << 4, 92 SHIM_CS_DCS_DSP160_AF160 = 5 << 4, 93 SHIM_CS_DCS_DSP32_AF32 = 6 << 4, 94 SHIM_CS_DCS_MASK = 7 << 4, 95 /* SSP Base Clock Select */ 96 SHIM_CS_SBCS_SSP0_24MHZ = 1 << 3, 97 SHIM_CS_SBCS_SSP0_32MHZ = 0 << 3, 98 SHIM_CS_SBCS_SSP1_24MHZ = 1 << 2, 99 SHIM_CS_SBCS_SSP1_32MHZ = 0 << 2, 100 /* DSP Core Reset */ 101 SHIM_CS_RST = 1 << 1, 102 }; 103 104 /* SHIM Clock Control */ 105 enum { 106 /* Clock Frequency Change In Progress */ 107 SHIM_CLKCTL_CFCIP = 1 << 31, 108 /* SSP MCLK Output Select */ 109 SHIM_CLKCTL_MCLK_MASK = 0x3, 110 SHIM_CLKCTL_MCLK_SHIFT = 24, 111 SHIM_CLKCTL_MCLK_DISABLED = 0 << 24, 112 SHIM_CLKCTL_MCLK_6MHZ = 1 << 24, 113 SHIM_CLKCTL_MCLK_12MHZ = 2 << 24, 114 SHIM_CLKCTL_MCLK_24MHZ = 3 << 24, 115 /* DSP Core Prevent Local Clock Gating */ 116 SHIM_CLKCTL_DCPLCG = 1 << 18, 117 /* SSP Clock Output Enable */ 118 SHIM_CLKCTL_SCOE_SSP1 = 1 << 17, 119 SHIM_CLKCTL_SCOE_SSP0 = 1 << 16, 120 /* DMA Engine Force Local Clock Gating */ 121 SHIM_CLKCTL_DEFLCGB_DMA1_CGE = 0 << 6, 122 SHIM_CLKCTL_DEFLCGB_DMA1_CGD = 1 << 6, 123 SHIM_CLKCTL_DEFLCGB_DMA0_CGE = 0 << 5, 124 SHIM_CLKCTL_DEFLCGB_DMA0_CGD = 1 << 5, 125 /* SSP Force Local Clock Gating */ 126 SHIM_CLKCTL_SFLCGB_SSP1_CGE = 0 << 1, 127 SHIM_CLKCTL_SFLCGB_SSP1_CGD = 1 << 1, 128 SHIM_CLKCTL_SFLCGB_SSP0_CGE = 0 << 0, 129 SHIM_CLKCTL_SFLCGB_SSP0_CGD = 1 << 0, 130 131 /* Reserved bits: 30:26, 23:19, 15:7, 4:2 */ 132 SHIM_CLKCTL_RESERVED = 0x1f << 26 | 0x1f << 19 | 0x1ff << 7 | 0x7 << 2, 133 }; 134 135 /* SSP Status */ 136 enum { 137 /* Bit Count Error */ 138 SSP_SSS_BCE = 1 << 23, 139 /* Clock Sync Statu s*/ 140 SSP_SSS_CSS = 1 << 22, 141 /* Transmit FIFO Underrun */ 142 SSP_SSS_TUR = 1 << 21, 143 /* End Of Chain */ 144 SSP_SSS_EOC = 1 << 20, 145 /* Receiver Time-out Interrupt */ 146 SSP_SSS_TINT = 1 << 19, 147 /* Peripheral Trailing Byte Interrupt */ 148 SSP_SSS_PINT = 1 << 18, 149 /* Received FIFO Level */ 150 SSP_RFL_MASK = 0xf, 151 SSP_RFL_SHIFT = 12, 152 /* Transmit FIFO Level */ 153 SSP_TFL_MASK = 0xf, 154 SSP_TFL_SHIFT = 8, 155 /* Receive FIFO Overrun */ 156 SSP_SSS_ROR = 1 << 7, 157 /* Receive FIFO Service Request */ 158 SSP_SSS_RFS = 1 << 6, 159 /* Transmit FIFO Service Request */ 160 SSP_SSS_TFS = 1 << 5, 161 /* SSP Busy */ 162 SSP_SSS_BSY = 1 << 4, 163 /* Receive FIFO Not Empty */ 164 SSP_SSS_RNE = 1 << 3, 165 /* Transmit FIFO Not Full */ 166 SSP_SSS_TNF = 1 << 2, 167 }; 168 169 /* SSP Control 0 */ 170 enum { 171 /* Mode */ 172 SSP_SSC0_MODE_NORMAL = 0 << 31, 173 SSP_SSC0_MODE_NETWORK = 1 << 31, 174 /* Audio Clock Select */ 175 SSP_SSC0_ACS_PCH = 0 << 30, 176 /* Frame Rate Divider Control (0-7) */ 177 SSP_SSC0_FRDC_MASK = 0x7, 178 SSP_SSC0_FRDC_SHIFT = 24, 179 SSP_SSC0_FRDC_STEREO = 1 << 24, 180 /* Transmit FIFO Underrun Interrupt Mask */ 181 SSP_SSC0_TIM = 1 << 23, 182 /* Receive FIFO Underrun Interrupt Mask */ 183 SSP_SSC0_RIM = 1 << 22, 184 /* Network Clock Select */ 185 SSP_SSC0_NCS_PCH = 0 << 21, 186 /* Extended Data Size Select */ 187 SSP_SSC0_EDSS = 1 << 20, 188 /* Serial Clock Rate (0-4095) */ 189 SSP_SSC0_SCR_SHIFT = 8, 190 SSP_SSC0_SCR_MASK = 0xfff << SSP_SSC0_SCR_SHIFT, 191 /* Synchronous Serial Port Enable */ 192 SSP_SSC0_SSE = 1 << 7, 193 /* External Clock Select */ 194 SSP_SSC0_ECS_PCH = 0 << 6, 195 /* Frame Format */ 196 SSP_SSC0_FRF_MOTOROLA_SPI = 0 << 4, 197 SSP_SSC0_FRF_TI_SSP = 1 << 4, 198 SSP_SSC0_FRF_NS_MICROWIRE = 2 << 4, 199 SSP_SSC0_FRF_PSP = 3 << 4, 200 /* Data Size Select */ 201 SSP_SSC0_DSS_SHIFT = 0, 202 SSP_SSC0_DSS_MASK = 0xf << SSP_SSC0_DSS_SHIFT, 203 }; 204 205 /* SSP Control 1 */ 206 enum { 207 /* TXD Tristate Enable on Last Phase */ 208 SSP_SSC1_TTELP = 1 << 31, 209 /* TXD Tristate Enable */ 210 SSP_SSC1_TTE = 1 << 30, 211 /* Enable Bit Count Error Interrupt */ 212 SSP_SSC1_EBCEI = 1 << 29, 213 /* Slave Clock Running */ 214 SSP_SSC1_SCFR = 1 << 28, 215 /* Enable Clock Request A */ 216 SSP_SSC1_ECRA = 1 << 27, 217 /* Enable Clock Request B */ 218 SSP_SSC1_ECRB = 1 << 26, 219 /* SSPCLK Direction */ 220 SSP_SSC1_SCLKDIR_SLAVE = 1 << 25, 221 SSP_SSC1_SCLKDIR_MASTER = 0 << 25, 222 /* SSPFRM Direction */ 223 SSP_SSC1_SFRMDIR_SLAVE = 1 << 24, 224 SSP_SSC1_SFRMDIR_MASTER = 0 << 24, 225 /* Receive without Transmit */ 226 SSP_SSC1_RWOT = 1 << 23, 227 /* Trailing Byte */ 228 SSP_SSC1_TRAIL = 1 << 22, 229 /* DMA Tx Service Request Enable */ 230 SSP_SSC1_TSRE = 1 << 21, 231 /* DMA Rx Service Request Enable */ 232 SSP_SSC1_RSRE = 1 << 20, 233 /* Receiver Timeout Interrupt Enable */ 234 SSP_SSC1_TINTE = 1 << 19, 235 /* Periph. Trailing Byte Int. Enable */ 236 SSP_SSC1_PINTE = 1 << 18, 237 /* Invert Frame Signal */ 238 SSP_SSC1_IFS = 1 << 16, 239 /* Select FIFO for EFWR: test mode */ 240 SSP_SSC1_STRF = 1 << 15, 241 /* Enable FIFO Write/Read: test mode */ 242 SSP_SSC1_EFWR = 1 << 14, 243 /* Receive FIFO Trigger Threshold */ 244 SSP_SSC1_RFT_SHIFT = 10, 245 SSP_SSC1_RFT_MASK = 0xf << SSP_SSC1_RFT_SHIFT, 246 /* Transmit FIFO Trigger Threshold */ 247 SSP_SSC1_TFT_SHIFT = 6, 248 SSP_SSC1_TFT_MASK = 0xf << SSP_SSC1_TFT_SHIFT, 249 /* Microwire Transmit Data Size */ 250 SSP_SSC1_MWDS = 1 << 5, 251 /* Motorola SPI SSPSCLK Phase Setting*/ 252 SSP_SSC1_SPH = 1 << 4, 253 /* Motorola SPI SSPSCLK Polarity */ 254 SSP_SSC1_SPO = 1 << 3, 255 /* Loopback mode: test mode */ 256 SSP_SSC1_LBM = 1 << 2, 257 /* Transmit FIFO Interrupt Enable */ 258 SSP_SSC1_TIE = 1 << 1, 259 /* Receive FIFO Interrupt Enable */ 260 SSP_SSC1_RIE = 1 << 0, 261 262 SSP_SSC1_RESERVED = 17 << 1, 263 }; 264 265 /* SSP Programmable Serial Protocol */ 266 enum { 267 /* Extended Dummy Stop (0-31) */ 268 SSP_PSP_EDYMSTOP_SHIFT = 26, 269 SSP_PSP_EDMYSTOP_MASK = 0x7 << SSP_PSP_EDYMSTOP_SHIFT, 270 /* Frame Sync Relative Timing */ 271 SSP_PSP_FSRT = 1 << 25, 272 /* Dummy Stop low bits */ 273 SSP_PSP_DMYSTOP_SHIFT = 23, 274 SSP_PSP_DMYSTOP_MASK = 0x3 << SSP_PSP_DMYSTOP_SHIFT, 275 /* Serial Frame Width */ 276 SSP_PSP_SFRMWDTH_SHIFT = 16, 277 SSP_PSP_SFRMWDTH_MASK = 0x3f << SSP_PSP_SFRMWDTH_SHIFT, 278 /* Serial Frame Delay */ 279 SSP_PSP_SFRMDLY_MASK = 0x7f, 280 SSP_PSP_SFRMDLY_SHIFT = 9, 281 /* Start Delay */ 282 SSP_PSP_STRTDLY_MASK = 0x7, 283 SSP_PSP_STRTDLY_SHIFT = 4, 284 /* End of Transfer Data State */ 285 SSP_PSP_ETDS = 1 << 3, 286 /* Serial Frame Polarity */ 287 SSP_PSP_SFRMP = 1 << 2, 288 /* Serial Clock Mode */ 289 SSP_PSP_SCMODE_SHIFT = 0, 290 SSP_PSP_SCMODE_MASK = 0x3 << SSP_PSP_SCMODE_SHIFT, 291 292 SSP_PSP_RESERVED = 1 << 22, 293 }; 294 295 /* SSP TX Time Slot Active */ 296 enum { 297 SSP_SSTSA_EN = 1 << 8, 298 SSP_SSTSA_MASK = 0xff, 299 }; 300 301 #endif /* __BROADWELL_I2S_H__ */ 302